Commit 0c2fd59a authored by Dave Airlie's avatar Dave Airlie

Merge branch 'mediatek-drm-next-4.19' of...

Merge branch 'mediatek-drm-next-4.19' of https://github.com/ckhu-mediatek/linux.git-tags into drm-next

This include MT2712 SoC support and removing struct mtk_drm_fb.
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531204482.14433.6.camel@mtksdaap41
parents 54c88a02 57c7f581
...@@ -40,7 +40,7 @@ Required properties (all function blocks): ...@@ -40,7 +40,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive "mediatek,<chip>-disp-od" - overdrive
the supported chips are mt2701 and mt8173. the supported chips are mt2701, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space - reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for - interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks). merge and split function blocks).
......
...@@ -539,6 +539,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, ...@@ -539,6 +539,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int ret; int ret;
int i; int i;
if (!path)
return 0;
for (i = 0; i < path_len; i++) { for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i]; enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node; struct device_node *node;
......
...@@ -28,8 +28,12 @@ ...@@ -28,8 +28,12 @@
#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
#define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
...@@ -41,45 +45,89 @@ ...@@ -41,45 +45,89 @@
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1) #define INT_MUTEX BIT(1)
#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) #define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) #define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) #define MT8173_MUTEX_MOD_DISP_RDMA0 13
#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) #define MT8173_MUTEX_MOD_DISP_RDMA1 14
#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) #define MT8173_MUTEX_MOD_DISP_RDMA2 15
#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) #define MT8173_MUTEX_MOD_DISP_WDMA0 16
#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) #define MT8173_MUTEX_MOD_DISP_WDMA1 17
#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) #define MT8173_MUTEX_MOD_DISP_COLOR0 18
#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) #define MT8173_MUTEX_MOD_DISP_COLOR1 19
#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) #define MT8173_MUTEX_MOD_DISP_AAL 20
#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) #define MT8173_MUTEX_MOD_DISP_GAMMA 21
#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) #define MT8173_MUTEX_MOD_DISP_UFOE 22
#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) #define MT8173_MUTEX_MOD_DISP_PWM0 23
#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD BIT(25) #define MT8173_MUTEX_MOD_DISP_OD 25
#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) #define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) #define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) #define MT2712_MUTEX_MOD_DISP_OVL1 12
#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) #define MT2712_MUTEX_MOD_DISP_RDMA0 13
#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) #define MT2712_MUTEX_MOD_DISP_RDMA1 14
#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) #define MT2712_MUTEX_MOD_DISP_RDMA2 15
#define MT2712_MUTEX_MOD_DISP_WDMA0 16
#define MT2712_MUTEX_MOD_DISP_WDMA1 17
#define MT2712_MUTEX_MOD_DISP_COLOR0 18
#define MT2712_MUTEX_MOD_DISP_COLOR1 19
#define MT2712_MUTEX_MOD_DISP_AAL0 20
#define MT2712_MUTEX_MOD_DISP_UFOE 22
#define MT2712_MUTEX_MOD_DISP_PWM0 23
#define MT2712_MUTEX_MOD_DISP_PWM1 24
#define MT2712_MUTEX_MOD_DISP_OD0 25
#define MT2712_MUTEX_MOD2_DISP_AAL1 33
#define MT2712_MUTEX_MOD2_DISP_OD1 34
#define MT2701_MUTEX_MOD_DISP_OVL 3
#define MT2701_MUTEX_MOD_DISP_WDMA 6
#define MT2701_MUTEX_MOD_DISP_COLOR 7
#define MT2701_MUTEX_MOD_DISP_BLS 9
#define MT2701_MUTEX_MOD_DISP_RDMA0 10
#define MT2701_MUTEX_MOD_DISP_RDMA1 12
#define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI0 1
#define MUTEX_SOF_DSI1 2 #define MUTEX_SOF_DSI1 2
#define MUTEX_SOF_DPI0 3 #define MUTEX_SOF_DPI0 3
#define MUTEX_SOF_DPI1 4
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
#define OVL0_MOUT_EN_COLOR0 0x1 #define OVL0_MOUT_EN_COLOR0 0x1
#define OD_MOUT_EN_RDMA0 0x1 #define OD_MOUT_EN_RDMA0 0x1
#define OD1_MOUT_EN_RDMA1 BIT(16)
#define UFOE_MOUT_EN_DSI0 0x1 #define UFOE_MOUT_EN_DSI0 0x1
#define COLOR0_SEL_IN_OVL0 0x1 #define COLOR0_SEL_IN_OVL0 0x1
#define OVL1_MOUT_EN_COLOR1 0x1 #define OVL1_MOUT_EN_COLOR1 0x1
#define GAMMA_MOUT_EN_RDMA1 0x1 #define GAMMA_MOUT_EN_RDMA1 0x1
#define RDMA1_MOUT_DPI0 0x2 #define RDMA0_SOUT_DPI0 0x2
#define RDMA0_SOUT_DSI2 0x4
#define RDMA0_SOUT_DSI3 0x5
#define RDMA1_SOUT_DPI0 0x2
#define RDMA1_SOUT_DPI1 0x3
#define RDMA1_SOUT_DSI1 0x1
#define RDMA1_SOUT_DSI2 0x4
#define RDMA1_SOUT_DSI3 0x5
#define RDMA2_SOUT_DPI0 0x2
#define RDMA2_SOUT_DPI1 0x3
#define RDMA2_SOUT_DSI1 0x1
#define RDMA2_SOUT_DSI2 0x4
#define RDMA2_SOUT_DSI3 0x5
#define DPI0_SEL_IN_RDMA1 0x1 #define DPI0_SEL_IN_RDMA1 0x1
#define DPI0_SEL_IN_RDMA2 0x3
#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
#define DSI1_SEL_IN_RDMA1 0x1
#define DSI1_SEL_IN_RDMA2 0x4
#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
#define COLOR1_SEL_IN_OVL1 0x1 #define COLOR1_SEL_IN_OVL1 0x1
#define OVL_MOUT_EN_RDMA 0x1 #define OVL_MOUT_EN_RDMA 0x1
...@@ -108,12 +156,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { ...@@ -108,12 +156,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
}; };
static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
[DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
[DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
[DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
[DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
[DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
[DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
[DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
[DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
[DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
...@@ -138,7 +206,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, ...@@ -138,7 +206,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA; value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0; value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
...@@ -150,9 +218,48 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, ...@@ -150,9 +218,48 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1; value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_MOUT_DPI0; value = RDMA1_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI3;
} else { } else {
value = 0; value = 0;
} }
...@@ -172,6 +279,33 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, ...@@ -172,6 +279,33 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN; *addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA1; value = DPI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI3_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI2_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI3_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1; value = COLOR1_SEL_IN_OVL1;
...@@ -278,6 +412,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, ...@@ -278,6 +412,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]); mutex[mutex->id]);
unsigned int reg; unsigned int reg;
unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex); WARN_ON(&ddp->mutex[mutex->id] != mutex);
...@@ -288,13 +423,30 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, ...@@ -288,13 +423,30 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
case DDP_COMPONENT_DSI1: case DDP_COMPONENT_DSI1:
reg = MUTEX_SOF_DSI0; reg = MUTEX_SOF_DSI0;
break; break;
case DDP_COMPONENT_DSI2:
reg = MUTEX_SOF_DSI2;
break;
case DDP_COMPONENT_DSI3:
reg = MUTEX_SOF_DSI3;
break;
case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI0:
reg = MUTEX_SOF_DPI0; reg = MUTEX_SOF_DPI0;
break; break;
case DDP_COMPONENT_DPI1:
reg = MUTEX_SOF_DPI1;
break;
default: default:
reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); if (ddp->mutex_mod[id] < 32) {
reg |= ddp->mutex_mod[id]; offset = DISP_REG_MUTEX_MOD(mutex->id);
writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); reg = readl_relaxed(ddp->regs + offset);
reg |= 1 << ddp->mutex_mod[id];
writel_relaxed(reg, ddp->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(ddp->regs + offset);
reg |= 1 << (ddp->mutex_mod[id] - 32);
writel_relaxed(reg, ddp->regs + offset);
}
return; return;
} }
...@@ -307,20 +459,32 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, ...@@ -307,20 +459,32 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]); mutex[mutex->id]);
unsigned int reg; unsigned int reg;
unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex); WARN_ON(&ddp->mutex[mutex->id] != mutex);
switch (id) { switch (id) {
case DDP_COMPONENT_DSI0: case DDP_COMPONENT_DSI0:
case DDP_COMPONENT_DSI1: case DDP_COMPONENT_DSI1:
case DDP_COMPONENT_DSI2:
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE, writel_relaxed(MUTEX_SOF_SINGLE_MODE,
ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
break; break;
default: default:
reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); if (ddp->mutex_mod[id] < 32) {
reg &= ~(ddp->mutex_mod[id]); offset = DISP_REG_MUTEX_MOD(mutex->id);
writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); reg = readl_relaxed(ddp->regs + offset);
reg &= ~(1 << ddp->mutex_mod[id]);
writel_relaxed(reg, ddp->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(ddp->regs + offset);
reg &= ~(1 << (ddp->mutex_mod[id] - 32));
writel_relaxed(reg, ddp->regs + offset);
}
break; break;
} }
} }
...@@ -407,6 +571,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) ...@@ -407,6 +571,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
static const struct of_device_id ddp_driver_dt_match[] = { static const struct of_device_id ddp_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
{ .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{}, {},
}; };
......
...@@ -218,18 +218,25 @@ struct mtk_ddp_comp_match { ...@@ -218,18 +218,25 @@ struct mtk_ddp_comp_match {
}; };
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
[DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
...@@ -271,7 +278,11 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, ...@@ -271,7 +278,11 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
if (comp_id == DDP_COMPONENT_BLS || if (comp_id == DDP_COMPONENT_BLS ||
comp_id == DDP_COMPONENT_DPI0 || comp_id == DDP_COMPONENT_DPI0 ||
comp_id == DDP_COMPONENT_DPI1 ||
comp_id == DDP_COMPONENT_DSI0 || comp_id == DDP_COMPONENT_DSI0 ||
comp_id == DDP_COMPONENT_DSI1 ||
comp_id == DDP_COMPONENT_DSI2 ||
comp_id == DDP_COMPONENT_DSI3 ||
comp_id == DDP_COMPONENT_PWM0) { comp_id == DDP_COMPONENT_PWM0) {
comp->regs = NULL; comp->regs = NULL;
comp->clk = NULL; comp->clk = NULL;
......
...@@ -41,19 +41,25 @@ enum mtk_ddp_comp_type { ...@@ -41,19 +41,25 @@ enum mtk_ddp_comp_type {
}; };
enum mtk_ddp_comp_id { enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL, DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
DDP_COMPONENT_BLS, DDP_COMPONENT_BLS,
DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1, DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA, DDP_COMPONENT_GAMMA,
DDP_COMPONENT_OD, DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2, DDP_COMPONENT_RDMA2,
......
...@@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { ...@@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI0,
}; };
static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_OD0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_PWM0,
};
static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
DDP_COMPONENT_OVL1,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_AAL1,
DDP_COMPONENT_OD1,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_PWM1,
};
static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
DDP_COMPONENT_RDMA2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_PWM2,
};
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR0,
DDP_COMPONENT_AAL, DDP_COMPONENT_AAL0,
DDP_COMPONENT_OD, DDP_COMPONENT_OD0,
DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE, DDP_COMPONENT_UFOE,
DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI0,
...@@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { ...@@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.shadow_register = true, .shadow_register = true,
}; };
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.main_path = mt2712_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
.ext_path = mt2712_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main, .main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
...@@ -232,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) ...@@ -232,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret < 0) if (ret < 0)
goto err_component_unbind; goto err_component_unbind;
ret = mtk_drm_crtc_create(drm, private->data->third_path,
private->data->third_len);
if (ret < 0)
goto err_component_unbind;
/* Use OVL device for all DMA memory allocations */ /* Use OVL device for all DMA memory allocations */
np = private->comp_node[private->data->main_path[0]] ?: np = private->comp_node[private->data->main_path[0]] ?:
private->comp_node[private->data->ext_path[0]]; private->comp_node[private->data->ext_path[0]];
...@@ -360,24 +400,44 @@ static const struct component_master_ops mtk_drm_ops = { ...@@ -360,24 +400,44 @@ static const struct component_master_ops mtk_drm_ops = {
}; };
static const struct of_device_id mtk_ddp_comp_dt_ids[] = { static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt2701-disp-ovl",
{ .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-ovl",
{ .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt2701-disp-rdma",
{ .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-rdma",
{ .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-wdma",
{ .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, .data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-disp-color",
{ .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, .data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-disp-color",
{ .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, .data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-aal",
{ .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-gamma",
{ .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, .data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dpi",
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ } { }
}; };
...@@ -552,6 +612,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, ...@@ -552,6 +612,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
static const struct of_device_id mtk_drm_of_ids[] = { static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys", { .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data}, .data = &mt2701_mmsys_driver_data},
{ .compatible = "mediatek,mt2712-mmsys",
.data = &mt2712_mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys", { .compatible = "mediatek,mt8173-mmsys",
.data = &mt8173_mmsys_driver_data}, .data = &mt8173_mmsys_driver_data},
{ } { }
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <linux/io.h> #include <linux/io.h>
#include "mtk_drm_ddp_comp.h" #include "mtk_drm_ddp_comp.h"
#define MAX_CRTC 2 #define MAX_CRTC 3
#define MAX_CONNECTOR 2 #define MAX_CONNECTOR 2
struct device; struct device;
...@@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { ...@@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
unsigned int main_len; unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path; const enum mtk_ddp_comp_id *ext_path;
unsigned int ext_len; unsigned int ext_len;
const enum mtk_ddp_comp_id *third_path;
unsigned int third_len;
bool shadow_register; bool shadow_register;
}; };
......
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