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Commit 1220547b authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'depends/omap/gpio/runtime-pm-cleanup' into next/cleanup 

Conflicts:
	arch/arm/mach-omap1/gpio16xx.c
	drivers/gpio/gpio-omap.c

Merge in the runtime-pm-cleanup branch from the gpio tree into
next/cleanup, this resolves a nonobvious merge conflict between
the two branches. Both branches move parts of the gpio-omap
driver into platform code, this takes the superset of both
changes.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a26d3c4f f86bcc30
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Showing with 549 additions and 692 deletions
arch/arm/mach-omap1/gpio15xx.c
View file @ 1220547b
...@@ -42,11 +42,12 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = { ...@@ -42,11 +42,12 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT, .irqstatus = OMAP_MPUIO_GPIO_INT,
.irqenable = OMAP_MPUIO_GPIO_MASKIT, .irqenable = OMAP_MPUIO_GPIO_MASKIT,
.irqenable_inv = true, .irqenable_inv = true,
.irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
}; };
static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE, .virtual_irq_start = IH_MPUIO_BASE,
.bank_type = METHOD_MPUIO, .is_mpuio = true,
.bank_width = 16, .bank_width = 16,
.bank_stride = 1, .bank_stride = 1,
.regs = &omap15xx_mpuio_regs, .regs = &omap15xx_mpuio_regs,
...@@ -83,11 +84,12 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = { ...@@ -83,11 +84,12 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
.irqstatus = OMAP1510_GPIO_INT_STATUS, .irqstatus = OMAP1510_GPIO_INT_STATUS,
.irqenable = OMAP1510_GPIO_INT_MASK, .irqenable = OMAP1510_GPIO_INT_MASK,
.irqenable_inv = true, .irqenable_inv = true,
.irqctrl = OMAP1510_GPIO_INT_CONTROL,
.pinctrl = OMAP1510_GPIO_PIN_CONTROL,
}; };
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
.virtual_irq_start = IH_GPIO_BASE, .virtual_irq_start = IH_GPIO_BASE,
.bank_type = METHOD_GPIO_1510,
.bank_width = 16, .bank_width = 16,
.regs = &omap15xx_gpio_regs, .regs = &omap15xx_gpio_regs,
}; };
...@@ -115,7 +117,6 @@ static int __init omap15xx_gpio_init(void) ...@@ -115,7 +117,6 @@ static int __init omap15xx_gpio_init(void)
platform_device_register(&omap15xx_mpu_gpio); platform_device_register(&omap15xx_mpu_gpio);
platform_device_register(&omap15xx_gpio); platform_device_register(&omap15xx_gpio);
gpio_bank_count = 2;
return 0; return 0;
} }
postcore_initcall(omap15xx_gpio_init); postcore_initcall(omap15xx_gpio_init);
arch/arm/mach-omap1/gpio16xx.c
View file @ 1220547b
...@@ -24,6 +24,9 @@ ...@@ -24,6 +24,9 @@
#define OMAP1610_GPIO4_BASE 0xfffbbc00 #define OMAP1610_GPIO4_BASE 0xfffbbc00
#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
/* smart idle, enable wakeup */
#define SYSCONFIG_WORD 0x14
/* mpu gpio */ /* mpu gpio */
static struct __initdata resource omap16xx_mpu_gpio_resources[] = { static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
{ {
...@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = { ...@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT, .irqstatus = OMAP_MPUIO_GPIO_INT,
.irqenable = OMAP_MPUIO_GPIO_MASKIT, .irqenable = OMAP_MPUIO_GPIO_MASKIT,
.irqenable_inv = true, .irqenable_inv = true,
.irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
}; };
static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE, .virtual_irq_start = IH_MPUIO_BASE,
.bank_type = METHOD_MPUIO, .is_mpuio = true,
.bank_width = 16, .bank_width = 16,
.bank_stride = 1, .bank_stride = 1,
.regs = &omap16xx_mpuio_regs, .regs = &omap16xx_mpuio_regs,
...@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = { ...@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
.irqenable = OMAP1610_GPIO_IRQENABLE1, .irqenable = OMAP1610_GPIO_IRQENABLE1,
.set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1,
.clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1,
.wkup_en = OMAP1610_GPIO_WAKEUPENABLE,
.edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
.edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
}; };
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
.virtual_irq_start = IH_GPIO_BASE, .virtual_irq_start = IH_GPIO_BASE,
.bank_type = METHOD_GPIO_1610,
.bank_width = 16, .bank_width = 16,
.regs = &omap16xx_gpio_regs, .regs = &omap16xx_gpio_regs,
}; };
...@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = { ...@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
.virtual_irq_start = IH_GPIO_BASE + 16, .virtual_irq_start = IH_GPIO_BASE + 16,
.bank_type = METHOD_GPIO_1610,
.bank_width = 16, .bank_width = 16,
.regs = &omap16xx_gpio_regs, .regs = &omap16xx_gpio_regs,
}; };
...@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = { ...@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
.virtual_irq_start = IH_GPIO_BASE + 32, .virtual_irq_start = IH_GPIO_BASE + 32,
.bank_type = METHOD_GPIO_1610,
.bank_width = 16, .bank_width = 16,
.regs = &omap16xx_gpio_regs, .regs = &omap16xx_gpio_regs,
}; };
...@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = { ...@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
.virtual_irq_start = IH_GPIO_BASE + 48, .virtual_irq_start = IH_GPIO_BASE + 48,
.bank_type = METHOD_GPIO_1610,
.bank_width = 16, .bank_width = 16,
.regs = &omap16xx_gpio_regs, .regs = &omap16xx_gpio_regs,
}; };
...@@ -214,6 +217,10 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = { ...@@ -214,6 +217,10 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
static int __init omap16xx_gpio_init(void) static int __init omap16xx_gpio_init(void)
{ {
int i; int i;
void __iomem *base;
struct resource *res;
struct platform_device *pdev;
struct omap_gpio_platform_data *pdata;
if (!cpu_is_omap16xx()) if (!cpu_is_omap16xx())
return -EINVAL; return -EINVAL;
...@@ -225,10 +232,27 @@ static int __init omap16xx_gpio_init(void) ...@@ -225,10 +232,27 @@ static int __init omap16xx_gpio_init(void)
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
ULPD_CAM_CLK_CTRL); ULPD_CAM_CLK_CTRL);
for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
platform_device_register(omap16xx_gpio_dev[i]); pdev = omap16xx_gpio_dev[i];
pdata = pdev->dev.platform_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!res)) {
dev_err(&pdev->dev, "Invalid mem resource.\n");
return -ENODEV;
}
gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev); base = ioremap(res->start, resource_size(res));
if (unlikely(!base)) {
dev_err(&pdev->dev, "ioremap failed.\n");
return -ENOMEM;
}
__raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
iounmap(base);
platform_device_register(omap16xx_gpio_dev[i]);
}
return 0; return 0;
} }
......
arch/arm/mach-omap1/gpio7xx.c
View file @ 1220547b
...@@ -47,12 +47,13 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = { ...@@ -47,12 +47,13 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT / 2, .irqstatus = OMAP_MPUIO_GPIO_INT / 2,
.irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
.irqenable_inv = true, .irqenable_inv = true,
.irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
}; };
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE, .virtual_irq_start = IH_MPUIO_BASE,
.bank_type = METHOD_MPUIO, .is_mpuio = true,
.bank_width = 32, .bank_width = 16,
.bank_stride = 2, .bank_stride = 2,
.regs = &omap7xx_mpuio_regs, .regs = &omap7xx_mpuio_regs,
}; };
...@@ -88,11 +89,11 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = { ...@@ -88,11 +89,11 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
.irqstatus = OMAP7XX_GPIO_INT_STATUS, .irqstatus = OMAP7XX_GPIO_INT_STATUS,
.irqenable = OMAP7XX_GPIO_INT_MASK, .irqenable = OMAP7XX_GPIO_INT_MASK,
.irqenable_inv = true, .irqenable_inv = true,
.irqctrl = OMAP7XX_GPIO_INT_CONTROL,
}; };
static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
.virtual_irq_start = IH_GPIO_BASE, .virtual_irq_start = IH_GPIO_BASE,
.bank_type = METHOD_GPIO_7XX,
.bank_width = 32, .bank_width = 32,
.regs = &omap7xx_gpio_regs, .regs = &omap7xx_gpio_regs,
}; };
...@@ -122,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = { ...@@ -122,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
.virtual_irq_start = IH_GPIO_BASE + 32, .virtual_irq_start = IH_GPIO_BASE + 32,
.bank_type = METHOD_GPIO_7XX,
.bank_width = 32, .bank_width = 32,
.regs = &omap7xx_gpio_regs, .regs = &omap7xx_gpio_regs,
}; };
...@@ -152,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = { ...@@ -152,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
.virtual_irq_start = IH_GPIO_BASE + 64, .virtual_irq_start = IH_GPIO_BASE + 64,
.bank_type = METHOD_GPIO_7XX,
.bank_width = 32, .bank_width = 32,
.regs = &omap7xx_gpio_regs, .regs = &omap7xx_gpio_regs,
}; };
...@@ -182,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = { ...@@ -182,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
.virtual_irq_start = IH_GPIO_BASE + 96, .virtual_irq_start = IH_GPIO_BASE + 96,
.bank_type = METHOD_GPIO_7XX,
.bank_width = 32, .bank_width = 32,
.regs = &omap7xx_gpio_regs, .regs = &omap7xx_gpio_regs,
}; };
...@@ -212,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = { ...@@ -212,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
.virtual_irq_start = IH_GPIO_BASE + 128, .virtual_irq_start = IH_GPIO_BASE + 128,
.bank_type = METHOD_GPIO_7XX,
.bank_width = 32, .bank_width = 32,
.regs = &omap7xx_gpio_regs, .regs = &omap7xx_gpio_regs,
}; };
...@@ -242,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = { ...@@ -242,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
.virtual_irq_start = IH_GPIO_BASE + 160, .virtual_irq_start = IH_GPIO_BASE + 160,
.bank_type = METHOD_GPIO_7XX,
.bank_width = 32, .bank_width = 32,
.regs = &omap7xx_gpio_regs, .regs = &omap7xx_gpio_regs,
}; };
...@@ -282,8 +278,6 @@ static int __init omap7xx_gpio_init(void) ...@@ -282,8 +278,6 @@ static int __init omap7xx_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
platform_device_register(omap7xx_gpio_dev[i]); platform_device_register(omap7xx_gpio_dev[i]);
gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
return 0; return 0;
} }
postcore_initcall(omap7xx_gpio_init); postcore_initcall(omap7xx_gpio_init);
arch/arm/mach-omap2/gpio.c
View file @ 1220547b
...@@ -23,6 +23,9 @@ ...@@ -23,6 +23,9 @@
#include <plat/omap_hwmod.h> #include <plat/omap_hwmod.h>
#include <plat/omap_device.h> #include <plat/omap_device.h>
#include <plat/omap-pm.h>
#include "powerdomain.h"
static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
{ {
...@@ -31,6 +34,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -31,6 +34,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
struct omap_gpio_dev_attr *dev_attr; struct omap_gpio_dev_attr *dev_attr;
char *name = "omap_gpio"; char *name = "omap_gpio";
int id; int id;
struct powerdomain *pwrdm;
/* /*
* extract the device id from name field available in the * extract the device id from name field available in the
...@@ -52,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -52,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->bank_width = dev_attr->bank_width; pdata->bank_width = dev_attr->bank_width;
pdata->dbck_flag = dev_attr->dbck_flag; pdata->dbck_flag = dev_attr->dbck_flag;
pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
if (!pdata) { if (!pdata) {
pr_err("gpio%d: Memory allocation failed\n", id); pr_err("gpio%d: Memory allocation failed\n", id);
...@@ -61,8 +65,15 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -61,8 +65,15 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
switch (oh->class->rev) { switch (oh->class->rev) {
case 0: case 0:
if (id == 1)
/* non-wakeup GPIO pins for OMAP2 Bank1 */
pdata->non_wakeup_gpios = 0xe203ffc0;
else if (id == 2)
/* non-wakeup GPIO pins for OMAP2 Bank2 */
pdata->non_wakeup_gpios = 0x08700040;
/* fall through */
case 1: case 1:
pdata->bank_type = METHOD_GPIO_24XX;
pdata->regs->revision = OMAP24XX_GPIO_REVISION; pdata->regs->revision = OMAP24XX_GPIO_REVISION;
pdata->regs->direction = OMAP24XX_GPIO_OE; pdata->regs->direction = OMAP24XX_GPIO_OE;
pdata->regs->datain = OMAP24XX_GPIO_DATAIN; pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
...@@ -72,13 +83,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -72,13 +83,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1; pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2; pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1; pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2;
pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1; pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1; pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL; pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN; pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN;
pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
break; break;
case 2: case 2:
pdata->bank_type = METHOD_GPIO_44XX;
pdata->regs->revision = OMAP4_GPIO_REVISION; pdata->regs->revision = OMAP4_GPIO_REVISION;
pdata->regs->direction = OMAP4_GPIO_OE; pdata->regs->direction = OMAP4_GPIO_OE;
pdata->regs->datain = OMAP4_GPIO_DATAIN; pdata->regs->datain = OMAP4_GPIO_DATAIN;
...@@ -88,10 +105,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -88,10 +105,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0; pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1; pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0; pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1;
pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0; pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0; pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME; pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE; pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
pdata->regs->ctrl = OMAP4_GPIO_CTRL;
pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0;
pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT;
break; break;
default: default:
WARN(1, "Invalid gpio bank_type\n"); WARN(1, "Invalid gpio bank_type\n");
...@@ -99,6 +123,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -99,6 +123,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
return -EINVAL; return -EINVAL;
} }
pwrdm = omap_hwmod_get_pwrdm(oh);
pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
pdev = omap_device_build(name, id - 1, oh, pdata, pdev = omap_device_build(name, id - 1, oh, pdata,
sizeof(*pdata), NULL, 0, false); sizeof(*pdata), NULL, 0, false);
kfree(pdata); kfree(pdata);
...@@ -109,9 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) ...@@ -109,9 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
return PTR_ERR(pdev); return PTR_ERR(pdev);
} }
omap_device_disable_idle_on_suspend(pdev);
gpio_bank_count++;
return 0; return 0;
} }
......
arch/arm/mach-omap2/pm34xx.c
View file @ 1220547b
...@@ -75,16 +75,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm; ...@@ -75,16 +75,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm; static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm; static struct powerdomain *cam_pwrdm;
static inline void omap3_per_save_context(void)
{
omap_gpio_save_context();
}
static inline void omap3_per_restore_context(void)
{
omap_gpio_restore_context();
}
static void omap3_enable_io_chain(void) static void omap3_enable_io_chain(void)
{ {
int timeout = 0; int timeout = 0;
...@@ -332,8 +322,6 @@ void omap_sram_idle(void) ...@@ -332,8 +322,6 @@ void omap_sram_idle(void)
if (per_next_state < PWRDM_POWER_ON) { if (per_next_state < PWRDM_POWER_ON) {
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
omap2_gpio_prepare_for_idle(per_going_off); omap2_gpio_prepare_for_idle(per_going_off);
if (per_next_state == PWRDM_POWER_OFF)
omap3_per_save_context();
} }
/* CORE */ /* CORE */
...@@ -399,8 +387,6 @@ void omap_sram_idle(void) ...@@ -399,8 +387,6 @@ void omap_sram_idle(void)
if (per_next_state < PWRDM_POWER_ON) { if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
omap2_gpio_resume_after_idle(); omap2_gpio_resume_after_idle();
if (per_prev_state == PWRDM_POWER_OFF)
omap3_per_restore_context();
} }
/* Disable IO-PAD and IO-CHAIN wakeup */ /* Disable IO-PAD and IO-CHAIN wakeup */
......
arch/arm/plat-omap/include/plat/gpio.h
View file @ 1220547b
...@@ -162,13 +162,6 @@ ...@@ -162,13 +162,6 @@
IH_MPUIO_BASE + ((nr) & 0x0f) : \ IH_MPUIO_BASE + ((nr) & 0x0f) : \
IH_GPIO_BASE + (nr)) IH_GPIO_BASE + (nr))
#define METHOD_MPUIO 0
#define METHOD_GPIO_1510 1
#define METHOD_GPIO_1610 2
#define METHOD_GPIO_7XX 3
#define METHOD_GPIO_24XX 5
#define METHOD_GPIO_44XX 6
struct omap_gpio_dev_attr { struct omap_gpio_dev_attr {
int bank_width; /* GPIO bank width */ int bank_width; /* GPIO bank width */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
...@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs { ...@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs {
u16 irqstatus; u16 irqstatus;
u16 irqstatus2; u16 irqstatus2;
u16 irqenable; u16 irqenable;
u16 irqenable2;
u16 set_irqenable; u16 set_irqenable;
u16 clr_irqenable; u16 clr_irqenable;
u16 debounce; u16 debounce;
u16 debounce_en; u16 debounce_en;
u16 ctrl;
u16 wkup_en;
u16 leveldetect0;
u16 leveldetect1;
u16 risingdetect;
u16 fallingdetect;
u16 irqctrl;
u16 edgectrl1;
u16 edgectrl2;
u16 pinctrl;
bool irqenable_inv; bool irqenable_inv;
}; };
...@@ -198,19 +202,20 @@ struct omap_gpio_platform_data { ...@@ -198,19 +202,20 @@ struct omap_gpio_platform_data {
int bank_width; /* GPIO bank width */ int bank_width; /* GPIO bank width */
int bank_stride; /* Only needed for omap1 MPUIO */ int bank_stride; /* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
bool loses_context; /* whether the bank would ever lose context */
bool is_mpuio; /* whether the bank is of type MPUIO */
u32 non_wakeup_gpios;
struct omap_gpio_reg_offs *regs; struct omap_gpio_reg_offs *regs;
};
/* TODO: Analyze removing gpio_bank_count usage from driver code */ /* Return context loss count due to PM states changing */
extern int gpio_bank_count; int (*get_context_loss_count)(struct device *dev);
};
extern void omap2_gpio_prepare_for_idle(int off_mode); extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void); extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable); extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable); extern void omap_set_gpio_debounce_time(int gpio, int enable);
extern void omap_gpio_save_context(void);
extern void omap_gpio_restore_context(void);
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
/* Wrappers for "new style" GPIO calls, using the new infrastructure /* Wrappers for "new style" GPIO calls, using the new infrastructure
......
drivers/gpio/gpio-omap.c
View file @ 1220547b
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/irq.h> #include <asm/irq.h>
...@@ -28,19 +29,36 @@ ...@@ -28,19 +29,36 @@
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#define OFF_MODE 1
static LIST_HEAD(omap_gpio_list);
struct gpio_regs {
u32 irqenable1;
u32 irqenable2;
u32 wake_en;
u32 ctrl;
u32 oe;
u32 leveldetect0;
u32 leveldetect1;
u32 risingdetect;
u32 fallingdetect;
u32 dataout;
u32 debounce;
u32 debounce_en;
};
struct gpio_bank { struct gpio_bank {
struct list_head node;
unsigned long pbase; unsigned long pbase;
void __iomem *base; void __iomem *base;
u16 irq; u16 irq;
u16 virtual_irq_start; u16 virtual_irq_start;
int method;
u32 suspend_wakeup; u32 suspend_wakeup;
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
u32 saved_wakeup; u32 saved_wakeup;
#endif
u32 non_wakeup_gpios; u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios; u32 enabled_non_wakeup_gpios;
struct gpio_regs context;
u32 saved_datain; u32 saved_datain;
u32 saved_fallingdetect; u32 saved_fallingdetect;
u32 saved_risingdetect; u32 saved_risingdetect;
...@@ -51,44 +69,27 @@ struct gpio_bank { ...@@ -51,44 +69,27 @@ struct gpio_bank {
struct clk *dbck; struct clk *dbck;
u32 mod_usage; u32 mod_usage;
u32 dbck_enable_mask; u32 dbck_enable_mask;
bool dbck_enabled;
struct device *dev; struct device *dev;
bool is_mpuio;
bool dbck_flag; bool dbck_flag;
bool loses_context;
int stride; int stride;
u32 width; u32 width;
int context_loss_count;
u16 id;
int power_mode;
bool workaround_enabled;
void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
int (*get_context_loss_count)(struct device *dev);
struct omap_gpio_reg_offs *regs; struct omap_gpio_reg_offs *regs;
}; };
#ifdef CONFIG_ARCH_OMAP3
struct omap3_gpio_regs {
u32 irqenable1;
u32 irqenable2;
u32 wake_en;
u32 ctrl;
u32 oe;
u32 leveldetect0;
u32 leveldetect1;
u32 risingdetect;
u32 fallingdetect;
u32 dataout;
};
static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
#endif
/*
* TODO: Cleanup gpio_bank usage as it is having information
* related to all instances of the device
*/
static struct gpio_bank *gpio_bank;
/* TODO: Analyze removing gpio_bank_count usage from driver code */
int gpio_bank_count;
#define GPIO_INDEX(bank, gpio) (gpio % bank->width) #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
#define GPIO_MOD_CTRL_BIT BIT(0)
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
{ {
...@@ -102,6 +103,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) ...@@ -102,6 +103,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
else else
l &= ~(1 << gpio); l &= ~(1 << gpio);
__raw_writel(l, reg); __raw_writel(l, reg);
bank->context.oe = l;
} }
...@@ -132,6 +134,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) ...@@ -132,6 +134,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
else else
l &= ~gpio_bit; l &= ~gpio_bit;
__raw_writel(l, reg); __raw_writel(l, reg);
bank->context.dataout = l;
} }
static int _get_gpio_datain(struct gpio_bank *bank, int gpio) static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
...@@ -160,6 +163,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) ...@@ -160,6 +163,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
__raw_writel(l, base + reg); __raw_writel(l, base + reg);
} }
static inline void _gpio_dbck_enable(struct gpio_bank *bank)
{
if (bank->dbck_enable_mask && !bank->dbck_enabled) {
clk_enable(bank->dbck);
bank->dbck_enabled = true;
}
}
static inline void _gpio_dbck_disable(struct gpio_bank *bank)
{
if (bank->dbck_enable_mask && bank->dbck_enabled) {
clk_disable(bank->dbck);
bank->dbck_enabled = false;
}
}
/** /**
* _set_gpio_debounce - low level gpio debounce time * _set_gpio_debounce - low level gpio debounce time
* @bank: the gpio bank we're acting upon * @bank: the gpio bank we're acting upon
...@@ -188,70 +207,74 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, ...@@ -188,70 +207,74 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
l = GPIO_BIT(bank, gpio); l = GPIO_BIT(bank, gpio);
clk_enable(bank->dbck);
reg = bank->base + bank->regs->debounce; reg = bank->base + bank->regs->debounce;
__raw_writel(debounce, reg); __raw_writel(debounce, reg);
reg = bank->base + bank->regs->debounce_en; reg = bank->base + bank->regs->debounce_en;
val = __raw_readl(reg); val = __raw_readl(reg);
if (debounce) { if (debounce)
val |= l; val |= l;
clk_enable(bank->dbck); else
} else {
val &= ~l; val &= ~l;
clk_disable(bank->dbck);
}
bank->dbck_enable_mask = val; bank->dbck_enable_mask = val;
__raw_writel(val, reg); __raw_writel(val, reg);
clk_disable(bank->dbck);
/*
* Enable debounce clock per module.
* This call is mandatory because in omap_gpio_request() when
* *_runtime_get_sync() is called, _gpio_dbck_enable() within
* runtime callbck fails to turn on dbck because dbck_enable_mask
* used within _gpio_dbck_enable() is still not initialized at
* that point. Therefore we have to enable dbck here.
*/
_gpio_dbck_enable(bank);
if (bank->dbck_enable_mask) {
bank->context.debounce = debounce;
bank->context.debounce_en = val;
}
} }
#ifdef CONFIG_ARCH_OMAP2PLUS static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
int trigger) int trigger)
{ {
void __iomem *base = bank->base; void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio; u32 gpio_bit = 1 << gpio;
if (cpu_is_omap44xx()) { _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit, trigger & IRQ_TYPE_LEVEL_LOW);
trigger & IRQ_TYPE_LEVEL_LOW); _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit, trigger & IRQ_TYPE_LEVEL_HIGH);
trigger & IRQ_TYPE_LEVEL_HIGH); _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
_gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit, trigger & IRQ_TYPE_EDGE_RISING);
trigger & IRQ_TYPE_EDGE_RISING); _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
_gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit, trigger & IRQ_TYPE_EDGE_FALLING);
trigger & IRQ_TYPE_EDGE_FALLING);
} else { bank->context.leveldetect0 =
_gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, __raw_readl(bank->base + bank->regs->leveldetect0);
trigger & IRQ_TYPE_LEVEL_LOW); bank->context.leveldetect1 =
_gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, __raw_readl(bank->base + bank->regs->leveldetect1);
trigger & IRQ_TYPE_LEVEL_HIGH); bank->context.risingdetect =
_gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit, __raw_readl(bank->base + bank->regs->risingdetect);
trigger & IRQ_TYPE_EDGE_RISING); bank->context.fallingdetect =
_gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, __raw_readl(bank->base + bank->regs->fallingdetect);
trigger & IRQ_TYPE_EDGE_FALLING);
}
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (cpu_is_omap44xx()) { _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit, bank->context.wake_en =
trigger != 0); __raw_readl(bank->base + bank->regs->wkup_en);
} else {
/*
* GPIO wakeup request can only be generated on edge
* transitions
*/
if (trigger & IRQ_TYPE_EDGE_BOTH)
__raw_writel(1 << gpio, bank->base
+ OMAP24XX_GPIO_SETWKUENA);
else
__raw_writel(1 << gpio, bank->base
+ OMAP24XX_GPIO_CLEARWKUENA);
}
} }
/* This part needs to be executed always for OMAP{34xx, 44xx} */ /* This part needs to be executed always for OMAP{34xx, 44xx} */
if (cpu_is_omap34xx() || cpu_is_omap44xx() || if (!bank->regs->irqctrl) {
(bank->non_wakeup_gpios & gpio_bit)) { /* On omap24xx proceed only when valid GPIO bit is set */
if (bank->non_wakeup_gpios) {
if (!(bank->non_wakeup_gpios & gpio_bit))
goto exit;
}
/* /*
* Log the edge gpio and manually trigger the IRQ * Log the edge gpio and manually trigger the IRQ
* after resume if the input level changes * after resume if the input level changes
...@@ -264,17 +287,11 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, ...@@ -264,17 +287,11 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
bank->enabled_non_wakeup_gpios &= ~gpio_bit; bank->enabled_non_wakeup_gpios &= ~gpio_bit;
} }
if (cpu_is_omap44xx()) { exit:
bank->level_mask = bank->level_mask =
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | __raw_readl(bank->base + bank->regs->leveldetect0) |
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); __raw_readl(bank->base + bank->regs->leveldetect1);
} else {
bank->level_mask =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
}
} }
#endif
#ifdef CONFIG_ARCH_OMAP1 #ifdef CONFIG_ARCH_OMAP1
/* /*
...@@ -286,23 +303,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) ...@@ -286,23 +303,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
void __iomem *reg = bank->base; void __iomem *reg = bank->base;
u32 l = 0; u32 l = 0;
switch (bank->method) { if (!bank->regs->irqctrl)
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
break;
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
break;
#endif
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
case METHOD_GPIO_7XX:
reg += OMAP7XX_GPIO_INT_CONTROL;
break;
#endif
default:
return; return;
}
reg += bank->regs->irqctrl;
l = __raw_readl(reg); l = __raw_readl(reg);
if ((l >> gpio) & 1) if ((l >> gpio) & 1)
...@@ -312,31 +316,21 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) ...@@ -312,31 +316,21 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
__raw_writel(l, reg); __raw_writel(l, reg);
} }
#else
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
#endif #endif
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
{ {
void __iomem *reg = bank->base; void __iomem *reg = bank->base;
void __iomem *base = bank->base;
u32 l = 0; u32 l = 0;
switch (bank->method) { if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
#ifdef CONFIG_ARCH_OMAP1 set_gpio_trigger(bank, gpio, trigger);
case METHOD_MPUIO: } else if (bank->regs->irqctrl) {
reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; reg += bank->regs->irqctrl;
l = __raw_readl(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio;
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
l = __raw_readl(reg); l = __raw_readl(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio; bank->toggle_mask |= 1 << gpio;
...@@ -345,15 +339,15 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) ...@@ -345,15 +339,15 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
else if (trigger & IRQ_TYPE_EDGE_FALLING) else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio); l &= ~(1 << gpio);
else else
goto bad; return -EINVAL;
break;
#endif __raw_writel(l, reg);
#ifdef CONFIG_ARCH_OMAP16XX } else if (bank->regs->edgectrl1) {
case METHOD_GPIO_1610:
if (gpio & 0x08) if (gpio & 0x08)
reg += OMAP1610_GPIO_EDGE_CTRL2; reg += bank->regs->edgectrl2;
else else
reg += OMAP1610_GPIO_EDGE_CTRL1; reg += bank->regs->edgectrl1;
gpio &= 0x07; gpio &= 0x07;
l = __raw_readl(reg); l = __raw_readl(reg);
l &= ~(3 << (gpio << 1)); l &= ~(3 << (gpio << 1));
...@@ -361,40 +355,14 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) ...@@ -361,40 +355,14 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
l |= 2 << (gpio << 1); l |= 2 << (gpio << 1);
if (trigger & IRQ_TYPE_EDGE_FALLING) if (trigger & IRQ_TYPE_EDGE_FALLING)
l |= 1 << (gpio << 1); l |= 1 << (gpio << 1);
if (trigger)
/* Enable wake-up during idle for dynamic tick */ /* Enable wake-up during idle for dynamic tick */
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
else bank->context.wake_en =
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); __raw_readl(bank->base + bank->regs->wkup_en);
break; __raw_writel(l, reg);
#endif
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
case METHOD_GPIO_7XX:
reg += OMAP7XX_GPIO_INT_CONTROL;
l = __raw_readl(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio;
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
break;
#endif
#ifdef CONFIG_ARCH_OMAP2PLUS
case METHOD_GPIO_24XX:
case METHOD_GPIO_44XX:
set_24xx_gpio_triggering(bank, gpio, trigger);
return 0;
#endif
default:
goto bad;
} }
__raw_writel(l, reg);
return 0; return 0;
bad:
return -EINVAL;
} }
static int gpio_irq_type(struct irq_data *d, unsigned type) static int gpio_irq_type(struct irq_data *d, unsigned type)
...@@ -412,12 +380,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) ...@@ -412,12 +380,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
if (type & ~IRQ_TYPE_SENSE_MASK) if (type & ~IRQ_TYPE_SENSE_MASK)
return -EINVAL; return -EINVAL;
/* OMAP1 allows only only edge triggering */ bank = irq_data_get_irq_chip_data(d);
if (!cpu_class_is_omap2()
&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) if (!bank->regs->leveldetect0 &&
(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL; return -EINVAL;
bank = irq_data_get_irq_chip_data(d);
spin_lock_irqsave(&bank->lock, flags); spin_lock_irqsave(&bank->lock, flags);
retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
spin_unlock_irqrestore(&bank->lock, flags); spin_unlock_irqrestore(&bank->lock, flags);
...@@ -484,6 +452,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) ...@@ -484,6 +452,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
} }
__raw_writel(l, reg); __raw_writel(l, reg);
bank->context.irqenable1 = l;
} }
static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
...@@ -504,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) ...@@ -504,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
} }
__raw_writel(l, reg); __raw_writel(l, reg);
bank->context.irqenable1 = l;
} }
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
...@@ -567,38 +537,39 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) ...@@ -567,38 +537,39 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&bank->lock, flags); /*
* If this is the first gpio_request for the bank,
* enable the bank module.
*/
if (!bank->mod_usage)
pm_runtime_get_sync(bank->dev);
spin_lock_irqsave(&bank->lock, flags);
/* Set trigger to none. You need to enable the desired trigger with /* Set trigger to none. You need to enable the desired trigger with
* request_irq() or set_irq_type(). * request_irq() or set_irq_type().
*/ */
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
#ifdef CONFIG_ARCH_OMAP15XX if (bank->regs->pinctrl) {
if (bank->method == METHOD_GPIO_1510) { void __iomem *reg = bank->base + bank->regs->pinctrl;
void __iomem *reg;
/* Claim the pin for MPU */ /* Claim the pin for MPU */
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
__raw_writel(__raw_readl(reg) | (1 << offset), reg); __raw_writel(__raw_readl(reg) | (1 << offset), reg);
} }
#endif
if (!cpu_class_is_omap1()) { if (bank->regs->ctrl && !bank->mod_usage) {
if (!bank->mod_usage) { void __iomem *reg = bank->base + bank->regs->ctrl;
void __iomem *reg = bank->base; u32 ctrl;
u32 ctrl;
ctrl = __raw_readl(reg);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* Module is enabled, clocks are not gated */
reg += OMAP24XX_GPIO_CTRL; ctrl &= ~GPIO_MOD_CTRL_BIT;
else if (cpu_is_omap44xx()) __raw_writel(ctrl, reg);
reg += OMAP4_GPIO_CTRL; bank->context.ctrl = ctrl;
ctrl = __raw_readl(reg);
/* Module is enabled, clocks are not gated */
ctrl &= 0xFFFFFFFE;
__raw_writel(ctrl, reg);
}
bank->mod_usage |= 1 << offset;
} }
bank->mod_usage |= 1 << offset;
spin_unlock_irqrestore(&bank->lock, flags); spin_unlock_irqrestore(&bank->lock, flags);
return 0; return 0;
...@@ -607,48 +578,40 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) ...@@ -607,48 +578,40 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
{ {
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *base = bank->base;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&bank->lock, flags); spin_lock_irqsave(&bank->lock, flags);
#ifdef CONFIG_ARCH_OMAP16XX
if (bank->method == METHOD_GPIO_1610) { if (bank->regs->wkup_en) {
/* Disable wake-up during idle for dynamic tick */
void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
__raw_writel(1 << offset, reg);
}
#endif
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
if (bank->method == METHOD_GPIO_24XX) {
/* Disable wake-up during idle for dynamic tick */
void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
__raw_writel(1 << offset, reg);
}
#endif
#ifdef CONFIG_ARCH_OMAP4
if (bank->method == METHOD_GPIO_44XX) {
/* Disable wake-up during idle for dynamic tick */ /* Disable wake-up during idle for dynamic tick */
void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
__raw_writel(1 << offset, reg); bank->context.wake_en =
__raw_readl(bank->base + bank->regs->wkup_en);
} }
#endif
if (!cpu_class_is_omap1()) { bank->mod_usage &= ~(1 << offset);
bank->mod_usage &= ~(1 << offset);
if (!bank->mod_usage) { if (bank->regs->ctrl && !bank->mod_usage) {
void __iomem *reg = bank->base; void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl; u32 ctrl;
if (cpu_is_omap24xx() || cpu_is_omap34xx()) ctrl = __raw_readl(reg);
reg += OMAP24XX_GPIO_CTRL; /* Module is disabled, clocks are gated */
else if (cpu_is_omap44xx()) ctrl |= GPIO_MOD_CTRL_BIT;
reg += OMAP4_GPIO_CTRL; __raw_writel(ctrl, reg);
ctrl = __raw_readl(reg); bank->context.ctrl = ctrl;
/* Module is disabled, clocks are gated */
ctrl |= 1;
__raw_writel(ctrl, reg);
}
} }
_reset_gpio(bank, bank->chip.base + offset); _reset_gpio(bank, bank->chip.base + offset);
spin_unlock_irqrestore(&bank->lock, flags); spin_unlock_irqrestore(&bank->lock, flags);
/*
* If this is the last gpio to be freed in the bank,
* disable the bank module.
*/
if (!bank->mod_usage)
pm_runtime_put(bank->dev);
} }
/* /*
...@@ -674,6 +637,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) ...@@ -674,6 +637,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
bank = irq_get_handler_data(irq); bank = irq_get_handler_data(irq);
isr_reg = bank->base + bank->regs->irqstatus; isr_reg = bank->base + bank->regs->irqstatus;
pm_runtime_get_sync(bank->dev);
if (WARN_ON(!isr_reg)) if (WARN_ON(!isr_reg))
goto exit; goto exit;
...@@ -685,12 +649,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) ...@@ -685,12 +649,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
enabled = _get_gpio_irqbank_mask(bank); enabled = _get_gpio_irqbank_mask(bank);
isr_saved = isr = __raw_readl(isr_reg) & enabled; isr_saved = isr = __raw_readl(isr_reg) & enabled;
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) if (bank->level_mask)
isr &= 0x0000ffff;
if (cpu_class_is_omap2()) {
level_mask = bank->level_mask & enabled; level_mask = bank->level_mask & enabled;
}
/* clear edge sensitive interrupts before handler(s) are /* clear edge sensitive interrupts before handler(s) are
called so that we don't miss any interrupt occurred while called so that we don't miss any interrupt occurred while
...@@ -718,7 +678,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) ...@@ -718,7 +678,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
if (!(isr & 1)) if (!(isr & 1))
continue; continue;
#ifdef CONFIG_ARCH_OMAP1
/* /*
* Some chips can't respond to both rising and falling * Some chips can't respond to both rising and falling
* at the same time. If this irq was requested with * at the same time. If this irq was requested with
...@@ -728,7 +687,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) ...@@ -728,7 +687,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
*/ */
if (bank->toggle_mask & (1 << gpio_index)) if (bank->toggle_mask & (1 << gpio_index))
_toggle_gpio_edge_triggering(bank, gpio_index); _toggle_gpio_edge_triggering(bank, gpio_index);
#endif
generic_handle_irq(gpio_irq); generic_handle_irq(gpio_irq);
} }
...@@ -740,6 +698,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) ...@@ -740,6 +698,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
exit: exit:
if (!unmasked) if (!unmasked)
chained_irq_exit(chip, desc); chained_irq_exit(chip, desc);
pm_runtime_put(bank->dev);
} }
static void gpio_irq_shutdown(struct irq_data *d) static void gpio_irq_shutdown(struct irq_data *d)
...@@ -808,14 +767,6 @@ static struct irq_chip gpio_irq_chip = { ...@@ -808,14 +767,6 @@ static struct irq_chip gpio_irq_chip = {
/*---------------------------------------------------------------------*/ /*---------------------------------------------------------------------*/
#ifdef CONFIG_ARCH_OMAP1
#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
#ifdef CONFIG_ARCH_OMAP16XX
#include <linux/platform_device.h>
static int omap_mpuio_suspend_noirq(struct device *dev) static int omap_mpuio_suspend_noirq(struct device *dev)
{ {
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
...@@ -869,32 +820,16 @@ static struct platform_device omap_mpuio_device = { ...@@ -869,32 +820,16 @@ static struct platform_device omap_mpuio_device = {
/* could list the /proc/iomem resources */ /* could list the /proc/iomem resources */
}; };
static inline void mpuio_init(void) static inline void mpuio_init(struct gpio_bank *bank)
{ {
struct gpio_bank *bank = &gpio_bank[0];
platform_set_drvdata(&omap_mpuio_device, bank); platform_set_drvdata(&omap_mpuio_device, bank);
if (platform_driver_register(&omap_mpuio_driver) == 0) if (platform_driver_register(&omap_mpuio_driver) == 0)
(void) platform_device_register(&omap_mpuio_device); (void) platform_device_register(&omap_mpuio_device);
} }
#else
static inline void mpuio_init(void) {}
#endif /* 16xx */
#else
#define bank_is_mpuio(bank) 0
static inline void mpuio_init(void) {}
#endif
/*---------------------------------------------------------------------*/ /*---------------------------------------------------------------------*/
/* REVISIT these are stupid implementations! replace by ones that
* don't switch on METHOD_* and which mostly avoid spinlocks
*/
static int gpio_input(struct gpio_chip *chip, unsigned offset) static int gpio_input(struct gpio_chip *chip, unsigned offset)
{ {
struct gpio_bank *bank; struct gpio_bank *bank;
...@@ -1007,71 +942,32 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank) ...@@ -1007,71 +942,32 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
*/ */
static struct lock_class_key gpio_lock_class; static struct lock_class_key gpio_lock_class;
static inline int init_gpio_info(struct platform_device *pdev) static void omap_gpio_mod_init(struct gpio_bank *bank)
{ {
/* TODO: Analyze removing gpio_bank_count usage from driver code */ void __iomem *base = bank->base;
gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), u32 l = 0xffffffff;
GFP_KERNEL);
if (!gpio_bank) {
dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
return -ENOMEM;
}
return 0;
}
/* TODO: Cleanup cpu_is_* checks */ if (bank->width == 16)
static void omap_gpio_mod_init(struct gpio_bank *bank, int id) l = 0xffff;
{
if (cpu_class_is_omap2()) { if (bank->is_mpuio) {
if (cpu_is_omap44xx()) { __raw_writel(l, bank->base + bank->regs->irqenable);
__raw_writel(0xffffffff, bank->base + return;
OMAP4_GPIO_IRQSTATUSCLR0);
__raw_writel(0x00000000, bank->base +
OMAP4_GPIO_DEBOUNCENABLE);
/* Initialize interface clk ungated, module enabled */
__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
} else if (cpu_is_omap34xx()) {
__raw_writel(0x00000000, bank->base +
OMAP24XX_GPIO_IRQENABLE1);
__raw_writel(0xffffffff, bank->base +
OMAP24XX_GPIO_IRQSTATUS1);
__raw_writel(0x00000000, bank->base +
OMAP24XX_GPIO_DEBOUNCE_EN);
/* Initialize interface clk ungated, module enabled */
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
} else if (cpu_is_omap24xx()) {
static const u32 non_wakeup_gpios[] = {
0xe203ffc0, 0x08700040
};
if (id < ARRAY_SIZE(non_wakeup_gpios))
bank->non_wakeup_gpios = non_wakeup_gpios[id];
}
} else if (cpu_class_is_omap1()) {
if (bank_is_mpuio(bank))
__raw_writew(0xffff, bank->base +
OMAP_MPUIO_GPIO_MASKIT / bank->stride);
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
__raw_writew(0xffff, bank->base
+ OMAP1510_GPIO_INT_MASK);
__raw_writew(0x0000, bank->base
+ OMAP1510_GPIO_INT_STATUS);
}
if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
__raw_writew(0x0000, bank->base
+ OMAP1610_GPIO_IRQENABLE1);
__raw_writew(0xffff, bank->base
+ OMAP1610_GPIO_IRQSTATUS1);
__raw_writew(0x0014, bank->base
+ OMAP1610_GPIO_SYSCONFIG);
}
if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
__raw_writel(0xffffffff, bank->base
+ OMAP7XX_GPIO_INT_MASK);
__raw_writel(0x00000000, bank->base
+ OMAP7XX_GPIO_INT_STATUS);
}
} }
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
_gpio_rmw(base, bank->regs->irqstatus, l,
bank->regs->irqenable_inv == false);
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
if (bank->regs->debounce_en)
_gpio_rmw(base, bank->regs->debounce_en, 0, 1);
/* Save OE default value (0xffffffff) in the context */
bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
/* Initialize interface clk ungated, module enabled */
if (bank->regs->ctrl)
_gpio_rmw(base, bank->regs->ctrl, 0, 1);
} }
static __init void static __init void
...@@ -1094,8 +990,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, ...@@ -1094,8 +990,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = gpio_irq_type; ct->chip.irq_set_type = gpio_irq_type;
/* REVISIT: assuming only 16xx supports MPUIO wake events */
if (cpu_is_omap16xx()) if (bank->regs->wkup_en)
ct->chip.irq_set_wake = gpio_wake_enable, ct->chip.irq_set_wake = gpio_wake_enable,
ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
...@@ -1108,7 +1004,6 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) ...@@ -1108,7 +1004,6 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
int j; int j;
static int gpio; static int gpio;
bank->mod_usage = 0;
/* /*
* REVISIT eventually switch from OMAP-specific gpio structs * REVISIT eventually switch from OMAP-specific gpio structs
* over to the generic ones * over to the generic ones
...@@ -1121,11 +1016,10 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) ...@@ -1121,11 +1016,10 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
bank->chip.set_debounce = gpio_debounce; bank->chip.set_debounce = gpio_debounce;
bank->chip.set = gpio_set; bank->chip.set = gpio_set;
bank->chip.to_irq = gpio_2irq; bank->chip.to_irq = gpio_2irq;
if (bank_is_mpuio(bank)) { if (bank->is_mpuio) {
bank->chip.label = "mpuio"; bank->chip.label = "mpuio";
#ifdef CONFIG_ARCH_OMAP16XX if (bank->regs->wkup_en)
bank->chip.dev = &omap_mpuio_device.dev; bank->chip.dev = &omap_mpuio_device.dev;
#endif
bank->chip.base = OMAP_MPUIO(0); bank->chip.base = OMAP_MPUIO(0);
} else { } else {
bank->chip.label = "gpio"; bank->chip.label = "gpio";
...@@ -1140,7 +1034,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) ...@@ -1140,7 +1034,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
j < bank->virtual_irq_start + bank->width; j++) { j < bank->virtual_irq_start + bank->width; j++) {
irq_set_lockdep_class(j, &gpio_lock_class); irq_set_lockdep_class(j, &gpio_lock_class);
irq_set_chip_data(j, bank); irq_set_chip_data(j, bank);
if (bank_is_mpuio(bank)) { if (bank->is_mpuio) {
omap_mpuio_alloc_gc(bank, j, bank->width); omap_mpuio_alloc_gc(bank, j, bank->width);
} else { } else {
irq_set_chip(j, &gpio_irq_chip); irq_set_chip(j, &gpio_irq_chip);
...@@ -1154,42 +1048,44 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) ...@@ -1154,42 +1048,44 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
static int __devinit omap_gpio_probe(struct platform_device *pdev) static int __devinit omap_gpio_probe(struct platform_device *pdev)
{ {
static int gpio_init_done;
struct omap_gpio_platform_data *pdata; struct omap_gpio_platform_data *pdata;
struct resource *res; struct resource *res;
int id;
struct gpio_bank *bank; struct gpio_bank *bank;
int ret = 0;
if (!pdev->dev.platform_data) if (!pdev->dev.platform_data) {
return -EINVAL; ret = -EINVAL;
goto err_exit;
pdata = pdev->dev.platform_data;
if (!gpio_init_done) {
int ret;
ret = init_gpio_info(pdev);
if (ret)
return ret;
} }
id = pdev->id; bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
bank = &gpio_bank[id]; if (!bank) {
dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
ret = -ENOMEM;
goto err_exit;
}
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (unlikely(!res)) { if (unlikely(!res)) {
dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
return -ENODEV; pdev->id);
ret = -ENODEV;
goto err_free;
} }
bank->irq = res->start; bank->irq = res->start;
bank->id = pdev->id;
pdata = pdev->dev.platform_data;
bank->virtual_irq_start = pdata->virtual_irq_start; bank->virtual_irq_start = pdata->virtual_irq_start;
bank->method = pdata->bank_type;
bank->dev = &pdev->dev; bank->dev = &pdev->dev;
bank->dbck_flag = pdata->dbck_flag; bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride; bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width; bank->width = pdata->bank_width;
bank->is_mpuio = pdata->is_mpuio;
bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
bank->loses_context = pdata->loses_context;
bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs; bank->regs = pdata->regs;
if (bank->regs->set_dataout && bank->regs->clr_dataout) if (bank->regs->set_dataout && bank->regs->clr_dataout)
...@@ -1202,369 +1098,310 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) ...@@ -1202,369 +1098,310 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
/* Static mapping, never released */ /* Static mapping, never released */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!res)) { if (unlikely(!res)) {
dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
return -ENODEV; pdev->id);
ret = -ENODEV;
goto err_free;
} }
bank->base = ioremap(res->start, resource_size(res)); bank->base = ioremap(res->start, resource_size(res));
if (!bank->base) { if (!bank->base) {
dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
return -ENOMEM; pdev->id);
ret = -ENOMEM;
goto err_free;
} }
platform_set_drvdata(pdev, bank);
pm_runtime_enable(bank->dev); pm_runtime_enable(bank->dev);
pm_runtime_irq_safe(bank->dev);
pm_runtime_get_sync(bank->dev); pm_runtime_get_sync(bank->dev);
omap_gpio_mod_init(bank, id); if (bank->is_mpuio)
mpuio_init(bank);
omap_gpio_mod_init(bank);
omap_gpio_chip_init(bank); omap_gpio_chip_init(bank);
omap_gpio_show_rev(bank); omap_gpio_show_rev(bank);
if (!gpio_init_done) pm_runtime_put(bank->dev);
gpio_init_done = 1;
return 0; list_add_tail(&bank->node, &omap_gpio_list);
return ret;
err_free:
kfree(bank);
err_exit:
return ret;
} }
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) #ifdef CONFIG_ARCH_OMAP2PLUS
static int omap_gpio_suspend(void)
#if defined(CONFIG_PM_SLEEP)
static int omap_gpio_suspend(struct device *dev)
{ {
int i; struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
void __iomem *base = bank->base;
void __iomem *wakeup_enable;
unsigned long flags;
if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) if (!bank->mod_usage || !bank->loses_context)
return 0; return 0;
for (i = 0; i < gpio_bank_count; i++) { if (!bank->regs->wkup_en || !bank->suspend_wakeup)
struct gpio_bank *bank = &gpio_bank[i]; return 0;
void __iomem *wake_status;
void __iomem *wake_clear;
void __iomem *wake_set;
unsigned long flags;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP16XX
case METHOD_GPIO_1610:
wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
break;
#endif
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
case METHOD_GPIO_24XX:
wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
break;
#endif
#ifdef CONFIG_ARCH_OMAP4
case METHOD_GPIO_44XX:
wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
break;
#endif
default:
continue;
}
spin_lock_irqsave(&bank->lock, flags); wakeup_enable = bank->base + bank->regs->wkup_en;
bank->saved_wakeup = __raw_readl(wake_status);
__raw_writel(0xffffffff, wake_clear); spin_lock_irqsave(&bank->lock, flags);
__raw_writel(bank->suspend_wakeup, wake_set); bank->saved_wakeup = __raw_readl(wakeup_enable);
spin_unlock_irqrestore(&bank->lock, flags); _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
} _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
spin_unlock_irqrestore(&bank->lock, flags);
return 0; return 0;
} }
static void omap_gpio_resume(void) static int omap_gpio_resume(struct device *dev)
{ {
int i; struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
void __iomem *base = bank->base;
unsigned long flags;
if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) if (!bank->mod_usage || !bank->loses_context)
return; return 0;
for (i = 0; i < gpio_bank_count; i++) { if (!bank->regs->wkup_en || !bank->saved_wakeup)
struct gpio_bank *bank = &gpio_bank[i]; return 0;
void __iomem *wake_clear;
void __iomem *wake_set;
unsigned long flags;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP16XX
case METHOD_GPIO_1610:
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
break;
#endif
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
case METHOD_GPIO_24XX:
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
break;
#endif
#ifdef CONFIG_ARCH_OMAP4
case METHOD_GPIO_44XX:
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
break;
#endif
default:
continue;
}
spin_lock_irqsave(&bank->lock, flags); spin_lock_irqsave(&bank->lock, flags);
__raw_writel(0xffffffff, wake_clear); _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
__raw_writel(bank->saved_wakeup, wake_set); _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
spin_unlock_irqrestore(&bank->lock, flags); spin_unlock_irqrestore(&bank->lock, flags);
}
}
static struct syscore_ops omap_gpio_syscore_ops = { return 0;
.suspend = omap_gpio_suspend, }
.resume = omap_gpio_resume, #endif /* CONFIG_PM_SLEEP */
};
#endif #if defined(CONFIG_PM_RUNTIME)
static void omap_gpio_restore_context(struct gpio_bank *bank);
#ifdef CONFIG_ARCH_OMAP2PLUS static int omap_gpio_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
u32 l1 = 0, l2 = 0;
unsigned long flags;
static int workaround_enabled; spin_lock_irqsave(&bank->lock, flags);
if (bank->power_mode != OFF_MODE) {
bank->power_mode = 0;
goto update_gpio_context_count;
}
/*
* If going to OFF, remove triggering for all
* non-wakeup GPIOs. Otherwise spurious IRQs will be
* generated. See OMAP2420 Errata item 1.101.
*/
if (!(bank->enabled_non_wakeup_gpios))
goto update_gpio_context_count;
void omap2_gpio_prepare_for_idle(int off_mode) bank->saved_datain = __raw_readl(bank->base +
{ bank->regs->datain);
int i, c = 0; l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
int min = 0; l2 = __raw_readl(bank->base + bank->regs->risingdetect);
if (cpu_is_omap34xx()) bank->saved_fallingdetect = l1;
min = 1; bank->saved_risingdetect = l2;
l1 &= ~bank->enabled_non_wakeup_gpios;
l2 &= ~bank->enabled_non_wakeup_gpios;
for (i = min; i < gpio_bank_count; i++) { __raw_writel(l1, bank->base + bank->regs->fallingdetect);
struct gpio_bank *bank = &gpio_bank[i]; __raw_writel(l2, bank->base + bank->regs->risingdetect);
u32 l1 = 0, l2 = 0;
int j;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) bank->workaround_enabled = true;
clk_disable(bank->dbck);
if (!off_mode) update_gpio_context_count:
continue; if (bank->get_context_loss_count)
bank->context_loss_count =
bank->get_context_loss_count(bank->dev);
/* If going to OFF, remove triggering for all _gpio_dbck_disable(bank);
* non-wakeup GPIOs. Otherwise spurious IRQs will be spin_unlock_irqrestore(&bank->lock, flags);
* generated. See OMAP2420 Errata item 1.101. */
if (!(bank->enabled_non_wakeup_gpios))
continue;
if (cpu_is_omap24xx() || cpu_is_omap34xx()) { return 0;
bank->saved_datain = __raw_readl(bank->base + }
OMAP24XX_GPIO_DATAIN);
l1 = __raw_readl(bank->base +
OMAP24XX_GPIO_FALLINGDETECT);
l2 = __raw_readl(bank->base +
OMAP24XX_GPIO_RISINGDETECT);
}
if (cpu_is_omap44xx()) { static int omap_gpio_runtime_resume(struct device *dev)
bank->saved_datain = __raw_readl(bank->base + {
OMAP4_GPIO_DATAIN); struct platform_device *pdev = to_platform_device(dev);
l1 = __raw_readl(bank->base + struct gpio_bank *bank = platform_get_drvdata(pdev);
OMAP4_GPIO_FALLINGDETECT); int context_lost_cnt_after;
l2 = __raw_readl(bank->base + u32 l = 0, gen, gen0, gen1;
OMAP4_GPIO_RISINGDETECT); unsigned long flags;
}
bank->saved_fallingdetect = l1; spin_lock_irqsave(&bank->lock, flags);
bank->saved_risingdetect = l2; _gpio_dbck_enable(bank);
l1 &= ~bank->enabled_non_wakeup_gpios; if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
l2 &= ~bank->enabled_non_wakeup_gpios; spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
if (cpu_is_omap24xx() || cpu_is_omap34xx()) { if (bank->get_context_loss_count) {
__raw_writel(l1, bank->base + context_lost_cnt_after =
OMAP24XX_GPIO_FALLINGDETECT); bank->get_context_loss_count(bank->dev);
__raw_writel(l2, bank->base + if (context_lost_cnt_after != bank->context_loss_count ||
OMAP24XX_GPIO_RISINGDETECT); !context_lost_cnt_after) {
omap_gpio_restore_context(bank);
} else {
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
} }
}
if (cpu_is_omap44xx()) { __raw_writel(bank->saved_fallingdetect,
__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); bank->base + bank->regs->fallingdetect);
__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); __raw_writel(bank->saved_risingdetect,
} bank->base + bank->regs->risingdetect);
l = __raw_readl(bank->base + bank->regs->datain);
c++; /*
} * Check if any of the non-wakeup interrupt GPIOs have changed
if (!c) { * state. If so, generate an IRQ by software. This is
workaround_enabled = 0; * horribly racy, but it's the best we can do to work around
return; * this silicon bug.
} */
workaround_enabled = 1; l ^= bank->saved_datain;
} l &= bank->enabled_non_wakeup_gpios;
void omap2_gpio_resume_after_idle(void) /*
{ * No need to generate IRQs for the rising edge for gpio IRQs
int i; * configured with falling edge only; and vice versa.
int min = 0; */
gen0 = l & bank->saved_fallingdetect;
gen0 &= bank->saved_datain;
if (cpu_is_omap34xx()) gen1 = l & bank->saved_risingdetect;
min = 1; gen1 &= ~(bank->saved_datain);
for (i = min; i < gpio_bank_count; i++) {
struct gpio_bank *bank = &gpio_bank[i];
u32 l = 0, gen, gen0, gen1;
int j;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) /* FIXME: Consider GPIO IRQs with level detections properly! */
clk_enable(bank->dbck); gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
/* Consider all GPIO IRQs needed to be updated */
gen |= gen0 | gen1;
if (!workaround_enabled) if (gen) {
continue; u32 old0, old1;
if (!(bank->enabled_non_wakeup_gpios)) old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
continue; old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) { if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
__raw_writel(bank->saved_fallingdetect, __raw_writel(old0 | gen, bank->base +
bank->base + OMAP24XX_GPIO_FALLINGDETECT); bank->regs->leveldetect0);
__raw_writel(bank->saved_risingdetect, __raw_writel(old1 | gen, bank->base +
bank->base + OMAP24XX_GPIO_RISINGDETECT); bank->regs->leveldetect1);
l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
} }
if (cpu_is_omap44xx()) { if (cpu_is_omap44xx()) {
__raw_writel(bank->saved_fallingdetect, __raw_writel(old0 | l, bank->base +
bank->base + OMAP4_GPIO_FALLINGDETECT); bank->regs->leveldetect0);
__raw_writel(bank->saved_risingdetect, __raw_writel(old1 | l, bank->base +
bank->base + OMAP4_GPIO_RISINGDETECT); bank->regs->leveldetect1);
l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
}
/* Check if any of the non-wakeup interrupt GPIOs have changed
* state. If so, generate an IRQ by software. This is
* horribly racy, but it's the best we can do to work around
* this silicon bug. */
l ^= bank->saved_datain;
l &= bank->enabled_non_wakeup_gpios;
/*
* No need to generate IRQs for the rising edge for gpio IRQs
* configured with falling edge only; and vice versa.
*/
gen0 = l & bank->saved_fallingdetect;
gen0 &= bank->saved_datain;
gen1 = l & bank->saved_risingdetect;
gen1 &= ~(bank->saved_datain);
/* FIXME: Consider GPIO IRQs with level detections properly! */
gen = l & (~(bank->saved_fallingdetect) &
~(bank->saved_risingdetect));
/* Consider all GPIO IRQs needed to be updated */
gen |= gen0 | gen1;
if (gen) {
u32 old0, old1;
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
old0 = __raw_readl(bank->base +
OMAP24XX_GPIO_LEVELDETECT0);
old1 = __raw_readl(bank->base +
OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0 | gen, bank->base +
OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1 | gen, bank->base +
OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0, bank->base +
OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1, bank->base +
OMAP24XX_GPIO_LEVELDETECT1);
}
if (cpu_is_omap44xx()) {
old0 = __raw_readl(bank->base +
OMAP4_GPIO_LEVELDETECT0);
old1 = __raw_readl(bank->base +
OMAP4_GPIO_LEVELDETECT1);
__raw_writel(old0 | l, bank->base +
OMAP4_GPIO_LEVELDETECT0);
__raw_writel(old1 | l, bank->base +
OMAP4_GPIO_LEVELDETECT1);
__raw_writel(old0, bank->base +
OMAP4_GPIO_LEVELDETECT0);
__raw_writel(old1, bank->base +
OMAP4_GPIO_LEVELDETECT1);
}
} }
__raw_writel(old0, bank->base + bank->regs->leveldetect0);
__raw_writel(old1, bank->base + bank->regs->leveldetect1);
} }
bank->workaround_enabled = false;
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
} }
#endif /* CONFIG_PM_RUNTIME */
#endif void omap2_gpio_prepare_for_idle(int pwr_mode)
{
struct gpio_bank *bank;
list_for_each_entry(bank, &omap_gpio_list, node) {
if (!bank->mod_usage || !bank->loses_context)
continue;
bank->power_mode = pwr_mode;
pm_runtime_put_sync_suspend(bank->dev);
}
}
#ifdef CONFIG_ARCH_OMAP3 void omap2_gpio_resume_after_idle(void)
/* save the registers of bank 2-6 */
void omap_gpio_save_context(void)
{ {
int i; struct gpio_bank *bank;
/* saving banks from 2-6 only since GPIO1 is in WKUP */ list_for_each_entry(bank, &omap_gpio_list, node) {
for (i = 1; i < gpio_bank_count; i++) { if (!bank->mod_usage || !bank->loses_context)
struct gpio_bank *bank = &gpio_bank[i]; continue;
gpio_context[i].irqenable1 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); pm_runtime_get_sync(bank->dev);
gpio_context[i].irqenable2 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
gpio_context[i].wake_en =
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
gpio_context[i].ctrl =
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
gpio_context[i].oe =
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
gpio_context[i].leveldetect0 =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
gpio_context[i].leveldetect1 =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
gpio_context[i].risingdetect =
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
gpio_context[i].fallingdetect =
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
gpio_context[i].dataout =
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
} }
} }
/* restore the required registers of bank 2-6 */ #if defined(CONFIG_PM_RUNTIME)
void omap_gpio_restore_context(void) static void omap_gpio_restore_context(struct gpio_bank *bank)
{ {
int i; __raw_writel(bank->context.wake_en,
bank->base + bank->regs->wkup_en);
for (i = 1; i < gpio_bank_count; i++) { __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
struct gpio_bank *bank = &gpio_bank[i]; __raw_writel(bank->context.leveldetect0,
__raw_writel(gpio_context[i].irqenable1, bank->base + bank->regs->leveldetect0);
bank->base + OMAP24XX_GPIO_IRQENABLE1); __raw_writel(bank->context.leveldetect1,
__raw_writel(gpio_context[i].irqenable2, bank->base + bank->regs->leveldetect1);
bank->base + OMAP24XX_GPIO_IRQENABLE2); __raw_writel(bank->context.risingdetect,
__raw_writel(gpio_context[i].wake_en, bank->base + bank->regs->risingdetect);
bank->base + OMAP24XX_GPIO_WAKE_EN); __raw_writel(bank->context.fallingdetect,
__raw_writel(gpio_context[i].ctrl, bank->base + bank->regs->fallingdetect);
bank->base + OMAP24XX_GPIO_CTRL); if (bank->regs->set_dataout && bank->regs->clr_dataout)
__raw_writel(gpio_context[i].oe, __raw_writel(bank->context.dataout,
bank->base + OMAP24XX_GPIO_OE); bank->base + bank->regs->set_dataout);
__raw_writel(gpio_context[i].leveldetect0, else
bank->base + OMAP24XX_GPIO_LEVELDETECT0); __raw_writel(bank->context.dataout,
__raw_writel(gpio_context[i].leveldetect1, bank->base + bank->regs->dataout);
bank->base + OMAP24XX_GPIO_LEVELDETECT1); __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
__raw_writel(gpio_context[i].risingdetect,
bank->base + OMAP24XX_GPIO_RISINGDETECT); if (bank->dbck_enable_mask) {
__raw_writel(gpio_context[i].fallingdetect, __raw_writel(bank->context.debounce, bank->base +
bank->base + OMAP24XX_GPIO_FALLINGDETECT); bank->regs->debounce);
__raw_writel(gpio_context[i].dataout, __raw_writel(bank->context.debounce_en,
bank->base + OMAP24XX_GPIO_DATAOUT); bank->base + bank->regs->debounce_en);
} }
__raw_writel(bank->context.irqenable1,
bank->base + bank->regs->irqenable);
__raw_writel(bank->context.irqenable2,
bank->base + bank->regs->irqenable2);
} }
#endif /* CONFIG_PM_RUNTIME */
#else
#define omap_gpio_suspend NULL
#define omap_gpio_resume NULL
#define omap_gpio_runtime_suspend NULL
#define omap_gpio_runtime_resume NULL
#endif #endif
static const struct dev_pm_ops gpio_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
NULL)
};
static struct platform_driver omap_gpio_driver = { static struct platform_driver omap_gpio_driver = {
.probe = omap_gpio_probe, .probe = omap_gpio_probe,
.driver = { .driver = {
.name = "omap_gpio", .name = "omap_gpio",
.pm = &gpio_pm_ops,
}, },
}; };
...@@ -1578,17 +1415,3 @@ static int __init omap_gpio_drv_reg(void) ...@@ -1578,17 +1415,3 @@ static int __init omap_gpio_drv_reg(void)
return platform_driver_register(&omap_gpio_driver); return platform_driver_register(&omap_gpio_driver);
} }
postcore_initcall(omap_gpio_drv_reg); postcore_initcall(omap_gpio_drv_reg);
static int __init omap_gpio_sysinit(void)
{
mpuio_init();
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
if (cpu_is_omap16xx() || cpu_class_is_omap2())
register_syscore_ops(&omap_gpio_syscore_ops);
#endif
return 0;
}
arch_initcall(omap_gpio_sysinit);
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