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Commit 134d4d1c authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge kroah.com:/home/greg/linux/BK/bleed-2.5 

into kroah.com:/home/greg/linux/BK/tty-2.5
parents ebb11c7e 85567a40
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Documentation/00-INDEX
View file @ 134d4d1c
......@@ -182,6 +182,8 @@ ramdisk.txt
- short guide on how to set up and use the RAM disk.
riscom8.txt
- notes on using the RISCom/8 multi-port serial driver.
rocket.txt
- info on installing/using the Comtrol RocketPort multiport serial driver
rtc.txt
- notes on how to use the Real Time Clock (aka CMOS clock) driver.
s390/
......
Documentation/rocket.txt 0 → 100644
View file @ 134d4d1c
Comtrol(tm) RocketPort(R)/RocketModem(TM) Series
Device Driver for the Linux Operating System
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
PRODUCT OVERVIEW
----------------
This driver provides a loadable kernel driver for the Comtrol RocketPort
and RocketModem PCI boards. These boards provide, 2, 4, 8, 16, or 32
high-speed serial ports or modems. This driver supports up to a combination
of four RocketPort or RocketModems boards in one machine simultaneously.
This file assumes that you are using the RocketPort driver which is
integrated into the kernel sources.
The driver can also be installed as an external module using the usual
"make;make install" routine. This external module driver, obtainable
from the Comtrol website listed below, is useful for updating the driver
or installing it into kernels which do not have the driver configured
into them. Installations instructions for the external module
are in the included README and HW_INSTALL files.
RocketPort ISA and RocketModem II PCI boards are also supported by this
driver, but must use the external module driver for configuration reasons.
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
INSTALLATION PROCEDURES
-----------------------
RocketPort/RocketModem PCI cards require no driver configuration, they are
automatically detected and configured.
The RocketPort driver can be installed as a module (recommended) or built
into the kernel. This is selected, as for other drivers, through the `make config`
command from the root of the Linux source tree during the kernel build process.
The RocketPort/RocketModem serial ports installed by this driver are assigned
device major number 46, and will be named /dev/ttyRx, where x is the port number
starting at zero (ex. /dev/ttyR0, /devttyR1, ...). If you have multiple cards
installed in the system, the mapping of port names to serial ports is displayed
in the system log at /var/log/messages.
If installed as a module, the module must be loaded. This can be done
manually by entering "modprobe rocket". To have the module loaded automatically
upon system boot, edit the /etc/modules.conf file and add the line
"alias char-major-46 rocket".
In order to use the ports, their device names (nodes) must be created with mknod.
This is only required once, the system will retain the names once created. To
create the RocketPort/RocketModem device names, use the command
"mknod /dev/ttyRx c 46 x" where x is the port number starting at zero. For example:
>mknod /dev/ttyR0 c 46 0
>mknod /dev/ttyR1 c 46 1
>mknod /dev/ttyR2 c 46 2
The Linux script MAKEDEV will create the first 16 ttyRx device names (nodes) for you:
>/dev/MAKEDEV ttyR
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
REPORTING BUGS
--------------
For technical support, please provide the following
information: Driver version, kernel release, distribution of
kernel, and type of board you are using. Error messages and log
printouts port configuration details are especially helpful.
USA
Phone: (612) 494-4100
FAX: (612) 494-4199
email: support@comtrol.com
Comtrol Europe
Phone: +44 (0) 1 869 323-220
FAX: +44 (0) 1 869 323-211
email: support@comtrol.co.uk
Web: http://www.comtrol.com
FTP: ftp.comtrol.com
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
MAINTAINERS
View file @ 134d4d1c
......@@ -1524,6 +1524,12 @@ L: reiserfs-list@namesys.com
W: http://www.namesys.com
S: Supported
ROCKETPORT DRIVER
P: Comtrol Corp.
M: support@comtrol.com
W: http://www.comtrol.com
S: Maintained
ROSE NETWORK LAYER
P: Ralf Baechle
M: ralf@linux-mips.org
......
drivers/char/Kconfig
View file @ 134d4d1c
......@@ -94,18 +94,21 @@ config COMPUTONE
two modules called ip2 and ip2main.
config ROCKETPORT
tristate "Comtrol Rocketport support"
tristate "Comtrol RocketPort support"
depends on SERIAL_NONSTANDARD
help
This is a driver for the Comtrol Rocketport cards which provide
multiple serial ports. You would need something like this to connect
more than two modems to your Linux box, for instance in order to
become a dial-in server.
This driver supports Comtrol RocketPort and RocketModem PCI boards.
These boards provide 2, 4, 8, 16, or 32 high-speed serial ports or
modems. For information about the RocketPort/RocketModem boards
and this driver read <file:Documentation/rocket.txt>.
If you want to compile this driver as a module, say M here and read
<file:Documentation/modules.txt>. The module will be called
rocket.
If you want to compile this driver into the kernel, say Y here. If
you don't have a Comtrol RocketPort/RocketModem card installed, say N.
config CYCLADES
tristate "Cyclades async mux support"
depends on SERIAL_NONSTANDARD
......
drivers/char/rocket.c
View file @ 134d4d1c
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/char/rocket.h 0 → 100644
View file @ 134d4d1c
/*
* rocket.h --- the exported interface of the rocket driver to
* its configuration program.
*
* Written by Theodore Ts'o, Copyright 1997.
*
* Copyright 1994, 1997, 2003 Comtrol Corporation. All Rights Reserved.
*
* The following source code is subject to Comtrol Corporation's
* Developer's License Agreement.
*
* This source code is protected by United States copyright law and
* international copyright treaties.
*
* This source code may only be used to develop software products that
* will operate with Comtrol brand hardware.
*
* You may not reproduce nor distribute this source code in its original
* form but must produce a derivative work which includes portions of
* this source code only.
*
* The portions of this source code which you use in your derivative
* work must bear Comtrol's copyright notice:
*
* Copyright 1994 Comtrol Corporation.
*
*/
/* Model Information Struct */
typedef struct {
unsigned long model;
char modelString[80];
unsigned long numPorts;
int loadrm2;
int startingPortNumber;
} rocketModel_t;
struct rocket_config {
int line;
int flags;
int closing_wait;
int close_delay;
int port;
int reserved[32];
};
struct rocket_ports {
int tty_major;
int callout_major;
rocketModel_t rocketModel[8];
};
struct rocket_version {
char rocket_version[32];
char rocket_date[32];
char reserved[64];
};
/*
* Rocketport flags
*/
#define ROCKET_CALLOUT_NOHUP 0x00000001
#define ROCKET_FORCE_CD 0x00000002
#define ROCKET_HUP_NOTIFY 0x00000004
#define ROCKET_SPLIT_TERMIOS 0x00000008
#define ROCKET_SPD_MASK 0x00000070
#define ROCKET_SPD_HI 0x00000010 /* Use 56000 instead of 38400 bps */
#define ROCKET_SPD_VHI 0x00000020 /* Use 115200 instead of 38400 bps */
#define ROCKET_SPD_SHI 0x00000030 /* Use 230400 instead of 38400 bps */
#define ROCKET_SPD_WARP 0x00000040 /* Use 460800 instead of 38400 bps */
#define ROCKET_SAK 0x00000080
#define ROCKET_SESSION_LOCKOUT 0x00000100
#define ROCKET_PGRP_LOCKOUT 0x00000200
#define ROCKET_RTS_TOGGLE 0x00000400
#define ROCKET_MODE_MASK 0x00003000
#define ROCKET_MODE_RS232 0x00000000
#define ROCKET_MODE_RS485 0x00001000
#define ROCKET_MODE_RS422 0x00002000
#define ROCKET_FLAGS 0x00003FFF
#define ROCKET_USR_MASK 0x0071 /* Legal flags that non-privileged
* users can set or reset */
/*
* For closing_wait and closing_wait2
*/
#define ROCKET_CLOSING_WAIT_NONE 65535
#define ROCKET_CLOSING_WAIT_INF 0
/*
* Rocketport ioctls -- "RP"
*/
#define RCKP_GET_STRUCT 0x00525001
#define RCKP_GET_CONFIG 0x00525002
#define RCKP_SET_CONFIG 0x00525003
#define RCKP_GET_PORTS 0x00525004
#define RCKP_RESET_RM2 0x00525005
#define RCKP_GET_VERSION 0x00525006
/* Rocketport Models */
#define MODEL_RP32INTF 0x0001 /* RP 32 port w/external I/F */
#define MODEL_RP8INTF 0x0002 /* RP 8 port w/external I/F */
#define MODEL_RP16INTF 0x0003 /* RP 16 port w/external I/F */
#define MODEL_RP8OCTA 0x0005 /* RP 8 port w/octa cable */
#define MODEL_RP4QUAD 0x0004 /* RP 4 port w/quad cable */
#define MODEL_RP8J 0x0006 /* RP 8 port w/RJ11 connectors */
#define MODEL_RP4J 0x0007 /* RP 4 port w/RJ45 connectors */
#define MODEL_RP8SNI 0x0008 /* RP 8 port w/ DB78 SNI connector */
#define MODEL_RP16SNI 0x0009 /* RP 16 port w/ DB78 SNI connector */
#define MODEL_RPP4 0x000A /* RP Plus 4 port */
#define MODEL_RPP8 0x000B /* RP Plus 8 port */
#define MODEL_RP2_232 0x000E /* RP Plus 2 port RS232 */
#define MODEL_RP2_422 0x000F /* RP Plus 2 port RS232 */
/* Rocketmodem II Models */
#define MODEL_RP6M 0x000C /* RM 6 port */
#define MODEL_RP4M 0x000D /* RM 4 port */
/* Universal PCI boards */
#define MODEL_UPCI_RP32INTF 0x0801 /* RP UPCI 32 port w/external I/F */
#define MODEL_UPCI_RP8INTF 0x0802 /* RP UPCI 8 port w/external I/F */
#define MODEL_UPCI_RP16INTF 0x0803 /* RP UPCI 16 port w/external I/F */
#define MODEL_UPCI_RP8OCTA 0x0805 /* RP UPCI 8 port w/octa cable */
#define MODEL_UPCI_RM3_8PORT 0x080C /* RP UPCI Rocketmodem III 8 port */
#define MODEL_UPCI_RM3_4PORT 0x080C /* RP UPCI Rocketmodem III 4 port */
/* Compact PCI 16 port */
#define MODEL_CPCI_RP16INTF 0x0903 /* RP Compact PCI 16 port w/external I/F */
/* All ISA boards */
#define MODEL_ISA 0x1000
drivers/char/rocket_int.h
View file @ 134d4d1c
......@@ -3,9 +3,7 @@
*
* Written by Theodore Ts'o, Copyright 1997.
*
* Portions of this file are....
*
* Copyright 1994 Comtrol Corporation. All Rights Reserved.
* Copyright 1994, 1997, 2003 Comtrol Corporation. All Rights Reserved.
*
* The following source code is subject to Comtrol Corporation's
* Developer's License Agreement.
......@@ -28,23 +26,16 @@
*/
/*
* Begin Comtrol-provided headers, et. al.
* Definition of the types in rcktpt_type
*/
/*
user definitions for Rocket Toolkit
The following typedefs and defines must be established
depending on the platform the toolkit is being used
with.
*/
/************************************************************
The following sets up the world for use with Linux
************************************************************/
#define ROCKET_TYPE_NORMAL 0
#define ROCKET_TYPE_MODEM 1
#define ROCKET_TYPE_MODEMII 2
#define ROCKET_TYPE_MODEMIII 3
#define ROCKET_TYPE_PC104 4
#include <asm/io.h>
#include <asm/byteorder.h>
typedef unsigned char Byte_t;
typedef unsigned int ByteIO_t;
......@@ -55,17 +46,71 @@ typedef unsigned int WordIO_t;
typedef unsigned long DWord_t;
typedef unsigned int DWordIO_t;
/*
* Note! Normally the Linux I/O macros already take care of
* byte-swapping the I/O instructions. However, all accesses using
* sOutDW aren't really 32-bit accesses, but should be handled in byte
* order. Hence the use of the cpu_to_le32() macro to byte-swap
* things to no-op the byte swapping done by the big-endian outl()
* instruction.
*/
#ifdef ROCKET_DEBUG_IO
static inline void sOutB(unsigned short port, unsigned char value)
{
#ifdef ROCKET_DEBUG_IO
printk("sOutB(%x, %x)...", port, value);
#endif
outb_p(value, port);
}
static inline void sOutW(unsigned short port, unsigned short value)
{
#ifdef ROCKET_DEBUG_IO
printk("sOutW(%x, %x)...", port, value);
#endif
outw_p(value, port);
}
static inline void sOutDW(unsigned short port, unsigned long value)
{
#ifdef ROCKET_DEBUG_IO
printk("sOutDW(%x, %lx)...", port, value);
#endif
outl_p(cpu_to_le32(value), port);
}
static inline unsigned char sInB(unsigned short port)
{
return inb_p(port);
}
static inline unsigned short sInW(unsigned short port)
{
return inw_p(port);
}
#else /* !ROCKET_DEBUG_IO */
#define sOutB(a, b) outb_p(b, a)
#define sOutW(a, b) outw_p(b, a)
#define sOutDW(a, b) outl_p(b, a)
#define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
#define sInB(a) (inb_p(a))
#define sInW(a) (inw_p(a))
#endif /* ROCKET_DEBUG_IO */
/* This is used to move arrays of bytes so byte swapping isn't
* appropriate. On Linux 2.3 and above outsw is the same as
* outsw_ns, but we use the old form for compatibility with
* old kernels. */
#if defined(__BIG_ENDIAN) && (LINUX_VERSION_CODE < VERSION_CODE(2,3,0))
#define sOutStrW(port, addr, count) if (count) outsw_ns(port, addr, count)
#define sInStrW(port, addr, count) if (count) insw_ns(port, addr, count)
#else
#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
#define sInStrW(port, addr, count) if (count) insw(port, addr, count)
#endif
#define sOutStrW(port, addr, count) outsw(port, addr, count)
#define sInStrW(port, addr, count) insw(port, addr, count)
#define CTL_SIZE 4
#define CTL_SIZE 8
#define AIOP_CTL_SIZE 4
#define CHAN_AIOP_SIZE 8
#define MAX_PORTS_PER_AIOP 8
......@@ -78,219 +123,159 @@ typedef unsigned int DWordIO_t;
#define isMC 2
/* Controller ID numbers */
#define CTLID_NULL -1 /* no controller exists */
#define CTLID_0001 0x0001 /* controller release 1 */
#define CTLID_NULL -1 /* no controller exists */
#define CTLID_0001 0x0001 /* controller release 1 */
/* AIOP ID numbers, identifies AIOP type implementing channel */
#define AIOPID_NULL -1 /* no AIOP or channel exists */
#define AIOPID_0001 0x0001 /* AIOP release 1 */
#define AIOPID_NULL -1 /* no AIOP or channel exists */
#define AIOPID_0001 0x0001 /* AIOP release 1 */
#define NULLDEV -1 /* identifies non-existant device */
#define NULLCTL -1 /* identifies non-existant controller */
#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
#define NULLAIOP -1 /* identifies non-existant AIOP */
#define NULLCHAN -1 /* identifies non-existant channel */
#define NULLDEV -1 /* identifies non-existant device */
#define NULLCTL -1 /* identifies non-existant controller */
#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
#define NULLAIOP -1 /* identifies non-existant AIOP */
#define NULLCHAN -1 /* identifies non-existant channel */
/************************************************************************
Global Register Offsets - Direct Access - Fixed values
************************************************************************/
#define _CMD_REG 0x38 /* Command Register 8 Write */
#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
#define _UNUSED 0x3B /* Unused 8 */
#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
#define _CMD_REG 0x38 /* Command Register 8 Write */
#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
#define _UNUSED 0x3B /* Unused 8 */
#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
/************************************************************************
Channel Register Offsets for 1st channel in AIOP - Direct Access
************************************************************************/
#define _TD0 0x00 /* Transmit Data 16 Write */
#define _RD0 0x00 /* Receive Data 16 Read */
#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
#define _TD0 0x00 /* Transmit Data 16 Write */
#define _RD0 0x00 /* Receive Data 16 Read */
#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
/************************************************************************
Tx Control Register Offsets - Indexed - External - Fixed
************************************************************************/
#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
/************************************************************************
Memory Controller Register Offsets - Indexed - External - Fixed
************************************************************************/
#define _RX_FIFO 0x000 /* Rx FIFO */
#define _TX_FIFO 0x800 /* Tx FIFO */
#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
#define TXFIFO_SIZE 255 /* size of Tx FIFO */
#define RXFIFO_SIZE 1023 /* size of Rx FIFO */
#define _RX_FIFO 0x000 /* Rx FIFO */
#define _TX_FIFO 0x800 /* Tx FIFO */
#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
#define TXFIFO_SIZE 255 /* size of Tx FIFO */
#define RXFIFO_SIZE 1023 /* size of Rx FIFO */
/************************************************************************
Tx Priority Buffer - Indexed - External - Fixed
************************************************************************/
#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
#define TXP_SIZE 0x20 /* 32 bytes */
#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
#define TXP_SIZE 0x20 /* 32 bytes */
/************************************************************************
Channel Register Offsets - Indexed - Internal - Fixed
************************************************************************/
#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
#define _BAUD 0xFF4 /* Baud Rate 16 Write */
#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
#if 0
#define CLOCK_PRESC 0x14 /* ?????? new mod 4 (divide by 5) prescale */
#define BRD50 9215
#define BRD75 6143
#define BRD110 4188
#define BRD134 3438
#define BRD150 3071
#define BRD200 2303
#define BRD300 1535
#define BRD600 767
#define BRD1200 383
#define BRD1800 255
#define BRD2000 229
#define BRD2400 191
#define BRD3600 127
#define BRD4800 95
#define BRD7200 63
#define BRD9600 47
#define BRD14400 31
#define BRD19200 23
#define BRD38400 11
#define BRD57600 7
#define BRD76800 5
#define BRD115200 3
#define BRD230400 1
#define BRD460800 0
#endif
#if 0
/* Old clock prescale definition and baud rates associated with it */
#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
#define BRD50 4607
#define BRD75 3071
#define BRD110 2094
#define BRD134 1712
#define BRD150 1535
#define BRD200 1151
#define BRD300 767
#define BRD600 383
#define BRD1200 191
#define BRD1800 127
#define BRD2000 114
#define BRD2400 95
#define BRD3600 64
#define BRD4800 47
#define BRD7200 31
#define BRD9600 23
#define BRD14400 15
#define BRD19200 11
#define BRD38400 5
#define BRD57600 3
#define BRD76800 2
#define BRD115200 1
#define BRD230400 0
#endif
#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
#define _BAUD 0xFF4 /* Baud Rate 16 Write */
#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
#define STMBREAK 0x08 /* BREAK */
#define STMFRAME 0x04 /* framing error */
#define STMRCVROVR 0x02 /* receiver over run error */
#define STMPARITY 0x01 /* parity error */
#define STMBREAK 0x08 /* BREAK */
#define STMFRAME 0x04 /* framing error */
#define STMRCVROVR 0x02 /* receiver over run error */
#define STMPARITY 0x01 /* parity error */
#define STMERROR (STMBREAK | STMFRAME | STMPARITY)
#define STMBREAKH 0x800 /* BREAK */
#define STMFRAMEH 0x400 /* framing error */
#define STMRCVROVRH 0x200 /* receiver over run error */
#define STMPARITYH 0x100 /* parity error */
#define STMBREAKH 0x800 /* BREAK */
#define STMFRAMEH 0x400 /* framing error */
#define STMRCVROVRH 0x200 /* receiver over run error */
#define STMPARITYH 0x100 /* parity error */
#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
#define CTS_ACT 0x20 /* CTS input asserted */
#define DSR_ACT 0x10 /* DSR input asserted */
#define CD_ACT 0x08 /* CD input asserted */
#define TXFIFOMT 0x04 /* Tx FIFO is empty */
#define TXSHRMT 0x02 /* Tx shift register is empty */
#define RDA 0x01 /* Rx data available */
#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
#define STATMODE 0x8000 /* status mode enable bit */
#define RXFOVERFL 0x2000 /* receive FIFO overflow */
#define RX2MATCH 0x1000 /* receive compare byte 2 match */
#define RX1MATCH 0x0800 /* receive compare byte 1 match */
#define RXBREAK 0x0400 /* received BREAK */
#define RXFRAME 0x0200 /* received framing error */
#define RXPARITY 0x0100 /* received parity error */
#define CTS_ACT 0x20 /* CTS input asserted */
#define DSR_ACT 0x10 /* DSR input asserted */
#define CD_ACT 0x08 /* CD input asserted */
#define TXFIFOMT 0x04 /* Tx FIFO is empty */
#define TXSHRMT 0x02 /* Tx shift register is empty */
#define RDA 0x01 /* Rx data available */
#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
#define STATMODE 0x8000 /* status mode enable bit */
#define RXFOVERFL 0x2000 /* receive FIFO overflow */
#define RX2MATCH 0x1000 /* receive compare byte 2 match */
#define RX1MATCH 0x0800 /* receive compare byte 1 match */
#define RXBREAK 0x0400 /* received BREAK */
#define RXFRAME 0x0200 /* received framing error */
#define RXPARITY 0x0100 /* received parity error */
#define STATERROR (RXBREAK | RXFRAME | RXPARITY)
#define CTSFC_EN 0x80 /* CTS flow control enable bit */
#define RTSTOG_EN 0x40 /* RTS toggle enable bit */
#define TXINT_EN 0x10 /* transmit interrupt enable */
#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
#define PARITY_EN 0x04 /* enable parity (0 = no parity) */
#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
#define SETBREAK 0x10 /* send break condition (must clear) */
#define LOCALLOOP 0x08 /* local loopback set for test */
#define SET_DTR 0x04 /* assert DTR */
#define SET_RTS 0x02 /* assert RTS */
#define TX_ENABLE 0x01 /* enable transmitter */
#define RTSFC_EN 0x40 /* RTS flow control enable */
#define RXPROC_EN 0x20 /* receive processor enable */
#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
#define TRIG_1 0x08 /* trigger level 1 char */
#define TRIG_1_2 0x10 /* trigger level 1/2 */
#define TRIG_7_8 0x18 /* trigger level 7/8 */
#define TRIG_MASK 0x18 /* trigger level mask */
#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
#define RXINT_EN 0x02 /* Rx interrupt enable */
#define MCINT_EN 0x01 /* modem change interrupt enable */
#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
#define SRC_INT 0x08 /* special receive condition interrupt */
#define DELTA_CD 0x04 /* CD change interrupt */
#define DELTA_CTS 0x02 /* CTS change interrupt */
#define DELTA_DSR 0x01 /* DSR change interrupt */
#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
#define IGN2_EN 0x08 /* ignore byte 2 enable */
#define IGN1_EN 0x04 /* ignore byte 1 enable */
#define COMP2_EN 0x02 /* compare byte 2 enable */
#define COMP1_EN 0x01 /* compare byte 1 enable */
#define RESET_ALL 0x80 /* reset AIOP (all channels) */
#define TXOVERIDE 0x40 /* Transmit software off override */
#define RESETUART 0x20 /* reset channel's UART */
#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
#define INTSTAT0 0x01 /* AIOP 0 interrupt status */
#define INTSTAT1 0x02 /* AIOP 1 interrupt status */
#define INTSTAT2 0x04 /* AIOP 2 interrupt status */
#define INTSTAT3 0x08 /* AIOP 3 interrupt status */
#define INTR_EN 0x08 /* allow interrupts to host */
#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
#define CTSFC_EN 0x80 /* CTS flow control enable bit */
#define RTSTOG_EN 0x40 /* RTS toggle enable bit */
#define TXINT_EN 0x10 /* transmit interrupt enable */
#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
#define PARITY_EN 0x04 /* enable parity (0 = no parity) */
#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
#define SETBREAK 0x10 /* send break condition (must clear) */
#define LOCALLOOP 0x08 /* local loopback set for test */
#define SET_DTR 0x04 /* assert DTR */
#define SET_RTS 0x02 /* assert RTS */
#define TX_ENABLE 0x01 /* enable transmitter */
#define RTSFC_EN 0x40 /* RTS flow control enable */
#define RXPROC_EN 0x20 /* receive processor enable */
#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
#define TRIG_1 0x08 /* trigger level 1 char */
#define TRIG_1_2 0x10 /* trigger level 1/2 */
#define TRIG_7_8 0x18 /* trigger level 7/8 */
#define TRIG_MASK 0x18 /* trigger level mask */
#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
#define RXINT_EN 0x02 /* Rx interrupt enable */
#define MCINT_EN 0x01 /* modem change interrupt enable */
#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
#define SRC_INT 0x08 /* special receive condition interrupt */
#define DELTA_CD 0x04 /* CD change interrupt */
#define DELTA_CTS 0x02 /* CTS change interrupt */
#define DELTA_DSR 0x01 /* DSR change interrupt */
#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
#define IGN2_EN 0x08 /* ignore byte 2 enable */
#define IGN1_EN 0x04 /* ignore byte 1 enable */
#define COMP2_EN 0x02 /* compare byte 2 enable */
#define COMP1_EN 0x01 /* compare byte 1 enable */
#define RESET_ALL 0x80 /* reset AIOP (all channels) */
#define TXOVERIDE 0x40 /* Transmit software off override */
#define RESETUART 0x20 /* reset channel's UART */
#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
#define INTSTAT0 0x01 /* AIOP 0 interrupt status */
#define INTSTAT1 0x02 /* AIOP 1 interrupt status */
#define INTSTAT2 0x04 /* AIOP 2 interrupt status */
#define INTSTAT3 0x08 /* AIOP 3 interrupt status */
#define INTR_EN 0x08 /* allow interrupts to host */
#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
/**************************************************************************
MUDBAC remapped for PCI
......@@ -299,14 +284,22 @@ Channel Register Offsets - Indexed - Internal - Fixed
#define _CFG_INT_PCI 0x40
#define _PCI_INT_FUNC 0x3A
#define PCI_STROB 0x2000 /* bit 13 of int aiop register */
#define INTR_EN_PCI 0x0010 /* allow interrupts to host */
#define PCI_STROB 0x2000 /* bit 13 of int aiop register */
#define INTR_EN_PCI 0x0010 /* allow interrupts to host */
#define CHAN3_EN 0x08 /* enable AIOP 3 */
#define CHAN2_EN 0x04 /* enable AIOP 2 */
#define CHAN1_EN 0x02 /* enable AIOP 1 */
#define CHAN0_EN 0x01 /* enable AIOP 0 */
/*
* Definitions for Universal PCI board registers
*/
#define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */
#define _PCI_9030_GPIO_CTRL 0x54
#define PCI_INT_CTRL_AIOP 0x0001
#define PCI_GPIO_CTRL_8PORT 0x4000
#define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */
#define CHAN3_EN 0x08 /* enable AIOP 3 */
#define CHAN2_EN 0x04 /* enable AIOP 2 */
#define CHAN1_EN 0x02 /* enable AIOP 1 */
#define CHAN0_EN 0x01 /* enable AIOP 0 */
#define FREQ_DIS 0x00
#define FREQ_274HZ 0x60
#define FREQ_137HZ 0x50
......@@ -314,75 +307,110 @@ Channel Register Offsets - Indexed - Internal - Fixed
#define FREQ_34HZ 0x30
#define FREQ_17HZ 0x20
#define FREQ_9HZ 0x10
#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
#define RDATASIZE 72
#define RREGDATASIZE 52
/*
* AIOP interrupt bits for ISA/PCI boards and UPCI boards.
*/
#define AIOP_INTR_BIT_0 0x0001
#define AIOP_INTR_BIT_1 0x0002
#define AIOP_INTR_BIT_2 0x0004
#define AIOP_INTR_BIT_3 0x0008
#define AIOP_INTR_BITS ( \
AIOP_INTR_BIT_0 \
| AIOP_INTR_BIT_1 \
| AIOP_INTR_BIT_2 \
| AIOP_INTR_BIT_3)
#define UPCI_AIOP_INTR_BIT_0 0x0004
#define UPCI_AIOP_INTR_BIT_1 0x0020
#define UPCI_AIOP_INTR_BIT_2 0x0100
#define UPCI_AIOP_INTR_BIT_3 0x0800
#define UPCI_AIOP_INTR_BITS ( \
UPCI_AIOP_INTR_BIT_0 \
| UPCI_AIOP_INTR_BIT_1 \
| UPCI_AIOP_INTR_BIT_2 \
| UPCI_AIOP_INTR_BIT_3)
/* Controller level information structure */
typedef struct
{
int CtlID;
int CtlNum;
int BusType;
WordIO_t PCIIO;
ByteIO_t MBaseIO;
ByteIO_t MReg1IO;
ByteIO_t MReg2IO;
ByteIO_t MReg3IO;
Byte_t MReg2;
Byte_t MReg3;
int NumAiop;
WordIO_t AiopIO[AIOP_CTL_SIZE];
ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
int AiopID[AIOP_CTL_SIZE];
int AiopNumChan[AIOP_CTL_SIZE];
typedef struct {
int CtlID;
int CtlNum;
int BusType;
int boardType;
int isUPCI;
WordIO_t PCIIO;
WordIO_t PCIIO2;
ByteIO_t MBaseIO;
ByteIO_t MReg1IO;
ByteIO_t MReg2IO;
ByteIO_t MReg3IO;
Byte_t MReg2;
Byte_t MReg3;
int NumAiop;
int AltChanRingIndicator;
ByteIO_t UPCIRingInd;
WordIO_t AiopIO[AIOP_CTL_SIZE];
ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
int AiopID[AIOP_CTL_SIZE];
int AiopNumChan[AIOP_CTL_SIZE];
Word_t *AiopIntrBits;
} CONTROLLER_T;
typedef CONTROLLER_T CONTROLLER_t;
/* Channel level information structure */
typedef struct
{
CONTROLLER_T *CtlP;
int AiopNum;
int ChanID;
int ChanNum;
ByteIO_t Cmd;
ByteIO_t IntChan;
ByteIO_t IntMask;
DWordIO_t IndexAddr;
WordIO_t IndexData;
WordIO_t TxRxData;
WordIO_t ChanStat;
WordIO_t TxRxCount;
ByteIO_t IntID;
Word_t TxFIFO;
Word_t TxFIFOPtrs;
Word_t RxFIFO;
Word_t RxFIFOPtrs;
Word_t TxPrioCnt;
Word_t TxPrioPtr;
Word_t TxPrioBuf;
Byte_t R[RREGDATASIZE];
Byte_t BaudDiv[4];
Byte_t TxControl[4];
Byte_t RxControl[4];
Byte_t TxEnables[4];
Byte_t TxCompare[4];
Byte_t TxReplace1[4];
Byte_t TxReplace2[4];
typedef struct {
CONTROLLER_T *CtlP;
int AiopNum;
int ChanID;
int ChanNum;
int rtsToggle;
ByteIO_t Cmd;
ByteIO_t IntChan;
ByteIO_t IntMask;
DWordIO_t IndexAddr;
WordIO_t IndexData;
WordIO_t TxRxData;
WordIO_t ChanStat;
WordIO_t TxRxCount;
ByteIO_t IntID;
Word_t TxFIFO;
Word_t TxFIFOPtrs;
Word_t RxFIFO;
Word_t RxFIFOPtrs;
Word_t TxPrioCnt;
Word_t TxPrioPtr;
Word_t TxPrioBuf;
Byte_t R[RREGDATASIZE];
Byte_t BaudDiv[4];
Byte_t TxControl[4];
Byte_t RxControl[4];
Byte_t TxEnables[4];
Byte_t TxCompare[4];
Byte_t TxReplace1[4];
Byte_t TxReplace2[4];
} CHANNEL_T;
typedef CHANNEL_T CHANNEL_t;
typedef CHANNEL_T * CHANPTR_T;
typedef CHANNEL_T *CHANPTR_T;
#define InterfaceModeRS232 0x00
#define InterfaceModeRS422 0x08
#define InterfaceModeRS485 0x10
#define InterfaceModeRS232T 0x18
/***************************************************************************
Function: sClrBreak
......@@ -391,10 +419,10 @@ Call: sClrBreak(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrBreak(ChP) \
{ \
do { \
(ChP)->TxControl[3] &= ~SETBREAK; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sClrDTR
......@@ -403,10 +431,10 @@ Call: sClrDTR(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrDTR(ChP) \
{ \
do { \
(ChP)->TxControl[3] &= ~SET_DTR; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sClrRTS
......@@ -415,10 +443,11 @@ Call: sClrRTS(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrRTS(ChP) \
{ \
do { \
if ((ChP)->rtsToggle) break; \
(ChP)->TxControl[3] &= ~SET_RTS; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sClrTxXOFF
......@@ -427,10 +456,10 @@ Call: sClrTxXOFF(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrTxXOFF(ChP) \
{ \
do { \
sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
}
} while (0)
/***************************************************************************
Function: sCtlNumToCtlPtr
......@@ -452,10 +481,22 @@ Call: sControllerEOI(CtlP)
/***************************************************************************
Function: sPCIControllerEOI
Purpose: Strobe the PCI End Of Interrupt bit.
For the UPCI boards, toggle the AIOP interrupt enable bit
(this was taken from the Windows driver).
Call: sPCIControllerEOI(CtlP)
CONTROLLER_T *CtlP; Ptr to controller structure
*/
#define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB)
#define sPCIControllerEOI(CTLP) \
do { \
if ((CTLP)->isUPCI) { \
Word_t w = sInW((CTLP)->PCIIO); \
sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
sOutW((CTLP)->PCIIO, w); \
} \
else { \
sOutW((CTLP)->PCIIO, PCI_STROB); \
} \
} while (0)
/***************************************************************************
Function: sDisAiop
......@@ -465,10 +506,10 @@ Call: sDisAiop(CltP)
int AiopNum; Number of AIOP on controller
*/
#define sDisAiop(CTLP,AIOPNUM) \
{ \
do { \
(CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
}
} while (0)
/***************************************************************************
Function: sDisCTSFlowCtl
......@@ -477,10 +518,10 @@ Call: sDisCTSFlowCtl(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisCTSFlowCtl(ChP) \
{ \
do { \
(ChP)->TxControl[2] &= ~CTSFC_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sDisIXANY
......@@ -489,10 +530,10 @@ Call: sDisIXANY(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisIXANY(ChP) \
{ \
do { \
(ChP)->R[0x0e] = 0x86; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
}
} while (0)
/***************************************************************************
Function: DisParity
......@@ -503,10 +544,23 @@ Comments: Function sSetParity() can be used in place of functions sEnParity(),
sDisParity(), sSetOddParity(), and sSetEvenParity().
*/
#define sDisParity(ChP) \
{ \
do { \
(ChP)->TxControl[2] &= ~PARITY_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sDisRTSToggle
Purpose: Disable RTS toggle
Call: sDisRTSToggle(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisRTSToggle(ChP) \
do { \
(ChP)->TxControl[2] &= ~RTSTOG_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
(ChP)->rtsToggle = 0; \
} while (0)
/***************************************************************************
Function: sDisRxFIFO
......@@ -515,10 +569,10 @@ Call: sDisRxFIFO(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisRxFIFO(ChP) \
{ \
do { \
(ChP)->R[0x32] = 0x0a; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
}
} while (0)
/***************************************************************************
Function: sDisRxStatusMode
......@@ -542,10 +596,10 @@ Call: sDisTransmit(ChP)
and transmit shift register going completely empty.
*/
#define sDisTransmit(ChP) \
{ \
do { \
(ChP)->TxControl[3] &= ~TX_ENABLE; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sDisTxSoftFlowCtl
......@@ -554,10 +608,10 @@ Call: sDisTxSoftFlowCtl(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisTxSoftFlowCtl(ChP) \
{ \
do { \
(ChP)->R[0x06] = 0x8a; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
}
} while (0)
/***************************************************************************
Function: sEnAiop
......@@ -567,10 +621,10 @@ Call: sEnAiop(CltP)
int AiopNum; Number of AIOP on controller
*/
#define sEnAiop(CTLP,AIOPNUM) \
{ \
do { \
(CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
}
} while (0)
/***************************************************************************
Function: sEnCTSFlowCtl
......@@ -579,10 +633,10 @@ Call: sEnCTSFlowCtl(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnCTSFlowCtl(ChP) \
{ \
do { \
(ChP)->TxControl[2] |= CTSFC_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sEnIXANY
......@@ -591,10 +645,10 @@ Call: sEnIXANY(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnIXANY(ChP) \
{ \
do { \
(ChP)->R[0x0e] = 0x21; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
}
} while (0)
/***************************************************************************
Function: EnParity
......@@ -608,10 +662,28 @@ Warnings: Before enabling parity odd or even parity should be chosen using
functions sSetOddParity() or sSetEvenParity().
*/
#define sEnParity(ChP) \
{ \
do { \
(ChP)->TxControl[2] |= PARITY_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sEnRTSToggle
Purpose: Enable RTS toggle
Call: sEnRTSToggle(ChP)
CHANNEL_T *ChP; Ptr to channel structure
Comments: This function will disable RTS flow control and clear the RTS
line to allow operation of RTS toggle.
*/
#define sEnRTSToggle(ChP) \
do { \
(ChP)->RxControl[2] &= ~RTSFC_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
(ChP)->TxControl[2] |= RTSTOG_EN; \
(ChP)->TxControl[3] &= ~SET_RTS; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
(ChP)->rtsToggle = 1; \
} while (0)
/***************************************************************************
Function: sEnRxFIFO
......@@ -620,10 +692,10 @@ Call: sEnRxFIFO(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnRxFIFO(ChP) \
{ \
do { \
(ChP)->R[0x32] = 0x08; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
}
} while (0)
/***************************************************************************
Function: sEnRxProcessor
......@@ -641,10 +713,10 @@ Warnings: This function must be called after valid microcode has been
microcode has been downloaded.
*/
#define sEnRxProcessor(ChP) \
{ \
do { \
(ChP)->RxControl[2] |= RXPROC_EN; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sEnRxStatusMode
......@@ -665,10 +737,10 @@ Call: sEnTransmit(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnTransmit(ChP) \
{ \
do { \
(ChP)->TxControl[3] |= TX_ENABLE; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sEnTxSoftFlowCtl
......@@ -677,10 +749,10 @@ Call: sEnTxSoftFlowCtl(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnTxSoftFlowCtl(ChP) \
{ \
do { \
(ChP)->R[0x06] = 0xc5; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
}
} while (0)
/***************************************************************************
Function: sGetAiopIntStatus
......@@ -774,6 +846,18 @@ Return: Byte_t: The channel status low byte. Can be any combination
*/
#define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
/**********************************************************************
* Get RI status of channel
* Defined as a function in rocket.c -aes
*/
#if 0
#define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
(sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
(((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
(!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
0))
#endif
/***************************************************************************
Function: sGetControllerIntStatus
Purpose: Get the controller interrupt status
......@@ -798,7 +882,10 @@ Return: unsigned char: The controller interrupt status in the lower 4
was generated from periodic. If a bit is set the
AIOP is interrupting.
*/
#define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f)
#define sPCIGetControllerIntStatus(CTLP) \
((CTLP)->isUPCI ? \
(sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
/***************************************************************************
......@@ -834,7 +921,7 @@ Return: WordIO_t: I/O address of a channel's TxRx Data register
/***************************************************************************
Function: sInitChanDefaults
Purpose: Initialize a channel structure to its default state.
Purpose: Initialize a channel structure to it's default state.
Call: sInitChanDefaults(ChP)
CHANNEL_T *ChP; Ptr to the channel structure
Comments: This function must be called once for every channel structure
......@@ -842,12 +929,12 @@ Comments: This function must be called once for every channel structure
*/
#define sInitChanDefaults(ChP) \
{ \
do { \
(ChP)->CtlP = NULLCTLPTR; \
(ChP)->AiopNum = NULLAIOP; \
(ChP)->ChanID = AIOPID_NULL; \
(ChP)->ChanNum = NULLCHAN; \
}
} while (0)
/***************************************************************************
Function: sResetAiopByNum
......@@ -857,10 +944,10 @@ Call: sResetAiopByNum(CTLP,AIOPNUM)
AIOPNUM; AIOP index
*/
#define sResetAiopByNum(CTLP,AIOPNUM) \
{ \
do { \
sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
}
} while (0)
/***************************************************************************
Function: sSendBreak
......@@ -869,10 +956,10 @@ Call: sSendBreak(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSendBreak(ChP) \
{ \
do { \
(ChP)->TxControl[3] |= SETBREAK; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetBaud
......@@ -882,11 +969,11 @@ Call: sSetBaud(ChP,Divisor)
Word_t Divisor; 16 bit baud rate divisor for channel
*/
#define sSetBaud(ChP,DIVISOR) \
{ \
do { \
(ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
(ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
}
} while (0)
/***************************************************************************
Function: sSetData7
......@@ -895,10 +982,10 @@ Call: sSetData7(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetData7(ChP) \
{ \
do { \
(ChP)->TxControl[2] &= ~DATA8BIT; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetData8
......@@ -907,10 +994,10 @@ Call: sSetData8(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetData8(ChP) \
{ \
do { \
(ChP)->TxControl[2] |= DATA8BIT; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetDTR
......@@ -919,10 +1006,10 @@ Call: sSetDTR(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetDTR(ChP) \
{ \
do { \
(ChP)->TxControl[3] |= SET_DTR; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetEvenParity
......@@ -936,10 +1023,10 @@ Warnings: This function has no effect unless parity is enabled with function
sEnParity().
*/
#define sSetEvenParity(ChP) \
{ \
do { \
(ChP)->TxControl[2] |= EVEN_PAR; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetOddParity
......@@ -953,10 +1040,10 @@ Warnings: This function has no effect unless parity is enabled with function
sEnParity().
*/
#define sSetOddParity(ChP) \
{ \
do { \
(ChP)->TxControl[2] &= ~EVEN_PAR; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetRTS
......@@ -965,10 +1052,11 @@ Call: sSetRTS(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetRTS(ChP) \
{ \
do { \
if ((ChP)->rtsToggle) break; \
(ChP)->TxControl[3] |= SET_RTS; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetRxTrigger
......@@ -990,11 +1078,11 @@ Comments: An interrupt will be generated when the trigger level is reached
*/
#define sSetRxTrigger(ChP,LEVEL) \
{ \
do { \
(ChP)->RxControl[2] &= ~TRIG_MASK; \
(ChP)->RxControl[2] |= LEVEL; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetStop1
......@@ -1003,10 +1091,10 @@ Call: sSetStop1(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetStop1(ChP) \
{ \
do { \
(ChP)->TxControl[2] &= ~STOP2; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetStop2
......@@ -1015,10 +1103,10 @@ Call: sSetStop2(ChP)
CHANNEL_T *ChP; Ptr to channel structure
*/
#define sSetStop2(ChP) \
{ \
do { \
(ChP)->TxControl[2] |= STOP2; \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
}
} while (0)
/***************************************************************************
Function: sSetTxXOFFChar
......@@ -1028,10 +1116,10 @@ Call: sSetTxXOFFChar(ChP,Ch)
Byte_t Ch; The value to set the Tx XOFF character to
*/
#define sSetTxXOFFChar(ChP,CH) \
{ \
do { \
(ChP)->R[0x07] = (CH); \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
}
} while (0)
/***************************************************************************
Function: sSetTxXONChar
......@@ -1041,10 +1129,10 @@ Call: sSetTxXONChar(ChP,Ch)
Byte_t Ch; The value to set the Tx XON character to
*/
#define sSetTxXONChar(ChP,CH) \
{ \
do { \
(ChP)->R[0x0b] = (CH); \
sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \
}
} while (0)
/***************************************************************************
Function: sStartRxProcessor
......@@ -1069,37 +1157,38 @@ Warnings: This function writes the data byte without checking to see if
*/
#define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
int sInitController( CONTROLLER_T *CtlP,
int CtlNum,
ByteIO_t MudbacIO,
ByteIO_t *AiopIOList,
int AiopIOListSize,
int IRQNum,
Byte_t Frequency,
int PeriodicOnly);
int sPCIInitController( CONTROLLER_T *CtlP,
int CtlNum,
ByteIO_t *AiopIOList,
int AiopIOListSize,
int IRQNum,
Byte_t Frequency,
int PeriodicOnly);
int sInitController(CONTROLLER_T * CtlP,
int CtlNum,
ByteIO_t MudbacIO,
ByteIO_t * AiopIOList,
int AiopIOListSize,
int IRQNum, Byte_t Frequency, int PeriodicOnly);
int sPCIInitController(CONTROLLER_T * CtlP,
int CtlNum,
ByteIO_t * AiopIOList,
int AiopIOListSize,
WordIO_t ConfigIO,
int IRQNum,
Byte_t Frequency,
int PeriodicOnly,
int altChanRingIndicator, int UPCIRingInd);
int sReadAiopID(ByteIO_t io);
int sReadAiopNumChan(WordIO_t io);
int sInitChan( CONTROLLER_T *CtlP,
CHANNEL_T *ChP,
int AiopNum,
int ChanNum);
Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
void sStopRxProcessor(CHANNEL_T *ChP);
void sStopSWInFlowCtl(CHANNEL_T *ChP);
void sFlushRxFIFO(CHANNEL_T *ChP);
void sFlushTxFIFO(CHANNEL_T *ChP);
int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
int sInitChan(CONTROLLER_T * CtlP,
CHANNEL_T * ChP, int AiopNum, int ChanNum);
Byte_t sGetRxErrStatus(CHANNEL_T * ChP);
void sStopRxProcessor(CHANNEL_T * ChP);
void sStopSWInFlowCtl(CHANNEL_T * ChP);
void sFlushRxFIFO(CHANNEL_T * ChP);
void sFlushTxFIFO(CHANNEL_T * ChP);
int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
extern Byte_t R[RDATASIZE];
extern CONTROLLER_T sController[CTL_SIZE];
......@@ -1108,7 +1197,6 @@ extern Byte_t sBitMapClrTbl[8];
extern Byte_t sBitMapSetTbl[8];
extern int sClockPrescale;
/*
* Begin Linux specific definitions for the Rocketport driver
*
......@@ -1116,34 +1204,45 @@ extern int sClockPrescale;
*/
struct r_port {
int magic;
int line;
int flags;
int count;
int blocked_open;
struct tty_struct *tty;
int board:2;
int aiop:2;
int chan:3;
int magic;
int line;
int flags;
int count;
int blocked_open;
struct tty_struct *tty;
unsigned int board:3;
unsigned int aiop:2;
unsigned int chan:3;
CONTROLLER_t *ctlp;
CHANNEL_t channel;
int closing_wait;
int close_delay;
int intmask;
int xmit_fifo_room; /* room in xmit fifo */
unsigned char *xmit_buf;
int xmit_head;
int xmit_tail;
int xmit_cnt;
int cd_status;
int ignore_status_mask;
int read_status_mask;
int cps;
struct termios normal_termios;
wait_queue_head_t open_wait;
wait_queue_head_t close_wait;
CHANNEL_t channel;
int closing_wait;
int close_delay;
int intmask;
int xmit_fifo_room; /* room in xmit fifo */
unsigned char *xmit_buf;
int xmit_head;
int xmit_tail;
int xmit_cnt;
int session;
int pgrp;
int cd_status;
int ignore_status_mask;
int read_status_mask;
int cps;
struct termios normal_termios;
struct termios callout_termios;
#ifdef DECLARE_WAITQUEUE
wait_queue_head_t open_wait;
wait_queue_head_t close_wait;
#else
struct wait_queue *open_wait;
struct wait_queue *close_wait;
#endif
spinlock_t slock;
struct semaphore write_sem;
};
#define RPORT_MAGIC 0x525001
#define NUM_BOARDS 8
......@@ -1158,16 +1257,14 @@ struct r_port {
#define WAKEUP_CHARS 256
/* Internal flags used only by the rocketport driver */
#define ROCKET_INITIALIZED 0x80000000 /* Port is active */
#define ROCKET_CLOSING 0x40000000 /* Serial port is closing */
#define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */
#define ROCKET_CALLOUT_ACTIVE 0x10000000 /* Callout port is active */
#define ROCKET_INITIALIZED 0x80000000 /* Port is active */
#define ROCKET_CLOSING 0x40000000 /* Serial port is closing */
#define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */
#define ROCKET_CALLOUT_ACTIVE 0x10000000 /* Callout port is active */
/*
* tty subtypes
*
*/
/* tty subtypes */
#define SERIAL_TYPE_NORMAL 1
#define SERIAL_TYPE_CALLOUT 2
/*
* Assigned major numbers for the Comtrol Rocketport
......@@ -1175,9 +1272,6 @@ struct r_port {
#define TTY_ROCKET_MAJOR 46
#define CUA_ROCKET_MAJOR 47
/*
* Utility function.
*/
#ifndef MIN
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#endif
......@@ -1188,27 +1282,65 @@ struct r_port {
#undef PCI_DEVICE_ID_RP8INTF
#undef PCI_DEVICE_ID_RP16INTF
#undef PCI_DEVICE_ID_RP32INTF
#undef PCI_DEVICE_ID_URP8OCTA
#undef PCI_DEVICE_ID_URP8INTF
#undef PCI_DEVICE_ID_URP16INTF
#undef PCI_DEVICE_ID_CRP16INTF
#undef PCI_DEVICE_ID_URP32INTF
#endif
/* Comtrol PCI Vendor ID */
#define PCI_VENDOR_ID_RP 0x11fe
#define PCI_DEVICE_ID_RP32INTF 0x0001
#define PCI_DEVICE_ID_RP8INTF 0x0002
#define PCI_DEVICE_ID_RP16INTF 0x0003
#define PCI_DEVICE_ID_RP8OCTA 0x0005
#ifndef PCI_DEVICE_ID_RP4QUAD
#define PCI_DEVICE_ID_RP4QUAD 0x0004
#endif
#ifndef PCI_DEVICE_ID_RP8J
#define PCI_DEVICE_ID_RP8J 0x0006
#endif
#ifndef PCI_DEVICE_ID_RPP4
#define PCI_DEVICE_ID_RPP4 0x000A
#endif
#ifndef PCI_DEVICE_ID_RPP8
#define PCI_DEVICE_ID_RPP8 0x000B
#endif
#ifndef PCI_DEVICE_ID_RP8M
#define PCI_DEVICE_ID_RP8M 0x000C
#endif
/* Comtrol Device ID's */
#define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */
#define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */
#define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */
#define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */
#define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */
#define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */
#define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */
#define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
#define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */
#define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */
#define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */
#define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */
#define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */
#define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */
#define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */
/* Universal PCI boards */
#define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */
#define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */
#define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */
#define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */
#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */
/* Compact PCI device */
#define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */
/* Taking care of some kernel incompatibilities... */
#if LINUX_VERSION_CODE > VERSION_CODE(2,5,68)
#define TTY_GET_LINE(t) t->index
#define TTY_DRIVER_MINOR_START(t) t->driver->minor_start
#define TTY_DRIVER_SUBTYPE(t) t->driver->subtype
#define TTY_DRIVER_NAME(t) t->driver->name
#define TTY_DRIVER_NAME_BASE(t) t->driver->name_base
#define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver->flush_buffer
#define TTY_DRIVER_FLUSH_BUFFER(t) t->driver->flush_buffer(t)
#else
#define TTY_GET_LINE(t) minor(t->device) - TTY_DRIVER_MINOR_START(t)
#define TTY_DRIVER_MINOR_START(t) t->driver.minor_start
#define TTY_DRIVER_SUBTYPE(t) t->driver.subtype
#define TTY_DRIVER_NAME(t) t->driver.name
#define TTY_DRIVER_NAME_BASE(t) t->driver.name_base
#define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver.flush_buffer
#define TTY_DRIVER_FLUSH_BUFFER(t) t->driver.flush_buffer(t)
#endif
drivers/pci/pci.ids
View file @ 134d4d1c
......@@ -3745,19 +3745,26 @@
11fc Silicon Magic
11fd High Street Consultants
11fe Comtrol Corporation
0001 RocketPort 8 Oct
0002 RocketPort 8 Intf
0003 RocketPort 16 Intf
0004 RocketPort 32 Intf
0005 RocketPort Octacable
0006 RocketPort 8J
0007 RocketPort 4-port
0008 RocketPort 8-port
0009 RocketPort 16-port
000a RocketPort Plus Quadcable
000b RocketPort Plus Octacable
000c RocketPort 8-port Modem
8015 RocketPort 4-port UART 16954
0001 Rocketport 32 port w/external I/F
0002 Rocketport 8 port w/external I/F
0003 Rocketport 16 port w/external I/F
0004 Rocketport 4 port w/quad cable
0005 Rocketport 8 port w/octa cable
0006 Rocketport 8 port w/RJ11 connectors
0007 Rocketport 4 port w/RJ11 connectors
000a Rocketport Plus 4 port
000b Rocketport Plus 8 port
000c RocketModem 6 port
000d RocketModem 4-port
000e Rocketport Plus 2 port RS232
000f Rocketport Plus 2 port RS422
0801 Rocketport UPCI 32 port w/external I/F
0802 Rocketport UPCI 8 port w/external I/F
0803 Rocketport UPCI 16 port w/external I/F
0805 Rocketport UPCI 8 port w/octa cable
080C RocketModem III 8 port
080D RocketModem III 4 port
0903 Rocketport Compact PCI 16 port w/external I/F
11ff Scion Corporation
1200 CSS Corporation
1201 Vista Controls Corp
......
include/linux/pci_ids.h
View file @ 134d4d1c
......@@ -1398,9 +1398,20 @@
#define PCI_DEVICE_ID_RP4QUAD 0x0004
#define PCI_DEVICE_ID_RP8OCTA 0x0005
#define PCI_DEVICE_ID_RP8J 0x0006
#define PCI_DEVICE_ID_RP4J 0x0007
#define PCI_DEVICE_ID_RPP4 0x000A
#define PCI_DEVICE_ID_RPP8 0x000B
#define PCI_DEVICE_ID_RP8M 0x000C
#define PCI_DEVICE_ID_RP4M 0x000D
#define PCI_DEVICE_ID_RP2_232 0x000E
#define PCI_DEVICE_ID_RP2_422 0x000F
#define PCI_DEVICE_ID_URP32INTF 0x0801
#define PCI_DEVICE_ID_URP8INTF 0x0802
#define PCI_DEVICE_ID_URP16INTF 0x0803
#define PCI_DEVICE_ID_URP8OCTA 0x0805
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C
#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D
#define PCI_DEVICE_ID_CRP16INTF 0x0903
#define PCI_VENDOR_ID_CYCLADES 0x120e
#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100
......
include/linux/rocket.h deleted 100644 → 0
View file @ ebb11c7e
/*
* This file contains the exported interface of the rocket driver to
* its configuration program.
*/
struct rocket_config {
int line;
int flags;
int closing_wait;
int close_delay;
int port;
int reserved[32];
};
struct rocket_ports {
int tty_major;
int callout_major;
int port_bitmap[4];
int reserved[32];
};
/*
* Rocketport flags
*/
#define ROCKET_CALLOUT_NOHUP 0x00000001
#define ROCKET_FORCE_CD 0x00000002
#define ROCKET_HUP_NOTIFY 0x00000004
#define ROCKET_SPLIT_TERMIOS 0x00000008
#define ROCKET_SPD_MASK 0x00000070
#define ROCKET_SPD_HI 0x00000010 /* Use 56000 instead of 38400 bps */
#define ROCKET_SPD_VHI 0x00000020 /* Use 115200 instead of 38400 bps*/
#define ROCKET_SPD_SHI 0x00000030 /* Use 230400 instead of 38400 bps*/
#define ROCKET_SPD_WARP 0x00000040 /* Use 460800 instead of 38400 bps*/
#define ROCKET_SAK 0x00000080
#define ROCKET_SESSION_LOCKOUT 0x00000100
#define ROCKET_PGRP_LOCKOUT 0x00000200
#define ROCKET_FLAGS 0x000003FF
#define ROCKET_USR_MASK 0x0071 /* Legal flags that non-privileged
* users can set or reset */
/*
* For closing_wait and closing_wait2
*/
#define ROCKET_CLOSING_WAIT_NONE 65535
#define ROCKET_CLOSING_WAIT_INF 0
/*
* Rocketport ioctls -- "RP"
*/
#define RCKP_GET_STRUCT 0x00525001
#define RCKP_GET_CONFIG 0x00525002
#define RCKP_SET_CONFIG 0x00525003
#define RCKP_GET_PORTS 0x00525004
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