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Commit 15e824dd authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-soc-for-v3.16' of... 

Merge tag 'renesas-soc-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Renesas ARM Based SoC Updates for v3.16" from Simon Horman:

SH Mobile shared SoC code
* Add shared shmobile_init_delay()

r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCs (R-Car Gen2 shared code)
* Cache Mode Monitor Register Value

r8a7791 (R-Car M2) SoC
Check r8a7791 MD21 at SMP boot

r8a7790 (R-Car H2) SoC
* Make use of r8a7790_add_standard_devices()
* Update r8a7791 CPU freq to 1500MHz

r8a7778 (R-Car M1) SoC
* Move "select RENESAS_INTC_IRQPIN" under SoC

emev2 (Emma Mobale EV2) SoC
*  Remove legacy EMEV2 SoC support

* tag 'renesas-soc-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7778/bockw: Move "select RENESAS_INTC_IRQPIN" under SoC
  ARM: shmobile: Check r8a7791 MD21 at SMP boot
  ARM: shmobile: rcar-gen2: Cache Mode Monitor Register Value
  ARM: shmobile: Make use of r8a7790_add_standard_devices()
  ARM: shmobile: Remove EMEV2 header file
  ARM: shmobile: Remove legacy EMEV2 SoC support
  ARM: shmobile: Add shared shmobile_init_delay()
  ARM: shmobile: Update r8a7791 CPU freq to 1500MHz in C
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 89ca3b88 e35db38d
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Showing with 66 additions and 277 deletions
arch/arm/boot/dts/Makefile
View file @ 15e824dd
......@@ -297,8 +297,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
r7s72100-genmai-reference.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
......
arch/arm/mach-shmobile/Kconfig
View file @ 15e824dd
......@@ -108,6 +108,7 @@ config ARCH_R8A7778
select SH_CLK_CPG
select ARM_GIC
select SYS_SUPPORTS_SH_TMU
select RENESAS_INTC_IRQPIN
config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
......@@ -140,16 +141,6 @@ config ARCH_R8A7791
select SYS_SUPPORTS_SH_CMT
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
config ARCH_EMEV2
bool "Emma Mobile EV2"
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select CPU_V7
select MIGHT_HAVE_PCI
select USE_OF
select AUTO_ZRELADDR
select SYS_SUPPORTS_EM_STI
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select ARCH_WANT_OPTIONAL_GPIOLIB
......@@ -216,7 +207,6 @@ config MACH_BOCKW
depends on ARCH_R8A7778
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select RENESAS_INTC_IRQPIN
select SND_SOC_AK4554 if SND_SIMPLE_CARD
select SND_SOC_AK4642 if SND_SIMPLE_CARD
select USE_OF
......@@ -225,7 +215,6 @@ config MACH_BOCKW_REFERENCE
bool "BOCK-W - Reference Device Tree Implementation"
depends on ARCH_R8A7778
select ARCH_REQUIRE_GPIOLIB
select RENESAS_INTC_IRQPIN
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select USE_OF
---help---
......
arch/arm/mach-shmobile/Makefile
View file @ 15e824dd
......@@ -31,7 +31,6 @@ obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o
obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o
endif
......
arch/arm/mach-shmobile/clock-emev2.c deleted 100644 → 0
View file @ 89ca3b88
/*
* Emma Mobile EV2 clock framework support
*
* Copyright (C) 2012 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/common.h>
#define EMEV2_SMU_BASE 0xe0110000
/* EMEV2 SMU registers */
#define USIAU0_RSTCTRL 0x094
#define USIBU1_RSTCTRL 0x0ac
#define USIBU2_RSTCTRL 0x0b0
#define USIBU3_RSTCTRL 0x0b4
#define STI_RSTCTRL 0x124
#define USIAU0GCLKCTRL 0x4a0
#define USIBU1GCLKCTRL 0x4b8
#define USIBU2GCLKCTRL 0x4bc
#define USIBU3GCLKCTRL 0x04c0
#define STIGCLKCTRL 0x528
#define USIAU0SCLKDIV 0x61c
#define USIB2SCLKDIV 0x65c
#define USIB3SCLKDIV 0x660
#define STI_CLKSEL 0x688
/* not pretty, but hey */
static void __iomem *smu_base;
static void emev2_smu_write(unsigned long value, int offs)
{
BUG_ON(!smu_base || (offs >= PAGE_SIZE));
iowrite32(value, smu_base + offs);
}
static struct clk_mapping smu_mapping = {
.phys = EMEV2_SMU_BASE,
.len = PAGE_SIZE,
};
/* Fixed 32 KHz root clock from C32K pin */
static struct clk c32k_clk = {
.rate = 32768,
.mapping = &smu_mapping,
};
/* PLL3 multiplies C32K with 7000 */
static unsigned long pll3_recalc(struct clk *clk)
{
return clk->parent->rate * 7000;
}
static struct sh_clk_ops pll3_clk_ops = {
.recalc = pll3_recalc,
};
static struct clk pll3_clk = {
.ops = &pll3_clk_ops,
.parent = &c32k_clk,
};
static struct clk *main_clks[] = {
&c32k_clk,
&pll3_clk,
};
enum { SCLKDIV_USIAU0, SCLKDIV_USIBU2, SCLKDIV_USIBU1, SCLKDIV_USIBU3,
SCLKDIV_NR };
#define SCLKDIV(_reg, _shift) \
{ \
.parent = &pll3_clk, \
.enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \
.enable_bit = _shift, \
}
static struct clk sclkdiv_clks[SCLKDIV_NR] = {
[SCLKDIV_USIAU0] = SCLKDIV(USIAU0SCLKDIV, 0),
[SCLKDIV_USIBU2] = SCLKDIV(USIB2SCLKDIV, 16),
[SCLKDIV_USIBU1] = SCLKDIV(USIB2SCLKDIV, 0),
[SCLKDIV_USIBU3] = SCLKDIV(USIB3SCLKDIV, 0),
};
enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK,
GCLK_STI_SCLK,
GCLK_NR };
#define GCLK_SCLK(_parent, _reg) \
{ \
.parent = _parent, \
.enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \
.enable_bit = 1, /* SCLK_GCC */ \
}
static struct clk gclk_clks[GCLK_NR] = {
[GCLK_USIAU0_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIAU0],
USIAU0GCLKCTRL),
[GCLK_USIBU1_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU1],
USIBU1GCLKCTRL),
[GCLK_USIBU2_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU2],
USIBU2GCLKCTRL),
[GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3],
USIBU3GCLKCTRL),
[GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL),
};
static int emev2_gclk_enable(struct clk *clk)
{
iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
clk->mapped_reg);
return 0;
}
static void emev2_gclk_disable(struct clk *clk)
{
iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
clk->mapped_reg);
}
static struct sh_clk_ops emev2_gclk_clk_ops = {
.enable = emev2_gclk_enable,
.disable = emev2_gclk_disable,
.recalc = followparent_recalc,
};
static int __init emev2_gclk_register(struct clk *clks, int nr)
{
struct clk *clkp;
int ret = 0;
int k;
for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k;
clkp->ops = &emev2_gclk_clk_ops;
ret |= clk_register(clkp);
}
return ret;
}
static unsigned long emev2_sclkdiv_recalc(struct clk *clk)
{
unsigned int sclk_div;
sclk_div = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0xff;
return clk->parent->rate / (sclk_div + 1);
}
static struct sh_clk_ops emev2_sclkdiv_clk_ops = {
.recalc = emev2_sclkdiv_recalc,
};
static int __init emev2_sclkdiv_register(struct clk *clks, int nr)
{
struct clk *clkp;
int ret = 0;
int k;
for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k;
clkp->ops = &emev2_sclkdiv_clk_ops;
ret |= clk_register(clkp);
}
return ret;
}
static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("serial8250-em.0", &gclk_clks[GCLK_USIAU0_SCLK]),
CLKDEV_DEV_ID("e1020000.uart", &gclk_clks[GCLK_USIAU0_SCLK]),
CLKDEV_DEV_ID("serial8250-em.1", &gclk_clks[GCLK_USIBU1_SCLK]),
CLKDEV_DEV_ID("e1030000.uart", &gclk_clks[GCLK_USIBU1_SCLK]),
CLKDEV_DEV_ID("serial8250-em.2", &gclk_clks[GCLK_USIBU2_SCLK]),
CLKDEV_DEV_ID("e1040000.uart", &gclk_clks[GCLK_USIBU2_SCLK]),
CLKDEV_DEV_ID("serial8250-em.3", &gclk_clks[GCLK_USIBU3_SCLK]),
CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]),
CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]),
CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]),
};
void __init emev2_clock_init(void)
{
int k, ret = 0;
smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
BUG_ON(!smu_base);
/* setup STI timer to run on 32.768 kHz and deassert reset */
emev2_smu_write(0, STI_CLKSEL);
emev2_smu_write(1, STI_RSTCTRL);
/* deassert reset for UART0->UART3 */
emev2_smu_write(2, USIAU0_RSTCTRL);
emev2_smu_write(2, USIBU1_RSTCTRL);
emev2_smu_write(2, USIBU2_RSTCTRL);
emev2_smu_write(2, USIBU3_RSTCTRL);
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = emev2_sclkdiv_register(sclkdiv_clks, SCLKDIV_NR);
if (!ret)
ret = emev2_gclk_register(gclk_clks, GCLK_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
shmobile_clk_init();
else
panic("failed to setup emev2 clocks\n");
}
arch/arm/mach-shmobile/include/mach/common.h
View file @ 15e824dd
......@@ -4,6 +4,7 @@
extern void shmobile_earlytimer_init(void);
extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
unsigned int mult, unsigned int div);
extern void shmobile_init_delay(void);
struct twd_local_timer;
extern void shmobile_setup_console(void);
extern void shmobile_boot_vector(void);
......
arch/arm/mach-shmobile/include/mach/emev2.h deleted 100644 → 0
View file @ 89ca3b88
#ifndef __ASM_EMEV2_H__
#define __ASM_EMEV2_H__
extern void emev2_map_io(void);
extern void emev2_init_delay(void);
extern void emev2_clock_init(void);
extern struct smp_operations emev2_smp_ops;
#endif /* __ASM_EMEV2_H__ */
arch/arm/mach-shmobile/setup-emev2.c
View file @ 15e824dd
......@@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/of_platform.h>
#include <mach/common.h>
#include <mach/emev2.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -38,23 +37,19 @@ static struct map_desc emev2_io_desc[] __initdata = {
#endif
};
void __init emev2_map_io(void)
static void __init emev2_map_io(void)
{
iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
}
void __init emev2_init_delay(void)
static void __init emev2_init_delay(void)
{
shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
}
static void __init emev2_add_standard_devices_dt(void)
{
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#else
emev2_clock_init();
#endif
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
......@@ -63,6 +58,8 @@ static const char *emev2_boards_compat_dt[] __initconst = {
NULL,
};
extern struct smp_operations emev2_smp_ops;
DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
.smp = smp_ops(emev2_smp_ops),
.map_io = emev2_map_io,
......
arch/arm/mach-shmobile/setup-r8a7790.c
View file @ 15e824dd
......@@ -185,12 +185,6 @@ void __init r8a7790_pinmux_init(void)
r8a7790_register_gpio(3);
r8a7790_register_gpio(4);
r8a7790_register_gpio(5);
r8a7790_register_i2c(0);
r8a7790_register_i2c(1);
r8a7790_register_i2c(2);
r8a7790_register_i2c(3);
r8a7790_register_audio_dmac(0);
r8a7790_register_audio_dmac(1);
}
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
......@@ -308,6 +302,12 @@ void __init r8a7790_add_standard_devices(void)
r8a7790_add_dt_devices();
r8a7790_register_irqc(0);
r8a7790_register_thermal();
r8a7790_register_i2c(0);
r8a7790_register_i2c(1);
r8a7790_register_i2c(2);
r8a7790_register_i2c(3);
r8a7790_register_audio_dmac(0);
r8a7790_register_audio_dmac(1);
}
void __init r8a7790_init_early(void)
......
arch/arm/mach-shmobile/setup-r8a7791.c
View file @ 15e824dd
......@@ -213,7 +213,7 @@ void __init r8a7791_add_standard_devices(void)
void __init r8a7791_init_early(void)
{
#ifndef CONFIG_ARM_ARCH_TIMER
shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
#endif
}
......
arch/arm/mach-shmobile/setup-rcar-gen2.c
View file @ 15e824dd
......@@ -30,12 +30,16 @@
u32 rcar_gen2_read_mode_pins(void)
{
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
u32 mode;
static u32 mode;
static bool mode_valid;
if (!mode_valid) {
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
BUG_ON(!modemr);
mode = ioread32(modemr);
iounmap(modemr);
mode_valid = true;
}
return mode;
}
......
arch/arm/mach-shmobile/smp-emev2.c
View file @ 15e824dd
......@@ -24,7 +24,6 @@
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/common.h>
#include <mach/emev2.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
......
arch/arm/mach-shmobile/smp-r8a7791.c
View file @ 15e824dd
......@@ -20,6 +20,7 @@
#include <asm/smp_plat.h>
#include <mach/common.h>
#include <mach/r8a7791.h>
#include <mach/rcar-gen2.h>
#define RST 0xe6160000
#define CA15BAR 0x0020
......@@ -51,9 +52,21 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
iounmap(p);
}
static int r8a7791_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
/* Error out when hardware debug mode is enabled */
if (rcar_gen2_read_mode_pins() & BIT(21)) {
pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
return -ENOTSUPP;
}
return shmobile_smp_apmu_boot_secondary(cpu, idle);
}
struct smp_operations r8a7791_smp_ops __initdata = {
.smp_prepare_cpus = r8a7791_smp_prepare_cpus,
.smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
.smp_boot_secondary = r8a7791_smp_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_disable = shmobile_smp_cpu_disable,
.cpu_die = shmobile_smp_apmu_cpu_die,
......
arch/arm/mach-shmobile/timer.c
View file @ 15e824dd
......@@ -21,6 +21,7 @@
#include <linux/platform_device.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/of_address.h>
void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
unsigned int mult, unsigned int div)
......@@ -39,6 +40,33 @@ void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
preset_lpj = max_cpu_core_mhz * value;
}
void __init shmobile_init_delay(void)
{
struct device_node *np, *parent;
u32 max_freq, freq;
max_freq = 0;
parent = of_find_node_by_path("/cpus");
if (parent) {
for_each_child_of_node(parent, np) {
if (!of_property_read_u32(np, "clock-frequency", &freq))
max_freq = max(max_freq, freq);
}
of_node_put(parent);
}
if (max_freq) {
if (of_find_compatible_node(NULL, NULL, "arm,cortex-a8"))
shmobile_setup_delay(max_freq, 1, 3);
else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
shmobile_setup_delay(max_freq, 1, 3);
else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a15"))
if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
shmobile_setup_delay(max_freq, 2, 4);
}
}
static void __init shmobile_late_time_init(void)
{
/*
......
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