[ARM] Manual merge with Linus.

Documentation/arm/Porting

+Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/004064.html
+
+Initial definitions
+-------------------
+
+The following symbol definitions rely on you knowing the translation that
+__virt_to_phys() does for your machine.  This macro converts the passed
+virtual address to a physical address.  Normally, it is simply:
+
+		phys = virt - PAGE_OFFSET + PHYS_OFFSET
+
+
+Decompressor Symbols
+--------------------
+
+ZTEXTADDR
+	Start address of decompressor.  There's no point in talking about
+	virtual or physical addresses here, since the MMU will be off at
+	the time when you call the decompressor code.  You normally call
+	the kernel at this address to start it booting.  This doesn't have
+	to be located in RAM, it can be in flash or other read-only or
+	read-write addressable medium.
+
+ZBSSADDR
+	Start address of zero-initialised work area for the decompressor.
+	This must be pointing at RAM.  The decompressor will zero initialise
+	this for you.  Again, the MMU will be off.
+
+ZRELADDR
+	This is the address where the decompressed kernel will be written,
+	and eventually executed.  The following constraint must be valid:
+
+		__virt_to_phys(TEXTADDR) == ZRELADDR
+
+	The initial part of the kernel is carefully coded to be position
+	independent.
+
+INITRD_PHYS
+	Physical address to place the initial RAM disk.  Only relevant if
+	you are using the bootpImage stuff (which only works on the old
+	struct param_struct).
+
+INITRD_VIRT
+	Virtual address of the initial RAM disk.  The following  constraint
+	must be valid:
+
+		__virt_to_phys(INITRD_VIRT) == INITRD_PHYS
+
+PARAMS_PHYS
+	Physical address of the struct param_struct or tag list, giving the
+	kernel various parameters about its execution environment.
+
+
+Kernel Symbols
+--------------
+
+PHYS_OFFSET
+	Physical start address of the first bank of RAM.
+
+PAGE_OFFSET
+	Virtual start address of the first bank of RAM.  During the kernel
+	boot phase, virtual address PAGE_OFFSET will be mapped to physical
+	address PHYS_OFFSET, along with any other mappings you supply.
+	This should be the same value as TASK_SIZE.
+
+TASK_SIZE
+	The maximum size of a user process in bytes.  Since user space
+	always starts at zero, this is the maximum address that a user
+	process can access+1.  The user space stack grows down from this
+	address.
+
+	Any virtual address below TASK_SIZE is deemed to be user process
+	area, and therefore managed dynamically on a process by process
+	basis by the kernel.  I'll call this the user segment.
+
+	Anything above TASK_SIZE is common to all processes.  I'll call
+	this the kernel segment.
+
+	(In other words, you can't put IO mappings below TASK_SIZE, and
+	hence PAGE_OFFSET).
+
+TEXTADDR
+	Virtual start address of kernel, normally PAGE_OFFSET + 0x8000.
+	This is where the kernel image ends up.  With the latest kernels,
+	it must be located at 32768 bytes into a 128MB region.  Previous
+	kernels placed a restriction of 256MB here.
+
+DATAADDR
+	Virtual address for the kernel data segment.  Must not be defined
+	when using the decompressor.
+
+VMALLOC_START
+VMALLOC_END
+	Virtual addresses bounding the vmalloc() area.  There must not be
+	any static mappings in this area; vmalloc will overwrite them.
+	The addresses must also be in the kernel segment (see above).
+	Normally, the vmalloc() area starts VMALLOC_OFFSET bytes above the
+	last virtual RAM address (found using variable high_memory).
+
+VMALLOC_OFFSET
+	Offset normally incorporated into VMALLOC_START to provide a hole
+	between virtual RAM and the vmalloc area.  We do this to allow
+	out of bounds memory accesses (eg, something writing off the end
+	of the mapped memory map) to be caught.  Normally set to 8MB.
+
+Architecture Specific Macros
+----------------------------
+
+BOOT_MEM(pram,pio,vio)
+	`pram' specifies the physical start address of RAM.  Must always
+	be present, and should be the same as PHYS_OFFSET.
+
+	`pio' is the physical address of an 8MB region containing IO for
+	use with the debugging macros in arch/arm/kernel/debug-armv.S.
+
+	`vio' is the virtual address of the 8MB debugging region.
+
+	It is expected that the debugging region will be re-initialised
+	by the architecture specific code later in the code (via the
+	MAPIO function).
+
+BOOT_PARAMS
+	Same as, and see PARAMS_PHYS.
+
+FIXUP(func)
+	Machine specific fixups, run before memory subsystems have been
+	initialised.
+
+MAPIO(func)
+	Machine specific function to map IO areas (including the debug
+	region above).
+
+INITIRQ(func)
+	Machine specific function to initialise interrupts.
+

arch/arm/Kconfig

@@ -175,7 +175,7 @@ source "arch/arm/mach-epxa10db/Kconfig"
 
 source "arch/arm/mach-footbridge/Kconfig"
 
-source "arch/arm/mach-iop310/Kconfig"
+source "arch/arm/mach-iop3xx/Kconfig"
 
 source "arch/arm/mach-pxa/Kconfig"
 

arch/arm/Makefile

@@ -105,7 +105,7 @@ textaddr-$(CONFIG_ARCH_CLPS711X)   := 0xc0028000
  machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
 textaddr-$(CONFIG_ARCH_FORTUNET)   := 0xc0008000
  machine-$(CONFIG_ARCH_ANAKIN)	   := anakin
- machine-$(CONFIG_ARCH_IOP310)	   := iop310
+ machine-$(CONFIG_ARCH_IOP310)	   := iop3xx
  machine-$(CONFIG_ARCH_ADIFCC)	   := adifcc
 
 MACHINE  := $(machine-y)

arch/arm/common/sa1111.c

@@ -60,6 +60,7 @@ static struct sa1111_dev usb_dev = {
 	},
 	.skpcr_mask	= SKPCR_UCLKEN,
 	.devid		= SA1111_DEVID_USB,
+	.dma_mask	= 0xffffffffLL,
 	.irq = {
 		IRQ_USBPWR,
 		IRQ_HCIM,
@@ -494,6 +495,7 @@ sa1111_init_one_child(struct sa1111 *sachip, struct sa1111_dev *sadev, unsigned
 
 	sadev->dev.parent = sachip->dev;
 	sadev->dev.bus    = &sa1111_bus_type;
+	sadev->dev.dma_mask = &sadev->dma_mask;
 	sadev->res.start  = sachip->res.start + offset;
 	sadev->res.end    = sadev->res.start + 511;
 	sadev->res.name   = sadev->dev.name;

arch/arm/kernel/Makefile

@@ -27,10 +27,8 @@ ifneq ($(MACHINE),ebsa110)
   obj-y		+= io.o
 endif
 
-ifeq ($(CONFIG_CPU_32),y)
 head-y			:= head.o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
-endif
 
 extra-y := $(head-y) init_task.o
 

arch/arm/kernel/armksyms.c

@@ -95,11 +95,6 @@ EXPORT_SYMBOL_ALIAS(kern_fp_enter,fp_enter);
 EXPORT_SYMBOL_ALIAS(fp_printk,printk);
 EXPORT_SYMBOL_ALIAS(fp_send_sig,send_sig);
 
-#ifdef CONFIG_CPU_26
-EXPORT_SYMBOL(fpundefinstr);
-EXPORT_SYMBOL(ret_from_exception);
-#endif
-
 #ifdef CONFIG_VT
 EXPORT_SYMBOL(kd_mksound);
 #endif
@@ -111,10 +106,8 @@ EXPORT_SYMBOL_NOVERS(__backtrace);
 EXPORT_SYMBOL(dump_thread);
 EXPORT_SYMBOL(dump_fpu);
 EXPORT_SYMBOL(udelay);
-#ifdef CONFIG_CPU_32
 EXPORT_SYMBOL(__ioremap);
 EXPORT_SYMBOL(__iounmap);
-#endif
 EXPORT_SYMBOL(kernel_thread);
 EXPORT_SYMBOL(system_rev);
 EXPORT_SYMBOL(system_serial_low);
@@ -196,7 +189,6 @@ EXPORT_SYMBOL_NOVERS(memscan);
 EXPORT_SYMBOL_NOVERS(__memzero);
 
 	/* user mem (segment) */
-#if defined(CONFIG_CPU_32)
 EXPORT_SYMBOL(__arch_copy_from_user);
 EXPORT_SYMBOL(__arch_copy_to_user);
 EXPORT_SYMBOL(__arch_clear_user);
@@ -207,11 +199,6 @@ EXPORT_SYMBOL(consistent_alloc);
 EXPORT_SYMBOL(consistent_free);
 EXPORT_SYMBOL(consistent_sync);
 
-#elif defined(CONFIG_CPU_26)
-EXPORT_SYMBOL(uaccess_kernel);
-EXPORT_SYMBOL(uaccess_user);
-#endif
-
 EXPORT_SYMBOL_NOVERS(__get_user_1);
 EXPORT_SYMBOL_NOVERS(__get_user_2);
 EXPORT_SYMBOL_NOVERS(__get_user_4);

arch/arm/kernel/asm-offsets.c

@@ -21,10 +21,7 @@
 /*
  * Make sure that the compiler and target are compatible.
  */
-#if defined(__APCS_32__) && defined(CONFIG_CPU_26)
-#error Sorry, your compiler targets APCS-32 but this kernel requires APCS-26
-#endif
-#if defined(__APCS_26__) && defined(CONFIG_CPU_32)
+#if defined(__APCS_26__)
 #error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
 #endif
 #if __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 95)
@@ -52,7 +49,6 @@ int main(void)
   BLANK();
   DEFINE(VM_EXEC,	       	VM_EXEC);
   BLANK();
-#ifdef CONFIG_CPU_32
   DEFINE(HPTE_TYPE_SMALL,      	PTE_TYPE_SMALL);
   DEFINE(HPTE_AP_READ,		PTE_AP_READ);
   DEFINE(HPTE_AP_WRITE,		PTE_AP_WRITE);
@@ -65,15 +61,7 @@ int main(void)
   DEFINE(LPTE_WRITE,		L_PTE_WRITE);
   DEFINE(LPTE_EXEC,		L_PTE_EXEC);
   DEFINE(LPTE_DIRTY,		L_PTE_DIRTY);
-#endif
   BLANK();
-#ifdef CONFIG_CPU_26
-  DEFINE(PAGE_PRESENT,		_PAGE_PRESENT);
-  DEFINE(PAGE_READONLY,		_PAGE_READONLY);
-  DEFINE(PAGE_NOT_USER,		_PAGE_NOT_USER);
-  DEFINE(PAGE_OLD,		_PAGE_OLD);
-  DEFINE(PAGE_CLEAN,		_PAGE_CLEAN);
-#endif
   BLANK();
   DEFINE(PAGE_SZ,	       	PAGE_SIZE);
   BLANK();

arch/arm/kernel/ecard.c

@@ -220,7 +220,6 @@ static void ecard_do_request(struct ecard_request *req)
 	}
 }
 
-#ifdef CONFIG_CPU_32
 #include <linux/completion.h>
 
 static pid_t ecard_pid;
@@ -341,13 +340,6 @@ ecard_call(struct ecard_request *req)
 	 */
 	wait_for_completion(&ecard_completion);
 }
-#else
-/*
- * On 26-bit processors, we don't need the kcardd thread to access the
- * expansion card loaders.  We do it directly.
- */
-#define ecard_call(req)	ecard_do_request(req)
-#endif
 
 /* ======================= Mid-level card control ===================== */
 
@@ -1026,9 +1018,7 @@ static int __init ecard_init(void)
 {
 	int slot, irqhw;
 
-#ifdef CONFIG_CPU_32
 	init_waitqueue_head(&ecard_wait);
-#endif
 
 	printk("Probing expansion cards\n");
 

arch/arm/kernel/entry-header.S

@@ -41,14 +41,8 @@
 @ Stack format (ensured by USER_* and SVC_*)
 @
 #define S_FRAME_SIZE	72
-#ifdef CONFIG_CPU_32
 #define S_OLD_R0	68
 #define S_PSR		64
-#else
-#define S_OLD_R0	64
-#define S_PSR		60
-#define S_PC		60
-#endif
 
 #define S_PC		60
 #define S_LR		56
@@ -68,8 +62,6 @@
 #define S_R0		0
 #define S_OFF		8
 
-#ifdef CONFIG_CPU_32
-
 	.macro	set_cpsr_c, reg, mode
 #if 1
 	/* broken binutils */
@@ -160,58 +152,6 @@
 #endif
 	.endm
 
-#else
-	.macro	save_user_regs
-	str	r0, [sp, #-4]!
-	str	lr, [sp, #-4]!
-	sub	sp, sp, #15*4
-	stmia	sp, {r0 - lr}^
-	mov	r0, r0
-	.endm
-
-	.macro	restore_user_regs
-	ldmia	sp, {r0 - lr}^
-	mov	r0, r0
-	ldr	lr, [sp, #15*4]
-	add	sp, sp, #15*4+8
-	movs	pc, lr
-	.endm
-
-	.macro	fast_restore_user_regs
-	add	sp, sp, #S_OFF
-	ldmib	sp, {r1 - lr}^
-	mov	r0, r0
-	ldr	lr, [sp, #15*4]
-	add	sp, sp, #15*4+8
-	movs	pc, lr
-	.endm
-
-	.macro	mask_pc, rd, rm
-	bic	\rd, \rm, #PCMASK
-	.endm
-
-	.macro	enable_irqs, temp
-	teqp	pc, #0x00000003
-	.endm
-
-	.macro	initialise_traps_extra
-	.endm
-
-	.macro	get_thread_info, rd
-	mov	\rd, sp, lsr #13
-	mov	\rd, \rd, lsl #13
-	.endm
-
-	/*
-	 * Like adr, but force SVC mode (if required)
-	 */
-	.macro	adrsvc, cond, reg, label
-	adr\cond	\reg, \label
-	orr\cond	\reg, \reg, #0x08000003
-	.endm
-
-#endif
-
 
 /*
  * These are the registers used in the syscall handler, and allow us to

arch/arm/kernel/fiq.c

@@ -54,7 +54,6 @@
 
 static unsigned long no_fiq_insn;
 
-#ifdef CONFIG_CPU_32
 static inline void unprotect_page_0(void)
 {
 	modify_domain(DOMAIN_USER, DOMAIN_MANAGER);
@@ -64,12 +63,6 @@ static inline void protect_page_0(void)
 {
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
 }
-#else
-
-#define unprotect_page_0()
-#define protect_page_0()
-
-#endif
 
 /* Default reacquire function
  * - we always relinquish FIQ control
@@ -120,17 +113,6 @@ void set_fiq_regs(struct pt_regs *regs)
 {
 	register unsigned long tmp, tmp2;
 	__asm__ volatile (
-#ifdef CONFIG_CPU_26
-	"mov	%0, pc
-	bic	%1, %0, #0x3
-	orr	%1, %1, %3
-	teqp	%1, #0		@ select FIQ mode
-	mov	r0, r0
-	ldmia	%2, {r8 - r14}
-	teqp	%0, #0		@ return to SVC mode
-	mov	r0, r0"
-#endif
-#ifdef CONFIG_CPU_32
 	"mrs	%0, cpsr
 	mov	%1, %3
 	msr	cpsr_c, %1	@ select FIQ mode
@@ -138,7 +120,6 @@ void set_fiq_regs(struct pt_regs *regs)
 	ldmia	%2, {r8 - r14}
 	msr	cpsr_c, %0	@ return to SVC mode
 	mov	r0, r0"
-#endif
 	: "=&r" (tmp), "=&r" (tmp2)
 	: "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)
 	/* These registers aren't modified by the above code in a way
@@ -152,17 +133,6 @@ void get_fiq_regs(struct pt_regs *regs)
 {
 	register unsigned long tmp, tmp2;
 	__asm__ volatile (
-#ifdef CONFIG_CPU_26
-	"mov	%0, pc
-	bic	%1, %0, #0x3
-	orr	%1, %1, %3
-	teqp	%1, #0		@ select FIQ mode
-	mov	r0, r0
-	stmia	%2, {r8 - r14}
-	teqp	%0, #0		@ return to SVC mode
-	mov	r0, r0"
-#endif
-#ifdef CONFIG_CPU_32
 	"mrs	%0, cpsr
 	mov	%1, %3
 	msr	cpsr_c, %1	@ select FIQ mode
@@ -170,7 +140,6 @@ void get_fiq_regs(struct pt_regs *regs)
 	stmia	%2, {r8 - r14}
 	msr	cpsr_c, %0	@ return to SVC mode
 	mov	r0, r0"
-#endif
 	: "=&r" (tmp), "=&r" (tmp2)
 	: "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)
 	/* These registers aren't modified by the above code in a way

arch/arm/kernel/process.c

@@ -188,7 +188,6 @@ void show_regs(struct pt_regs * regs)
 		processor_modes[processor_mode(regs)],
 		thumb_mode(regs) ? " (T)" : "",
 		get_fs() == get_ds() ? "kernel" : "user");
-#if defined(CONFIG_CPU_32)
 	{
 		unsigned int ctrl, transbase, dac;
 		  __asm__ (
@@ -199,7 +198,6 @@ void show_regs(struct pt_regs * regs)
 		printk("Control: %04X  Table: %08X  DAC: %08X\n",
 		  	ctrl, transbase, dac);
 	}
-#endif
 }
 
 void show_fpregs(struct user_fp *regs)
@@ -237,18 +235,9 @@ void show_fpregs(struct user_fp *regs)
 static unsigned long *thread_info_head;
 static unsigned int nr_thread_info;
 
-#ifdef CONFIG_CPU_32
 #define EXTRA_TASK_STRUCT	4
 #define ll_alloc_task_struct() ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
 #define ll_free_task_struct(p) free_pages((unsigned long)(p),1)
-#else
-extern unsigned long get_page_8k(int priority);
-extern void free_page_8k(unsigned long page);
-
-#define EXTRA_TASK_STRUCT	0
-#define ll_alloc_task_struct()	((struct task_struct *)get_page_8k(GFP_KERNEL))
-#define ll_free_task_struct(p)  free_page_8k((unsigned long)(p))
-#endif
 
 struct thread_info *alloc_thread_info(void)
 {

arch/arm/kernel/semaphore.c

@@ -177,44 +177,6 @@ int __down_trylock(struct semaphore * sem)
  * registers (r0 to r3 and lr), but not ip, as we use it as a return
  * value in some cases..
  */
-#ifdef CONFIG_CPU_26
-asm("	.align	5				\n\
-	.globl	__down_failed			\n\
-__down_failed:					\n\
-	stmfd	sp!, {r0 - r3, lr}		\n\
-	mov	r0, ip				\n\
-	bl	__down				\n\
-	ldmfd	sp!, {r0 - r3, pc}^		\n\
-						\n\
-	.align	5				\n\
-	.globl	__down_interruptible_failed	\n\
-__down_interruptible_failed:			\n\
-	stmfd	sp!, {r0 - r3, lr}		\n\
-	mov	r0, ip				\n\
-	bl	__down_interruptible		\n\
-	mov	ip, r0				\n\
-	ldmfd	sp!, {r0 - r3, pc}^		\n\
-						\n\
-	.align	5				\n\
-	.globl	__down_trylock_failed		\n\
-__down_trylock_failed:				\n\
-	stmfd	sp!, {r0 - r3, lr}		\n\
-	mov	r0, ip				\n\
-	bl	__down_trylock			\n\
-	mov	ip, r0				\n\
-	ldmfd	sp!, {r0 - r3, pc}^		\n\
-						\n\
-	.align	5				\n\
-	.globl	__up_wakeup			\n\
-__up_wakeup:					\n\
-	stmfd	sp!, {r0 - r3, lr}		\n\
-	mov	r0, ip				\n\
-	bl	__up				\n\
-	ldmfd	sp!, {r0 - r3, pc}^		\n\
-	");
-
-#else
-/* 32 bit version */
 asm("	.align	5				\n\
 	.globl	__down_failed			\n\
 __down_failed:					\n\
@@ -250,4 +212,3 @@ __up_wakeup:					\n\
 	ldmfd	sp!, {r0 - r3, pc}		\n\
 	");
 
-#endif

arch/arm/kernel/setup.c

@@ -113,7 +113,6 @@ static struct resource io_res[] = {
 #define lp1 io_res[1]
 #define lp2 io_res[2]
 
-#ifdef CONFIG_CPU_32
 static const char *cache_types[16] = {
 	"write-through",
 	"write-back",
@@ -231,10 +230,6 @@ static void __init dump_cpu_info(void)
 	}
 }
 
-#else
-#define dump_cpu_info() do { } while (0)
-#endif
-
 int cpu_architecture(void)
 {
 	int cpu_arch;
@@ -768,7 +763,6 @@ static int c_show(struct seq_file *m, void *v)
 	}
 	seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
 
-#ifdef CONFIG_CPU_32
 	{
 		unsigned int cache_info;
 
@@ -791,7 +785,6 @@ static int c_show(struct seq_file *m, void *v)
 			}
 		}
 	}
-#endif
 
 	seq_puts(m, "\n");
 

arch/arm/kernel/signal.c

@@ -174,9 +174,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
 	__get_user_error(regs->ARM_sp, &sc->arm_sp, err);
 	__get_user_error(regs->ARM_lr, &sc->arm_lr, err);
 	__get_user_error(regs->ARM_pc, &sc->arm_pc, err);
-#ifdef CONFIG_CPU_32
 	__get_user_error(regs->ARM_cpsr, &sc->arm_cpsr, err);
-#endif
 
 	err |= !valid_user_regs(regs);
 
@@ -292,9 +290,7 @@ setup_sigcontext(struct sigcontext *sc, /*struct _fpstate *fpstate,*/
 	__put_user_error(regs->ARM_sp, &sc->arm_sp, err);
 	__put_user_error(regs->ARM_lr, &sc->arm_lr, err);
 	__put_user_error(regs->ARM_pc, &sc->arm_pc, err);
-#ifdef CONFIG_CPU_32
 	__put_user_error(regs->ARM_cpsr, &sc->arm_cpsr, err);
-#endif
 
 	__put_user_error(current->thread.trap_no, &sc->trap_no, err);
 	__put_user_error(current->thread.error_code, &sc->error_code, err);
@@ -328,7 +324,6 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 	unsigned long handler = (unsigned long)ka->sa.sa_handler;
 	unsigned long retcode;
 	int thumb = 0;
-#ifdef CONFIG_CPU_32
 	unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
 
 	/*
@@ -350,7 +345,6 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 		else
 			cpsr &= ~PSR_T_BIT;
 	}
-#endif
 #endif
 
 	if (ka->sa.sa_flags & SA_RESTORER) {
@@ -378,10 +372,7 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 	regs->ARM_sp = (unsigned long)frame;
 	regs->ARM_lr = retcode;
 	regs->ARM_pc = handler;
-
-#ifdef CONFIG_CPU_32
 	regs->ARM_cpsr = cpsr;
-#endif
 
 	return 0;
 }

arch/arm/kernel/traps.c

@@ -271,31 +271,6 @@ asmlinkage void do_undefinstr(struct pt_regs *regs)
 	die_if_kernel("Oops - undefined instruction", regs, 0);
 }
 
-#ifdef CONFIG_CPU_26
-asmlinkage void do_excpt(unsigned long address, struct pt_regs *regs, int mode)
-{
-	siginfo_t info;
-
-#ifdef CONFIG_DEBUG_USER
-	printk(KERN_INFO "%s (%d): address exception: pc=%08lx\n",
-		current->comm, current->pid, instruction_pointer(regs));
-	dump_instr(regs);
-#endif
-
-	current->thread.error_code = 0;
-	current->thread.trap_no = 11;
-
-	info.si_signo = SIGBUS;
-	info.si_errno = 0;
-	info.si_code  = BUS_ADRERR;
-	info.si_addr  = (void *)address;
-
-	force_sig_info(SIGBUS, &info, current);
-
-	die_if_kernel("Oops - address exception", regs, mode);
-}
-#endif
-
 asmlinkage void do_unexp_fiq (struct pt_regs *regs)
 {
 #ifndef CONFIG_IGNORE_FIQ
@@ -405,7 +380,6 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		ptrace_break(current, regs);
 		return regs->ARM_r0;
 
-#ifdef CONFIG_CPU_32
 	/*
 	 * Flush a region from virtual address 'r0' to virtual address 'r1'
 	 * _inclusive_.  There is no alignment requirement on either address;
@@ -435,14 +409,6 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 			break;
 		regs->ARM_cpsr |= MODE32_BIT;
 		return regs->ARM_r0;
-#else
-	case NR(cacheflush):
-		return 0;
-
-	case NR(usr26):
-	case NR(usr32):
-		break;
-#endif
 
 	default:
 		/* Calls 9f00xx..9f07ff are defined to return -ENOSYS
@@ -563,7 +529,5 @@ void __init trap_init(void)
 	if (base != 0)
 		printk(KERN_DEBUG "Relocating machine vectors to 0x%08lx\n",
 			base);
-#ifdef CONFIG_CPU_32
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
-#endif
 }

arch/arm/lib/copy_page.S

@@ -13,6 +13,12 @@
 #include <asm/assembler.h>
 #include <asm/constants.h>
 
+#ifndef PLD
+#define COPY_COUNT PAGE_SZ/64
+#else
+#define COPY_COUNT PAGE_SZ/64-1
+#endif
+
 		.text
 		.align	5
 /*
@@ -23,9 +29,13 @@
  */
 ENTRY(copy_page)
 		stmfd	sp!, {r4, lr}			@	2
-		mov	r2, #PAGE_SZ/64			@	1
+	PLD(	pld	[r1, #0]		)
+	PLD(	pld	[r1, #32]		)
+		mov	r2, #COPY_COUNT			@	1
 		ldmia	r1!, {r3, r4, ip, lr}		@	4+1
-1:		stmia	r0!, {r3, r4, ip, lr}		@	4
+1:	PLD(	pld	[r1, #64]		)
+	PLD(	pld	[r1, #96]		)
+2:		stmia	r0!, {r3, r4, ip, lr}		@	4
 		ldmia	r1!, {r3, r4, ip, lr}		@	4+1
 		stmia	r0!, {r3, r4, ip, lr}		@	4
 		ldmia	r1!, {r3, r4, ip, lr}		@	4+1
@@ -33,6 +43,8 @@ ENTRY(copy_page)
 		ldmia	r1!, {r3, r4, ip, lr}		@	4
 		subs	r2, r2, #1			@	1
 		stmia	r0!, {r3, r4, ip, lr}		@	4
-		ldmneia	r1!, {r3, r4, ip, lr}		@	4
-		bne	1b				@	1
+		ldmgtia	r1!, {r3, r4, ip, lr}		@	4
+		bgt	1b				@	1
+	PLD(	ldmeqia r1!, {r3, r4, ip, lr}	)
+	PLD(	beq	2b			)
 		LOADREGS(fd, sp!, {r4, pc})		@	3

arch/arm/lib/memcpy.S

@@ -27,15 +27,15 @@
 
 /*
  * Prototype: void memcpy(void *to,const void *from,unsigned long n);
- * ARM3: cant use memcopy here!!!
  */
 ENTRY(memcpy)
 ENTRY(memmove)
 		ENTER
 		cmp	r1, r0
-		bcc	19f
+		bcc	23f
 		subs	r2, r2, #4
 		blt	6f
+	PLD(	pld	[r1, #0]		)
 		ands	ip, r0, #3
 		bne	7f
 		ands	ip, r1, #3
@@ -43,29 +43,42 @@ ENTRY(memmove)
 
 1:		subs	r2, r2, #8
 		blt	5f
-		subs	r2, r2, #0x14
-		blt	3f
-2:		ldmia	r1!,{r3 - r9, ip}
-		stmia	r0!,{r3 - r9, ip}
+		subs	r2, r2, #20
+		blt	4f
+	PLD(	pld	[r1, #28]		)
+	PLD(	subs	r2, r2, #64		)
+	PLD(	blt	3f			)
+2:	PLD(	pld	[r1, #60]		)
+	PLD(	pld	[r1, #92]		)
+		ldmia	r1!, {r3 - r9, ip}
 		subs	r2, r2, #32
+		stmgeia	r0!, {r3 - r9, ip}
+		ldmgeia	r1!, {r3 - r9, ip}
+		subges	r2, r2, #32
+		stmia	r0!, {r3 - r9, ip}
 		bge	2b
-		cmn	r2, #16
+3:	PLD(	ldmia	r1!, {r3 - r9, ip}	)
+	PLD(	adds	r2, r2, #32		)
+	PLD(	stmgeia	r0!, {r3 - r9, ip}	)
+	PLD(	ldmgeia	r1!, {r3 - r9, ip}	)
+	PLD(	subges	r2, r2, #32		)
+	PLD(	stmia	r0!, {r3 - r9, ip}	)
+4:		cmn	r2, #16
 		ldmgeia	r1!, {r3 - r6}
+		subge	r2, r2, #16
 		stmgeia	r0!, {r3 - r6}
-		subge	r2, r2, #0x10
-3:		adds	r2, r2, #0x14
-4:		ldmgeia	r1!, {r3 - r5}
+		adds	r2, r2, #20
+		ldmgeia	r1!, {r3 - r5}
+		subge	r2, r2, #12
 		stmgeia	r0!, {r3 - r5}
-		subges	r2, r2, #12
-		bge	4b
 5:		adds	r2, r2, #8
 		blt	6f
 		subs	r2, r2, #4
 		ldrlt	r3, [r1], #4
 		ldmgeia	r1!, {r4, r5}
+		subge	r2, r2, #4
 		strlt	r3, [r0], #4
 		stmgeia	r0!, {r4, r5}
-		subge	r2, r2, #4
 
 6:		adds	r2, r2, #4
 		EXITEQ
@@ -94,13 +107,19 @@ ENTRY(memmove)
 8:		bic	r1, r1, #3
 		ldr	r7, [r1], #4
 		cmp	ip, #2
-		bgt	15f
-		beq	11f
+		bgt	18f
+		beq	13f
 		cmp	r2, #12
-		blt	10f
+		blt	11f
+	PLD(	pld	[r1, #12]		)
 		sub	r2, r2, #12
-9:		mov	r3, r7, pull #8
+	PLD(	subs	r2, r2, #32		)
+	PLD(	blt	10f			)
+	PLD(	pld	[r1, #28]		)
+9:	PLD(	pld	[r1, #44]		)
+10:		mov	r3, r7, pull #8
 		ldmia	r1!, {r4 - r7}
+		subs	r2, r2, #16
 		orr	r3, r3, r4, push #24
 		mov	r4, r4, pull #8
 		orr	r4, r4, r5, push #24
@@ -109,24 +128,32 @@ ENTRY(memmove)
 		mov	r6, r6, pull #8
 		orr	r6, r6, r7, push #24
 		stmia	r0!, {r3 - r6}
-		subs	r2, r2, #16
 		bge	9b
+	PLD(	cmn	r2, #32			)
+	PLD(	bge	10b			)
+	PLD(	add	r2, r2, #32		)
 		adds	r2, r2, #12
-		blt	100f
-10:		mov	r3, r7, pull #8
+		blt	12f
+11:		mov	r3, r7, pull #8
 		ldr	r7, [r1], #4
 		subs	r2, r2, #4
 		orr	r3, r3, r7, push #24
 		str	r3, [r0], #4
-		bge	10b
-100:		sub	r1, r1, #3
+		bge	11b
+12:		sub	r1, r1, #3
 		b	6b
 
-11:		cmp	r2, #12
-		blt	13f		/* */
+13:		cmp	r2, #12
+		blt	16f
+	PLD(	pld	[r1, #12]		)
 		sub	r2, r2, #12
-12:		mov	r3, r7, pull #16
+	PLD(	subs	r2, r2, #32		)
+	PLD(	blt	15f			)
+	PLD(	pld	[r1, #28]		)
+14:	PLD(	pld	[r1, #44]		)
+15:		mov	r3, r7, pull #16
 		ldmia	r1!, {r4 - r7}
+		subs	r2, r2, #16
 		orr	r3, r3, r4, push #16
 		mov	r4, r4, pull #16
 		orr	r4, r4, r5, push #16
@@ -135,24 +162,32 @@ ENTRY(memmove)
 		mov	r6, r6, pull #16
 		orr	r6, r6, r7, push #16
 		stmia	r0!, {r3 - r6}
-		subs	r2, r2, #16
-		bge	12b
+		bge	14b
+	PLD(	cmn	r2, #32			)
+	PLD(	bge	15b			)
+	PLD(	add	r2, r2, #32		)
 		adds	r2, r2, #12
-		blt	14f
-13:		mov	r3, r7, pull #16
+		blt	17f
+16:		mov	r3, r7, pull #16
 		ldr	r7, [r1], #4
 		subs	r2, r2, #4
 		orr	r3, r3, r7, push #16
 		str	r3, [r0], #4
-		bge	13b
-14:		sub	r1, r1, #2
+		bge	16b
+17:		sub	r1, r1, #2
 		b	6b
 
-15:		cmp	r2, #12
-		blt	17f
+18:		cmp	r2, #12
+		blt	21f
+	PLD(	pld	[r1, #12]		)
 		sub	r2, r2, #12
-16:		mov	r3, r7, pull #24
+	PLD(	subs	r2, r2, #32		)
+	PLD(	blt	20f			)
+	PLD(	pld	[r1, #28]		)
+19:	PLD(	pld	[r1, #44]		)
+20:		mov	r3, r7, pull #24
 		ldmia	r1!, {r4 - r7}
+		subs	r2, r2, #16
 		orr	r3, r3, r4, push #8
 		mov	r4, r4, pull #24
 		orr	r4, r4, r5, push #8
@@ -161,55 +196,72 @@ ENTRY(memmove)
 		mov	r6, r6, pull #24
 		orr	r6, r6, r7, push #8
 		stmia	r0!, {r3 - r6}
-		subs	r2, r2, #16
-		bge	16b
+		bge	19b
+	PLD(	cmn	r2, #32			)
+	PLD(	bge	20b			)
+	PLD(	add	r2, r2, #32		)
 		adds	r2, r2, #12
-		blt	18f
-17:		mov	r3, r7, pull #24
+		blt	22f
+21:		mov	r3, r7, pull #24
 		ldr	r7, [r1], #4
 		subs	r2, r2, #4
 		orr	r3, r3, r7, push #8
 		str	r3, [r0], #4
-		bge	17b
-18:		sub	r1, r1, #1
+		bge	21b
+22:		sub	r1, r1, #1
 		b	6b
 
 
-19:		add	r1, r1, r2
+23:		add	r1, r1, r2
 		add	r0, r0, r2
 		subs	r2, r2, #4
-		blt	24f
+		blt	29f
+	PLD(	pld	[r1, #-4]		)
 		ands	ip, r0, #3
-		bne	25f
+		bne	30f
 		ands	ip, r1, #3
-		bne	26f
+		bne	31f
 
-20:		subs	r2, r2, #8
-		blt	23f
-		subs	r2, r2, #0x14
-		blt	22f
-21:		ldmdb	r1!, {r3 - r9, ip}
-		stmdb	r0!, {r3 - r9, ip}
+24:		subs	r2, r2, #8
+		blt	28f
+		subs	r2, r2, #20
+		blt	27f
+	PLD(	pld	[r1, #-32]		)
+	PLD(	subs	r2, r2, #64		)
+	PLD(	blt	26f			)
+25:	PLD(	pld	[r1, #-64]		)
+	PLD(	pld	[r1, #-96]		)
+		ldmdb	r1!, {r3 - r9, ip}
 		subs	r2, r2, #32
-		bge	21b
-22:		cmn	r2, #16
+		stmgedb	r0!, {r3 - r9, ip}
+		ldmgedb	r1!, {r3 - r9, ip}
+		subges	r2, r2, #32
+		stmdb	r0!, {r3 - r9, ip}
+		bge	25b
+26:	PLD(	ldmdb	r1!, {r3 - r9, ip}	)
+	PLD(	adds	r2, r2, #32		)
+	PLD(	stmgedb	r0!, {r3 - r9, ip}	)
+	PLD(	ldmgedb	r1!, {r3 - r9, ip}	)
+	PLD(	subges	r2, r2, #32		)
+	PLD(	stmdb	r0!, {r3 - r9, ip}	)
+27:		cmn	r2, #16
 		ldmgedb	r1!, {r3 - r6}
-		stmgedb	r0!, {r3 - r6}
 		subge	r2, r2, #16
+		stmgedb	r0!, {r3 - r6}
 		adds	r2, r2, #20
 		ldmgedb	r1!, {r3 - r5}
-		stmgedb	r0!, {r3 - r5}
 		subge	r2, r2, #12
-23:		adds	r2, r2, #8
-		blt	24f
+		stmgedb	r0!, {r3 - r5}
+28:		adds	r2, r2, #8
+		blt	29f
 		subs	r2, r2, #4
 		ldrlt	r3, [r1, #-4]!
 		ldmgedb	r1!, {r4, r5}
+		subge	r2, r2, #4
 		strlt	r3, [r0, #-4]!
 		stmgedb	r0!, {r4, r5}
-		subge	r2, r2, #4
 
-24:		adds	r2, r2, #4
+29:		adds	r2, r2, #4
 		EXITEQ
 		cmp	r2, #2
 		ldrb	r3, [r1, #-1]!
@@ -220,7 +272,7 @@ ENTRY(memmove)
 		strgtb	r5, [r0, #-1]!
 		EXIT
 
-25:		cmp	ip, #2
+30:		cmp	ip, #2
 		ldrb	r3, [r1, #-1]!
 		ldrgeb	r4, [r1, #-1]!
 		ldrgtb	r5, [r1, #-1]!
@@ -228,20 +280,26 @@ ENTRY(memmove)
 		strgeb	r4, [r0, #-1]!
 		strgtb	r5, [r0, #-1]!
 		subs	r2, r2, ip
-		blt	24b
+		blt	29b
 		ands	ip, r1, #3
-		beq	20b
+		beq	24b
 
-26:		bic	r1, r1, #3
+31:		bic	r1, r1, #3
 		ldr	r3, [r1], #0
 		cmp	ip, #2
-		blt	34f
-		beq	30f
+		blt	41f
+		beq	36f
 		cmp	r2, #12
-		blt	28f
+		blt	34f
+	PLD(	pld	[r1, #-16]		)
 		sub	r2, r2, #12
-27:		mov	r7, r3, push #8
+	PLD(	subs	r2, r2, #32		)
+	PLD(	blt	33f			)
+	PLD(	pld	[r1, #-32]		)
+32:	PLD(	pld	[r1, #-48]		)
+33:		mov	r7, r3, push #8
 		ldmdb	r1!, {r3, r4, r5, r6}
+		subs	r2, r2, #16
 		orr	r7, r7, r6, pull #24
 		mov	r6, r6, push #8
 		orr	r6, r6, r5, pull #24
@@ -250,24 +308,32 @@ ENTRY(memmove)
 		mov	r4, r4, push #8
 		orr	r4, r4, r3, pull #24
 		stmdb	r0!, {r4, r5, r6, r7}
-		subs	r2, r2, #16
-		bge	27b
+		bge	32b
+	PLD(	cmn	r2, #32			)
+	PLD(	bge	33b			)
+	PLD(	add	r2, r2, #32		)
 		adds	r2, r2, #12
-		blt	29f
-28:		mov	ip, r3, push #8
+		blt	35f
+34:		mov	ip, r3, push #8
 		ldr	r3, [r1, #-4]!
 		subs	r2, r2, #4
 		orr	ip, ip, r3, pull #24
 		str	ip, [r0, #-4]!
-		bge	28b
-29:		add	r1, r1, #3
-		b	24b
+		bge	34b
+35:		add	r1, r1, #3
+		b	29b
 
-30:		cmp	r2, #12
-		blt	32f
+36:		cmp	r2, #12
+		blt	39f
+	PLD(	pld	[r1, #-16]		)
 		sub	r2, r2, #12
-31:		mov	r7, r3, push #16
+	PLD(	subs	r2, r2, #32		)
+	PLD(	blt	38f			)
+	PLD(	pld	[r1, #-32]		)
+37:	PLD(	pld	[r1, #-48]		)
+38:		mov	r7, r3, push #16
 		ldmdb	r1!, {r3, r4, r5, r6}
+		subs	r2, r2, #16
 		orr	r7, r7, r6, pull #16
 		mov	r6, r6, push #16
 		orr	r6, r6, r5, pull #16
@@ -276,24 +342,32 @@ ENTRY(memmove)
 		mov	r4, r4, push #16
 		orr	r4, r4, r3, pull #16
 		stmdb	r0!, {r4, r5, r6, r7}
-		subs	r2, r2, #16
-		bge	31b
+		bge	37b
+	PLD(	cmn	r2, #32			)
+	PLD(	bge	38b			)
+	PLD(	add	r2, r2, #32		)
 		adds	r2, r2, #12
-		blt	33f
-32:		mov	ip, r3, push #16
+		blt	40f
+39:		mov	ip, r3, push #16
 		ldr	r3, [r1, #-4]!
 		subs	r2, r2, #4
 		orr	ip, ip, r3, pull #16
 		str	ip, [r0, #-4]!
-		bge	32b
-33:		add	r1, r1, #2
-		b	24b
+		bge	39b
+40:		add	r1, r1, #2
+		b	29b
 
-34:		cmp	r2, #12
-		blt	36f
+41:		cmp	r2, #12
+		blt	44f
+	PLD(	pld	[r1, #-16]		)
 		sub	r2, r2, #12
-35:		mov	r7, r3, push #24
+	PLD(	subs	r2, r2, #32		)
+	PLD(	blt	43f			)
+	PLD(	pld	[r1, #-32]		)
+42:	PLD(	pld	[r1, #-48]		)
+43:		mov	r7, r3, push #24
 		ldmdb	r1!, {r3, r4, r5, r6}
+		subs	r2, r2, #16
 		orr	r7, r7, r6, pull #8
 		mov	r6, r6, push #24
 		orr	r6, r6, r5, pull #8
@@ -302,17 +376,18 @@ ENTRY(memmove)
 		mov	r4, r4, push #24
 		orr	r4, r4, r3, pull #8
 		stmdb	r0!, {r4, r5, r6, r7}
-		subs	r2, r2, #16
-		bge	35b
+		bge	42b
+	PLD(	cmn	r2, #32			)
+	PLD(	bge	43b			)
+	PLD(	add	r2, r2, #32		)
 		adds	r2, r2, #12
-		blt	37f
-36:		mov	ip, r3, push #24
+		blt	45f
+44:		mov	ip, r3, push #24
 		ldr	r3, [r1, #-4]!
 		subs	r2, r2, #4
 		orr	ip, ip, r3, pull #8
 		str	ip, [r0, #-4]!
-		bge	36b
-37:		add	r1, r1, #1
-		b	24b
+		bge	44b
+45:		add	r1, r1, #1
+		b	29b
 
-		.align

arch/arm/lib/uaccess.S

@@ -43,6 +43,8 @@ ENTRY(__arch_copy_to_user)
 		stmfd	sp!, {r2, r4 - r7, lr}
 		cmp	r2, #4
 		blt	.c2u_not_enough
+	PLD(	pld	[r1, #0]		)
+	PLD(	pld	[r0, #0]		)
 		ands	ip, r0, #3
 		bne	.c2u_dest_not_aligned
 .c2u_dest_aligned:
@@ -71,13 +73,26 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #32
 		blt	.c2u_0rem8lp
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
+	PLD(	subs	ip, ip, #64			)
+	PLD(	blt	.c2u_0cpynopld		)
+	PLD(	pld	[r1, #60]		)
+	PLD(	pld	[r0, #60]		)
 
-.c2u_0cpy8lp:	ldmia	r1!, {r3 - r6}
+.c2u_0cpy8lp:
+	PLD(	pld	[r1, #92]		)
+	PLD(	pld	[r0, #92]		)
+.c2u_0cpynopld:	ldmia	r1!, {r3 - r6}
 		stmia	r0!, {r3 - r6}			@ Shouldnt fault
 		ldmia	r1!, {r3 - r6}
-		stmia	r0!, {r3 - r6}			@ Shouldnt fault
 		subs	ip, ip, #32
+		stmia	r0!, {r3 - r6}			@ Shouldnt fault
 		bpl	.c2u_0cpy8lp
+	PLD(	cmn	ip, #64			)
+	PLD(	bge	.c2u_0cpynopld		)
+	PLD(	add	ip, ip, #64		)
+
 .c2u_0rem8lp:	cmn	ip, #16
 		ldmgeia	r1!, {r3 - r6}
 		stmgeia	r0!, {r3 - r6}			@ Shouldnt fault
@@ -128,9 +143,19 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #16
 		blt	.c2u_1rem8lp
+	PLD(	pld	[r1, #12]		)
+	PLD(	pld	[r0, #12]		)
+	PLD(	subs	ip, ip, #32		)
+	PLD(	blt	.c2u_1cpynopld		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
 
-.c2u_1cpy8lp:	mov	r3, r7, pull #8
+.c2u_1cpy8lp:
+	PLD(	pld	[r1, #44]		)
+	PLD(	pld	[r0, #44]		)
+.c2u_1cpynopld:	mov	r3, r7, pull #8
 		ldmia	r1!, {r4 - r7}
+		subs	ip, ip, #16
 		orr	r3, r3, r4, push #24
 		mov	r4, r4, pull #8
 		orr	r4, r4, r5, push #24
@@ -139,8 +164,11 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		mov	r6, r6, pull #8
 		orr	r6, r6, r7, push #24
 		stmia	r0!, {r3 - r6}			@ Shouldnt fault
-		subs	ip, ip, #16
 		bpl	.c2u_1cpy8lp
+	PLD(	cmn	ip, #32			)
+	PLD(	bge	.c2u_1cpynopld		)
+	PLD(	add	ip, ip, #32		)
+
 .c2u_1rem8lp:	tst	ip, #8
 		movne	r3, r7, pull #8
 		ldmneia	r1!, {r4, r7}
@@ -182,9 +210,19 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #16
 		blt	.c2u_2rem8lp
+	PLD(	pld	[r1, #12]		)
+	PLD(	pld	[r0, #12]		)
+	PLD(	subs	ip, ip, #32		)
+	PLD(	blt	.c2u_2cpynopld		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
 
-.c2u_2cpy8lp:	mov	r3, r7, pull #16
+.c2u_2cpy8lp:
+	PLD(	pld	[r1, #44]		)
+	PLD(	pld	[r0, #44]		)
+.c2u_2cpynopld:	mov	r3, r7, pull #16
 		ldmia	r1!, {r4 - r7}
+		subs	ip, ip, #16
 		orr	r3, r3, r4, push #16
 		mov	r4, r4, pull #16
 		orr	r4, r4, r5, push #16
@@ -193,8 +231,11 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		mov	r6, r6, pull #16
 		orr	r6, r6, r7, push #16
 		stmia	r0!, {r3 - r6}			@ Shouldnt fault
-		subs	ip, ip, #16
 		bpl	.c2u_2cpy8lp
+	PLD(	cmn	ip, #32			)
+	PLD(	bge	.c2u_2cpynopld		)
+	PLD(	add	ip, ip, #32		)
+
 .c2u_2rem8lp:	tst	ip, #8
 		movne	r3, r7, pull #16
 		ldmneia	r1!, {r4, r7}
@@ -236,9 +277,19 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #16
 		blt	.c2u_3rem8lp
+	PLD(	pld	[r1, #12]		)
+	PLD(	pld	[r0, #12]		)
+	PLD(	subs	ip, ip, #32		)
+	PLD(	blt	.c2u_3cpynopld		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
 
-.c2u_3cpy8lp:	mov	r3, r7, pull #24
+.c2u_3cpy8lp:
+	PLD(	pld	[r1, #44]		)
+	PLD(	pld	[r0, #44]		)
+.c2u_3cpynopld:	mov	r3, r7, pull #24
 		ldmia	r1!, {r4 - r7}
+		subs	ip, ip, #16
 		orr	r3, r3, r4, push #8
 		mov	r4, r4, pull #24
 		orr	r4, r4, r5, push #8
@@ -247,8 +298,11 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		mov	r6, r6, pull #24
 		orr	r6, r6, r7, push #8
 		stmia	r0!, {r3 - r6}			@ Shouldnt fault
-		subs	ip, ip, #16
 		bpl	.c2u_3cpy8lp
+	PLD(	cmn	ip, #32			)
+	PLD(	bge	.c2u_3cpynopld		)
+	PLD(	add	ip, ip, #32		)
+
 .c2u_3rem8lp:	tst	ip, #8
 		movne	r3, r7, pull #24
 		ldmneia	r1!, {r4, r7}
@@ -302,6 +356,8 @@ ENTRY(__arch_copy_from_user)
 		stmfd	sp!, {r0, r2, r4 - r7, lr}
 		cmp	r2, #4
 		blt	.cfu_not_enough
+	PLD(	pld	[r1, #0]		)
+	PLD(	pld	[r0, #0]		)
 		ands	ip, r0, #3
 		bne	.cfu_dest_not_aligned
 .cfu_dest_aligned:
@@ -329,13 +385,26 @@ USER(		ldrt	r3, [r1], #4)
 		sub	r2, r2, ip
 		subs	ip, ip, #32
 		blt	.cfu_0rem8lp
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
+	PLD(	subs	ip, ip, #64			)
+	PLD(	blt	.cfu_0cpynopld		)
+	PLD(	pld	[r1, #60]		)
+	PLD(	pld	[r0, #60]		)
 
-.cfu_0cpy8lp:	ldmia	r1!, {r3 - r6}			@ Shouldnt fault
+.cfu_0cpy8lp:
+	PLD(	pld	[r1, #92]		)
+	PLD(	pld	[r0, #92]		)
+.cfu_0cpynopld:	ldmia	r1!, {r3 - r6}			@ Shouldnt fault
 		stmia	r0!, {r3 - r6}
 		ldmia	r1!, {r3 - r6}			@ Shouldnt fault
-		stmia	r0!, {r3 - r6}
 		subs	ip, ip, #32
+		stmia	r0!, {r3 - r6}
 		bpl	.cfu_0cpy8lp
+	PLD(	cmn	ip, #64			)
+	PLD(	bge	.cfu_0cpynopld		)
+	PLD(	add	ip, ip, #64		)
+
 .cfu_0rem8lp:	cmn	ip, #16
 		ldmgeia	r1!, {r3 - r6}			@ Shouldnt fault
 		stmgeia	r0!, {r3 - r6}
@@ -387,9 +456,19 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #16
 		blt	.cfu_1rem8lp
+	PLD(	pld	[r1, #12]		)
+	PLD(	pld	[r0, #12]		)
+	PLD(	subs	ip, ip, #32		)
+	PLD(	blt	.cfu_1cpynopld		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
 
-.cfu_1cpy8lp:	mov	r3, r7, pull #8
+.cfu_1cpy8lp:
+	PLD(	pld	[r1, #44]		)
+	PLD(	pld	[r0, #44]		)
+.cfu_1cpynopld:	mov	r3, r7, pull #8
 		ldmia	r1!, {r4 - r7}			@ Shouldnt fault
+		subs	ip, ip, #16
 		orr	r3, r3, r4, push #24
 		mov	r4, r4, pull #8
 		orr	r4, r4, r5, push #24
@@ -398,8 +477,11 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		mov	r6, r6, pull #8
 		orr	r6, r6, r7, push #24
 		stmia	r0!, {r3 - r6}
-		subs	ip, ip, #16
 		bpl	.cfu_1cpy8lp
+	PLD(	cmn	ip, #32			)
+	PLD(	bge	.cfu_1cpynopld		)
+	PLD(	add	ip, ip, #32		)
+
 .cfu_1rem8lp:	tst	ip, #8
 		movne	r3, r7, pull #8
 		ldmneia	r1!, {r4, r7}			@ Shouldnt fault
@@ -441,9 +523,19 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #16
 		blt	.cfu_2rem8lp
+	PLD(	pld	[r1, #12]		)
+	PLD(	pld	[r0, #12]		)
+	PLD(	subs	ip, ip, #32		)
+	PLD(	blt	.cfu_2cpynopld		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
 
-.cfu_2cpy8lp:	mov	r3, r7, pull #16
+.cfu_2cpy8lp:
+	PLD(	pld	[r1, #44]		)
+	PLD(	pld	[r0, #44]		)
+.cfu_2cpynopld:	mov	r3, r7, pull #16
 		ldmia	r1!, {r4 - r7}			@ Shouldnt fault
+		subs	ip, ip, #16
 		orr	r3, r3, r4, push #16
 		mov	r4, r4, pull #16
 		orr	r4, r4, r5, push #16
@@ -452,8 +544,11 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		mov	r6, r6, pull #16
 		orr	r6, r6, r7, push #16
 		stmia	r0!, {r3 - r6}
-		subs	ip, ip, #16
 		bpl	.cfu_2cpy8lp
+	PLD(	cmn	ip, #32			)
+	PLD(	bge	.cfu_2cpynopld		)
+	PLD(	add	ip, ip, #32		)
+
 .cfu_2rem8lp:	tst	ip, #8
 		movne	r3, r7, pull #16
 		ldmneia	r1!, {r4, r7}			@ Shouldnt fault
@@ -495,8 +590,17 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		sub	r2, r2, ip
 		subs	ip, ip, #16
 		blt	.cfu_3rem8lp
+	PLD(	pld	[r1, #12]		)
+	PLD(	pld	[r0, #12]		)
+	PLD(	subs	ip, ip, #32		)
+	PLD(	blt	.cfu_3cpynopld		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	pld	[r0, #28]		)
 
-.cfu_3cpy8lp:	mov	r3, r7, pull #24
+.cfu_3cpy8lp:
+	PLD(	pld	[r1, #44]		)
+	PLD(	pld	[r0, #44]		)
+.cfu_3cpynopld:	mov	r3, r7, pull #24
 		ldmia	r1!, {r4 - r7}			@ Shouldnt fault
 		orr	r3, r3, r4, push #8
 		mov	r4, r4, pull #24
@@ -508,6 +612,10 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmia	r0!, {r3 - r6}
 		subs	ip, ip, #16
 		bpl	.cfu_3cpy8lp
+	PLD(	cmn	ip, #32			)
+	PLD(	bge	.cfu_3cpynopld		)
+	PLD(	add	ip, ip, #32		)
+
 .cfu_3rem8lp:	tst	ip, #8
 		movne	r3, r7, pull #24
 		ldmneia	r1!, {r4, r7}			@ Shouldnt fault

arch/arm/mach-iop310/arch.c → arch/arm/mach-iop3xx/arch.c

 /*
- * linux/arch/arm/mach-iop310/arch.c
+ * linux/arch/arm/mach-iop3xx/arch.c
  *
  * Author: Nicolas Pitre <nico@cam.org>
  * Copyright (C) 2001 MontaVista Software, Inc.

arch/arm/mach-iop310/iop310-irq.c → arch/arm/mach-iop3xx/iop310-irq.c

 /*
- * linux/arch/arm/mach-iop310/iop310-irq.c
+ * linux/arch/arm/mach-iop3xx/iop310-irq.c
  *
  * Generic IOP310 IRQ handling functionality
  *

arch/arm/mach-iop310/iop310-pci.c → arch/arm/mach-iop3xx/iop310-pci.c

 /*
- * arch/arm/mach-iop310/iop310-pci.c
+ * arch/arm/mach-iop3xx/iop310-pci.c
  *
  * PCI support for the Intel IOP310 chipset
  *

arch/arm/mach-iop310/iq80310-irq.c → arch/arm/mach-iop3xx/iq80310-irq.c

 /*
- * linux/arch/arm/mach-iop310/iq80310-irq.c
+ * linux/arch/arm/mach-iop3xx/iq80310-irq.c
  *
  * IRQ hadling/demuxing for IQ80310 board
  *

arch/arm/mach-iop310/iq80310-pci.c → arch/arm/mach-iop3xx/iq80310-pci.c

 /*
- * arch/arm/mach-iop310/iq80310-pci.c
+ * arch/arm/mach-iop3xx/iq80310-pci.c
  *
  * PCI support for the Intel IQ80310 reference board
  *

arch/arm/mach-iop310/iq80310-time.c → arch/arm/mach-iop3xx/iq80310-time.c

 /*
- * linux/arch/arm/mach-iop310/time-iq80310.c
+ * linux/arch/arm/mach-iop3xx/time-iq80310.c
  *
  * Timer functions for IQ80310 onboard timer
  *

arch/arm/mach-iop310/mm.c → arch/arm/mach-iop3xx/mm.c

 /*
- * linux/arch/arm/mach-iop310/mm.c
+ * linux/arch/arm/mach-iop3xx/mm.c
  *
  * Low level memory initialization for IOP310 based systems
  *

arch/arm/mach-iop310/xs80200-irq.c → arch/arm/mach-iop3xx/xs80200-irq.c

 /*
- * linux/arch/arm/mach-iop310/xs80200-irq.c
+ * linux/arch/arm/mach-iop3xx/xs80200-irq.c
  *
  * Generic IRQ handling for the XS80200 XScale core.
  *

arch/arm/mach-sa1100/badge4.c

@@ -186,11 +186,26 @@ static struct map_desc badge4_io_desc[] __initdata = {
   {0xf4000000, 0x48000000, 0x00100000, MT_DEVICE } /* SA-1111      */
 };
 
+static void
+badge4_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+	if (!state) {
+		Ser1SDCR0 |= SDCR0_UART;
+	}
+}
+
+static struct sa1100_port_fns badge4_port_fns __initdata = {
+	//.get_mctrl	= badge4_get_mctrl,
+	//.set_mctrl	= badge4_set_mctrl,
+	.pm		= badge4_uart_pm,
+};
+
 static void __init badge4_map_io(void)
 {
 	sa1100_map_io();
 	iotable_init(badge4_io_desc, ARRAY_SIZE(badge4_io_desc));
 
+	sa1100_register_uart_fns(&badge4_port_fns);
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1);
 }

arch/arm/mm/copypage-xscale.S

@@ -39,11 +39,25 @@ ENTRY(xscale_mc_copy_user_page)
 	mov	r0, r1
 	bl	map_page_minicache
 	mov	r1, r5
-	mov	lr, #PAGE_SZ/32
+	mov	lr, #PAGE_SZ/64-1
 
-1:	mov	ip, r1
-	ldrd	r2, [r0], #8
+	/*
+	 * Strangely enough, best performance is achieved
+	 * when prefetching destination as well.  (NP)
+	 */
+	pld	[r0, #0]
+	pld	[r0, #32]
+	pld	[r1, #0]
+	pld	[r1, #32]
+
+1:	pld	[r0, #64]
+	pld	[r0, #96]
+	pld	[r1, #64]
+	pld	[r1, #96]
+
+2:	ldrd	r2, [r0], #8
 	ldrd	r4, [r0], #8
+	mov	ip, r1
 	strd	r2, [r1], #8
 	ldrd	r2, [r0], #8
 	strd	r4, [r1], #8
@@ -51,9 +65,21 @@ ENTRY(xscale_mc_copy_user_page)
 	strd	r2, [r1], #8
 	strd	r4, [r1], #8
 	mcr	p15, 0, ip, c7, c10, 1		@ clean D line
+	ldrd	r2, [r0], #8
 	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line
+	ldrd	r4, [r0], #8
+	mov	ip, r1
+	strd	r2, [r1], #8
+	ldrd	r2, [r0], #8
+	strd	r4, [r1], #8
+	ldrd	r4, [r0], #8
+	strd	r2, [r1], #8
+	strd	r4, [r1], #8
+	mcr	p15, 0, ip, c7, c10, 1		@ clean D line
 	subs	lr, lr, #1
-	bne	1b
+	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line
+	bgt	1b
+	beq	2b
 
 	ldmfd	sp!, {r4, r5, pc}
 
@@ -64,7 +90,6 @@ ENTRY(xscale_mc_copy_user_page)
  *  r1 = virtual user address of ultimate destination page
  */
 ENTRY(xscale_mc_clear_user_page)
-	str	lr, [sp, #-4]!
 	mov	r1, #PAGE_SZ/32
 	mov	r2, #0
 	mov	r3, #0
@@ -74,10 +99,10 @@ ENTRY(xscale_mc_clear_user_page)
 	strd	r2, [r0], #8
 	strd	r2, [r0], #8
 	mcr	p15, 0, ip, c7, c10, 1		@ clean D line
-	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line
 	subs	r1, r1, #1
+	mcr	p15, 0, ip, c7, c6, 1		@ invalidate D line
 	bne	1b
-	ldr	pc, [sp], #4
+	mov	pc, lr
 
 	__INIT
 

drivers/mtd/maps/sa1100-flash.c

@@ -174,9 +174,15 @@ static struct mtd_partition assabet5_partitions[] = {
 
 #ifdef CONFIG_SA1100_BADGE4
 /*
- * 1 x Intel 28F320C3BA100 Advanced+ Boot Block Flash (32 Mi bit)
+ * 1 x Intel 28F320C3 Advanced+ Boot Block Flash (32 Mi bit)
  *   Eight 4 KiW Parameter Bottom Blocks (64 KiB)
  *   Sixty-three 32 KiW Main Blocks (4032 Ki b)
+ *
+ * <or>
+ *
+ * 1 x Intel 28F640C3 Advanced+ Boot Block Flash (64 Mi bit)
+ *   Eight 4 KiW Parameter Bottom Blocks (64 KiB)
+ *   One-hundred-twenty-seven 32 KiW Main Blocks (8128 Ki b)
  */
 static struct mtd_partition badge4_partitions[] = {
 	{
@@ -187,10 +193,6 @@ static struct mtd_partition badge4_partitions[] = {
 		.name		= "params",
 		.offset		= MTDPART_OFS_APPEND,
 		.size		= 0x00006000
-	}, {
-		.name		= "kernel",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= 0x00100000
 	}, {
 		.name		= "root",
 		.offset		= MTDPART_OFS_APPEND,
@@ -1087,8 +1089,10 @@ static void __exit sa1100_destroy_mtd(struct sa_info *sa, struct mtd_info *mtd)
 
 	del_mtd_partitions(mtd);
 
+#ifdef CONFIG_MTD_CONCAT
 	if (mtd != sa[0].mtd)
 		mtd_concat_destroy(mtd);
+#endif
 
 	for (i = NR_SUBMTD; i >= 0; i--) {
 		if (sa[i].mtd)
@@ -1119,7 +1123,7 @@ static int __init sa1100_locate_flash(void)
 	}
 	if (machine_is_badge4()) {
 		info[0].base = SA1100_CS0_PHYS;
-		info[0].size = SZ_4M;
+		info[0].size = SZ_64M;
 		nr = 1;
 	}
 	if (machine_is_cerf()) {

drivers/pcmcia/sa1111_generic.h

@@ -7,6 +7,7 @@ extern int sa1111_pcmcia_configure_socket(struct sa1100_pcmcia_socket *, const s
 extern void sa1111_pcmcia_socket_init(struct sa1100_pcmcia_socket *);
 extern void sa1111_pcmcia_socket_suspend(struct sa1100_pcmcia_socket *);
 
+extern int pcmcia_badge4_init(struct device *);
 extern int pcmcia_jornada720_init(struct device *);
 extern int pcmcia_neponset_init(struct device *);
 

include/asm-arm/arch-iop310/ide.h → include/asm-arm/arch-iop3xx/ide.h

 /*
- * include/asm-arm/arch-iop310/ide.h
+ * include/asm-arm/arch-iop3xx/ide.h
  *
  * Generic IDE functions for IOP310 systems
  *

include/asm-arm/arch-iop310/io.h → include/asm-arm/arch-iop3xx/io.h

 /*
- * linux/include/asm-arm/arch-iop310/io.h
+ * linux/include/asm-arm/arch-iop3xx/io.h
  *
  *  Copyright (C) 2001  MontaVista Software, Inc.
  *

include/asm-arm/arch-iop310/iop310.h → include/asm-arm/arch-iop3xx/iop310.h

 /*
- * linux/include/asm/arch-iop310/iop310.h
+ * linux/include/asm/arch-iop3xx/iop310.h
  *
  * Intel IOP310 Compainion Chip definitions
  *

include/asm-arm/arch-iop310/irqs.h → include/asm-arm/arch-iop3xx/irqs.h

 /*
- * linux/include/asm-arm/arch-iop310/irqs.h
+ * linux/include/asm-arm/arch-iop3xx/irqs.h
  *
  * Author:	Nicolas Pitre
  * Copyright:	(C) 2001 MontaVista Software Inc.

include/asm-arm/arch-iop310/serial.h → include/asm-arm/arch-iop3xx/serial.h

 /*
- * include/asm-arm/arch-iop310/serial.h
+ * include/asm-arm/arch-iop3xx/serial.h
  */
 #include <linux/config.h>
 

include/asm-arm/arch-iop310/vmalloc.h → include/asm-arm/arch-iop3xx/vmalloc.h

 /*
- * linux/include/asm-arm/arch-iop310/vmalloc.h
+ * linux/include/asm-arm/arch-iop3xx/vmalloc.h
  */
 
 /*

include/asm-arm/assembler.h

@@ -26,3 +26,13 @@
 #define push            lsr
 #define byte(x)         ((3-x)*8)
 #endif
+
+/*
+ * Data preload for architectures that support it
+ */
+#if __LINUX_ARM_ARCH__ >= 5
+#define PLD(code...)	code
+#else
+#define PLD(code...)
+#endif
+

include/asm-arm/hardware/sa1111.h

@@ -553,6 +553,7 @@ struct sa1111_dev {
 	void		*mapbase;
 	unsigned int	skpcr_mask;
 	unsigned int	irq[6];
+	u64		dma_mask;
 };
 
 #define SA1111_DEV(_d)	container_of((_d), struct sa1111_dev, dev)