clk: pistachio: Add sanity checks on PLL configuration
When setting the PLL rates, check that: - VCO is within range - PFD is within range - PLL is disabled when postdiv is changed - postdiv2 <= postdiv1 Reviewed-by:Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Kevin Cernekee <cernekee@chromium.org> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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