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Commit 188bdf72 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/adsp' and 'asoc/topic/amd' into asoc-next

parents 551e13a4 83a40ce9 7cb1dc81
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include/sound/designware_i2s.h
View file @ 188bdf72
......@@ -46,6 +46,7 @@ struct i2s_platform_data {
u32 snd_rates;
#define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
#define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
unsigned int quirks;
unsigned int i2s_reg_comp1;
unsigned int i2s_reg_comp2;
......
sound/soc/Kconfig
View file @ 188bdf72
......@@ -38,6 +38,7 @@ config SND_SOC_TOPOLOGY
# All the supported SoCs
source "sound/soc/adi/Kconfig"
source "sound/soc/amd/Kconfig"
source "sound/soc/atmel/Kconfig"
source "sound/soc/au1x/Kconfig"
source "sound/soc/bcm/Kconfig"
......
sound/soc/Makefile
View file @ 188bdf72
......@@ -18,6 +18,7 @@ obj-$(CONFIG_SND_SOC) += snd-soc-core.o
obj-$(CONFIG_SND_SOC) += codecs/
obj-$(CONFIG_SND_SOC) += generic/
obj-$(CONFIG_SND_SOC) += adi/
obj-$(CONFIG_SND_SOC) += amd/
obj-$(CONFIG_SND_SOC) += atmel/
obj-$(CONFIG_SND_SOC) += au1x/
obj-$(CONFIG_SND_SOC) += bcm/
......
sound/soc/amd/Kconfig 0 → 100644
View file @ 188bdf72
config SND_SOC_AMD_ACP
tristate "AMD Audio Coprocessor support"
help
This option enables ACP DMA support on AMD platform.
sound/soc/amd/Makefile 0 → 100644
View file @ 188bdf72
snd-soc-acp-pcm-objs := acp-pcm-dma.o
obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o
sound/soc/amd/acp-pcm-dma.c 0 → 100644
View file @ 188bdf72
/*
* AMD ALSA SoC PCM Driver for ACP 2.x
*
* Copyright 2014-2015 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "acp.h"
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 2
#define PLAYBACK_MAX_PERIOD_SIZE 16384
#define PLAYBACK_MIN_PERIOD_SIZE 1024
#define CAPTURE_MIN_NUM_PERIODS 2
#define CAPTURE_MAX_NUM_PERIODS 2
#define CAPTURE_MAX_PERIOD_SIZE 16384
#define CAPTURE_MIN_PERIOD_SIZE 1024
#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
#define MIN_BUFFER MAX_BUFFER
static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
struct audio_drv_data {
struct snd_pcm_substream *play_stream;
struct snd_pcm_substream *capture_stream;
void __iomem *acp_mmio;
};
static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
{
return readl(acp_mmio + (reg * 4));
}
static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
{
writel(val, acp_mmio + (reg * 4));
}
/* Configure a given dma channel parameters - enable/disble,
* number of descriptors, priority
*/
static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
u16 dscr_strt_idx, u16 num_dscrs,
enum acp_dma_priority_level priority_level)
{
u32 dma_ctrl;
/* disable the channel run field */
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/* program a DMA channel with first descriptor to be processed. */
acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
& dscr_strt_idx),
acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
/* program a DMA channel with the number of descriptors to be
* processed in the transfer
*/
acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
/* set DMA channel priority */
acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
}
/* Initialize a dma descriptor in SRAM based on descritor information passed */
static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
u16 descr_idx,
acp_dma_dscr_transfer_t *descr_info)
{
u32 sram_offset;
sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
/* program the source base address. */
acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* program the destination base address. */
acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* program the number of bytes to be transferred for this descriptor. */
acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
}
/* Initialize the DMA descriptor information for transfer between
* system memory <-> ACP SRAM
*/
static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
u32 size, int direction,
u32 pte_offset)
{
u16 i;
u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
dmadscr[i].xfer_val = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i;
dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS +
(size / 2) - (i * (size/2));
dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) + (i * (size/2));
dmadscr[i].xfer_val |=
(ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) |
(size / 2);
} else {
dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
(i * (size/2));
dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) +
(i * (size/2));
dmadscr[i].xfer_val |=
BIT(22) |
(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
(size / 2);
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
&dmadscr[i]);
}
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM,
PLAYBACK_START_DMA_DESCR_CH12,
NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL);
else
config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM,
CAPTURE_START_DMA_DESCR_CH14,
NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL);
}
/* Initialize the DMA descriptor information for transfer between
* ACP SRAM <-> I2S
*/
static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
u32 size, int direction)
{
u16 i;
u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
dmadscr[i].xfer_val = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i;
dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS +
(i * (size/2));
/* dmadscr[i].dest is unused by hardware. */
dmadscr[i].dest = 0;
dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) |
(size / 2);
} else {
dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i;
/* dmadscr[i].src is unused by hardware. */
dmadscr[i].src = 0;
dmadscr[i].dest = ACP_SHARED_RAM_BANK_5_ADDRESS +
(i * (size / 2));
dmadscr[i].xfer_val |= BIT(22) |
(FROM_ACP_I2S_1 << 16) | (size / 2);
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
&dmadscr[i]);
}
/* Configure the DMA channel with the above descriptore */
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
PLAYBACK_START_DMA_DESCR_CH13,
NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL);
else
config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
CAPTURE_START_DMA_DESCR_CH15,
NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL);
}
/* Create page table entries in ACP SRAM for the allocated memory */
static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
u16 num_of_pages, u32 pte_offset)
{
u16 page_idx;
u64 addr;
u32 low;
u32 high;
u32 offset;
offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
acp_reg_write((offset + (page_idx * 8)),
acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
addr = page_to_phys(pg);
low = lower_32_bits(addr);
high = upper_32_bits(addr);
acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* Load the High address of page int ACP SRAM through SRBM */
acp_reg_write((offset + (page_idx * 8) + 4),
acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
/* page enable in ACP */
high |= BIT(31);
acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* Move to next physically contiguos page */
pg++;
}
}
static void config_acp_dma(void __iomem *acp_mmio,
struct audio_substream_data *audio_config)
{
u32 pte_offset;
if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
pte_offset = ACP_PLAYBACK_PTE_OFFSET;
else
pte_offset = ACP_CAPTURE_PTE_OFFSET;
acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages,
pte_offset);
/* Configure System memory <-> ACP SRAM DMA descriptors */
set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,
audio_config->direction, pte_offset);
/* Configure ACP SRAM <-> I2S DMA descriptors */
set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size,
audio_config->direction);
}
/* Start a given DMA channel transfer */
static void acp_dma_start(void __iomem *acp_mmio,
u16 ch_num, bool is_circular)
{
u32 dma_ctrl;
/* read the dma control register and disable the channel run field */
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/* Invalidating the DAGB cache */
acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
/* configure the DMA channel and start the DMA transfer
* set dmachrun bit to start the transfer and enable the
* interrupt on completion of the dma transfer
*/
dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
switch (ch_num) {
case ACP_TO_I2S_DMA_CH_NUM:
case ACP_TO_SYSRAM_CH_NUM:
case I2S_TO_ACP_DMA_CH_NUM:
dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
break;
default:
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
break;
}
/* enable for ACP SRAM to/from I2S DMA channel */
if (is_circular == true)
dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
else
dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
}
/* Stop a given DMA channel transfer */
static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
{
u32 dma_ctrl;
u32 dma_ch_sts;
u32 count = ACP_DMA_RESET_TIME;
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/* clear the dma control register fields before writing zero
* in reset bit
*/
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
if (dma_ch_sts & BIT(ch_num)) {
/* set the reset bit for this channel to stop the dma
* transfer
*/
dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
}
/* check the channel status bit for some time and return the status */
while (true) {
dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
if (!(dma_ch_sts & BIT(ch_num))) {
/* clear the reset flag after successfully stopping
* the dma transfer and break from the loop
*/
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
+ ch_num);
break;
}
if (--count == 0) {
pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
return -ETIMEDOUT;
}
udelay(100);
}
return 0;
}
static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
bool power_on)
{
u32 val, req_reg, sts_reg, sts_reg_mask;
u32 loops = 1000;
if (bank < 32) {
req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
sts_reg_mask = 0xFFFFFFFF;
} else {
bank -= 32;
req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
sts_reg_mask = 0x0000FFFF;
}
val = acp_reg_read(acp_mmio, req_reg);
if (val & (1 << bank)) {
/* bank is in off state */
if (power_on == true)
/* request to on */
val &= ~(1 << bank);
else
/* request to off */
return;
} else {
/* bank is in on state */
if (power_on == false)
/* request to off */
val |= 1 << bank;
else
/* request to on */
return;
}
acp_reg_write(val, acp_mmio, req_reg);
while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
if (!loops--) {
pr_err("ACP SRAM bank %d state change failed\n", bank);
break;
}
cpu_relax();
}
}
/* Initialize and bring ACP hardware to default state. */
static int acp_init(void __iomem *acp_mmio)
{
u16 bank;
u32 val, count, sram_pte_offset;
/* Assert Soft reset of ACP */
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
val |= ACP_SOFT_RESET__SoftResetAud_MASK;
acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
/* Enable clock to ACP and wait until the clock is enabled */
val = acp_reg_read(acp_mmio, mmACP_CONTROL);
val = val | ACP_CONTROL__ClkEn_MASK;
acp_reg_write(val, acp_mmio, mmACP_CONTROL);
count = ACP_CLOCK_EN_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_STATUS);
if (val & (u32) 0x1)
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
/* Deassert the SOFT RESET flags */
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
/* initiailize Onion control DAGB register */
acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
mmACP_AXI2DAGB_ONION_CNTL);
/* initiailize Garlic control DAGB registers */
acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
mmACP_AXI2DAGB_GARLIC_CNTL);
sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
mmACP_DAGB_PAGE_SIZE_GRP_1);
acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
mmACP_DMA_DESC_BASE_ADDR);
/* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
/* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
* Now, turn off all of them. This can't be done in 'poweron' of
* ACP pm domain, as this requires ACP to be initialized.
*/
for (bank = 1; bank < 48; bank++)
acp_set_sram_bank_state(acp_mmio, bank, false);
return 0;
}
/* Deintialize ACP */
static int acp_deinit(void __iomem *acp_mmio)
{
u32 val;
u32 count;
/* Assert Soft reset of ACP */
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
val |= ACP_SOFT_RESET__SoftResetAud_MASK;
acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
/** Disable ACP clock */
val = acp_reg_read(acp_mmio, mmACP_CONTROL);
val &= ~ACP_CONTROL__ClkEn_MASK;
acp_reg_write(val, acp_mmio, mmACP_CONTROL);
count = ACP_CLOCK_EN_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_STATUS);
if (!(val & (u32) 0x1))
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
return 0;
}
/* ACP DMA irq handler routine for playback, capture usecases */
static irqreturn_t dma_irq_handler(int irq, void *arg)
{
u16 dscr_idx;
u32 intr_flag, ext_intr_status;
struct audio_drv_data *irq_data;
void __iomem *acp_mmio;
struct device *dev = arg;
bool valid_irq = false;
irq_data = dev_get_drvdata(dev);
acp_mmio = irq_data->acp_mmio;
ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
intr_flag = (((ext_intr_status &
ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
valid_irq = true;
if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) ==
PLAYBACK_START_DMA_DESCR_CH13)
dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
else
dscr_idx = PLAYBACK_END_DMA_DESCR_CH12;
config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx,
1, 0);
acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
snd_pcm_period_elapsed(irq_data->play_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
valid_irq = true;
if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) ==
CAPTURE_START_DMA_DESCR_CH15)
dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
else
dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
1, 0);
acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
valid_irq = true;
snd_pcm_period_elapsed(irq_data->capture_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if (valid_irq)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static int acp_dma_open(struct snd_pcm_substream *substream)
{
u16 bank;
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev);
struct audio_substream_data *adata =
kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
if (adata == NULL)
return -ENOMEM;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = acp_pcm_hardware_playback;
else
runtime->hw = acp_pcm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(prtd->platform->dev, "set integer constraint failed\n");
return ret;
}
adata->acp_mmio = intr_data->acp_mmio;
runtime->private_data = adata;
/* Enable ACP irq, when neither playback or capture streams are
* active by the time when a new stream is being opened.
* This enablement is not required for another stream, if current
* stream is not closed
*/
if (!intr_data->play_stream && !intr_data->capture_stream)
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
intr_data->play_stream = substream;
for (bank = 1; bank <= 4; bank++)
acp_set_sram_bank_state(intr_data->acp_mmio, bank,
true);
} else {
intr_data->capture_stream = substream;
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(intr_data->acp_mmio, bank,
true);
}
return 0;
}
static int acp_dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
int status;
uint64_t size;
struct snd_dma_buffer *dma_buffer;
struct page *pg;
struct snd_pcm_runtime *runtime;
struct audio_substream_data *rtd;
dma_buffer = &substream->dma_buffer;
runtime = substream->runtime;
rtd = runtime->private_data;
if (WARN_ON(!rtd))
return -EINVAL;
size = params_buffer_bytes(params);
status = snd_pcm_lib_malloc_pages(substream, size);
if (status < 0)
return status;
memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
pg = virt_to_page(substream->dma_buffer.area);
if (pg != NULL) {
acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
/* Save for runtime private data */
rtd->pg = pg;
rtd->order = get_order(size);
/* Fill the page table entries in ACP SRAM */
rtd->pg = pg;
rtd->size = size;
rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
rtd->direction = substream->stream;
config_acp_dma(rtd->acp_mmio, rtd);
status = 0;
} else {
status = -ENOMEM;
}
return status;
}
static int acp_dma_hw_free(struct snd_pcm_substream *substream)
{
return snd_pcm_lib_free_pages(substream);
}
static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
{
u16 dscr;
u32 mul, dma_config, period_bytes;
u32 pos = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
dscr = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CUR_DSCR_13);
if (dscr == PLAYBACK_START_DMA_DESCR_CH13)
mul = 0;
else
mul = 1;
pos = (mul * period_bytes);
} else {
dma_config = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CNTL_14);
if (dma_config != 0) {
dscr = acp_reg_read(rtd->acp_mmio,
mmACP_DMA_CUR_DSCR_14);
if (dscr == CAPTURE_START_DMA_DESCR_CH14)
mul = 1;
else
mul = 2;
pos = (mul * period_bytes);
}
if (pos >= (2 * period_bytes))
pos = 0;
}
return bytes_to_frames(runtime, pos);
}
static int acp_dma_mmap(struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
return snd_pcm_lib_default_mmap(substream, vma);
}
static int acp_dma_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
PLAYBACK_START_DMA_DESCR_CH12,
NUM_DSCRS_PER_CHANNEL, 0);
config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
PLAYBACK_START_DMA_DESCR_CH13,
NUM_DSCRS_PER_CHANNEL, 0);
/* Fill ACP SRAM (2 periods) with zeros from System RAM
* which is zero-ed in hw_params
*/
acp_dma_start(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
/* ACP SRAM (2 periods of buffer size) is intially filled with
* zeros. Before rendering starts, 2nd half of SRAM will be
* filled with valid audio data DMA'ed from first half of system
* RAM and 1st half of SRAM will be filled with Zeros. This is
* the initial scenario when redering starts from SRAM. Later
* on, 2nd half of system memory will be DMA'ed to 1st half of
* SRAM, 1st half of system memory will be DMA'ed to 2nd half of
* SRAM in ping-pong way till rendering stops.
*/
config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
PLAYBACK_START_DMA_DESCR_CH12,
1, 0);
} else {
config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM,
CAPTURE_START_DMA_DESCR_CH14,
NUM_DSCRS_PER_CHANNEL, 0);
config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
CAPTURE_START_DMA_DESCR_CH15,
NUM_DSCRS_PER_CHANNEL, 0);
}
return 0;
}
static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
{
int ret;
u32 loops = 1000;
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
struct audio_substream_data *rtd = runtime->private_data;
if (!rtd)
return -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
acp_dma_start(rtd->acp_mmio,
SYSRAM_TO_ACP_CH_NUM, false);
while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
BIT(SYSRAM_TO_ACP_CH_NUM)) {
if (!loops--) {
dev_err(prtd->platform->dev,
"acp dma start timeout\n");
return -ETIMEDOUT;
}
cpu_relax();
}
acp_dma_start(rtd->acp_mmio,
ACP_TO_I2S_DMA_CH_NUM, true);
} else {
acp_dma_start(rtd->acp_mmio,
I2S_TO_ACP_DMA_CH_NUM, true);
}
ret = 0;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
/* Need to stop only circular DMA channels :
* ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular
* channels will stopped automatically after its transfer
* completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = acp_dma_stop(rtd->acp_mmio,
ACP_TO_I2S_DMA_CH_NUM);
else
ret = acp_dma_stop(rtd->acp_mmio,
I2S_TO_ACP_DMA_CH_NUM);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
{
return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
SNDRV_DMA_TYPE_DEV,
NULL, MIN_BUFFER,
MAX_BUFFER);
}
static int acp_dma_close(struct snd_pcm_substream *substream)
{
u16 bank;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev);
kfree(rtd);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adata->play_stream = NULL;
for (bank = 1; bank <= 4; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
false);
} else {
adata->capture_stream = NULL;
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
false);
}
/* Disable ACP irq, when the current stream is being closed and
* another stream is also not active.
*/
if (!adata->play_stream && !adata->capture_stream)
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static struct snd_pcm_ops acp_dma_ops = {
.open = acp_dma_open,
.close = acp_dma_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = acp_dma_hw_params,
.hw_free = acp_dma_hw_free,
.trigger = acp_dma_trigger,
.pointer = acp_dma_pointer,
.mmap = acp_dma_mmap,
.prepare = acp_dma_prepare,
};
static struct snd_soc_platform_driver acp_asoc_platform = {
.ops = &acp_dma_ops,
.pcm_new = acp_dma_new,
};
static int acp_audio_probe(struct platform_device *pdev)
{
int status;
struct audio_drv_data *audio_drv_data;
struct resource *res;
audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
GFP_KERNEL);
if (audio_drv_data == NULL)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
/* The following members gets populated in device 'open'
* function. Till then interrupts are disabled in 'acp_init'
* and device doesn't generate any interrupts.
*/
audio_drv_data->play_stream = NULL;
audio_drv_data->capture_stream = NULL;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
return -ENODEV;
}
status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
0, "ACP_IRQ", &pdev->dev);
if (status) {
dev_err(&pdev->dev, "ACP IRQ request failed\n");
return status;
}
dev_set_drvdata(&pdev->dev, audio_drv_data);
/* Initialize the ACP */
acp_init(audio_drv_data->acp_mmio);
status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform);
if (status != 0) {
dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
return status;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return status;
}
static int acp_audio_remove(struct platform_device *pdev)
{
struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
acp_deinit(adata->acp_mmio);
snd_soc_unregister_platform(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static int acp_pcm_resume(struct device *dev)
{
u16 bank;
struct audio_drv_data *adata = dev_get_drvdata(dev);
acp_init(adata->acp_mmio);
if (adata->play_stream && adata->play_stream->runtime) {
for (bank = 1; bank <= 4; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
true);
config_acp_dma(adata->acp_mmio,
adata->play_stream->runtime->private_data);
}
if (adata->capture_stream && adata->capture_stream->runtime) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
true);
config_acp_dma(adata->acp_mmio,
adata->capture_stream->runtime->private_data);
}
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp_pcm_runtime_suspend(struct device *dev)
{
struct audio_drv_data *adata = dev_get_drvdata(dev);
acp_deinit(adata->acp_mmio);
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp_pcm_runtime_resume(struct device *dev)
{
struct audio_drv_data *adata = dev_get_drvdata(dev);
acp_init(adata->acp_mmio);
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static const struct dev_pm_ops acp_pm_ops = {
.resume = acp_pcm_resume,
.runtime_suspend = acp_pcm_runtime_suspend,
.runtime_resume = acp_pcm_runtime_resume,
};
static struct platform_driver acp_dma_driver = {
.probe = acp_audio_probe,
.remove = acp_audio_remove,
.driver = {
.name = "acp_audio_dma",
.pm = &acp_pm_ops,
},
};
module_platform_driver(acp_dma_driver);
MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
MODULE_DESCRIPTION("AMD ACP PCM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:acp-dma-audio");
sound/soc/amd/acp.h 0 → 100644
View file @ 188bdf72
#ifndef __ACP_HW_H
#define __ACP_HW_H
#include "include/acp_2_2_d.h"
#include "include/acp_2_2_sh_mask.h"
#define ACP_PAGE_SIZE_4K_ENABLE 0x02
#define ACP_PLAYBACK_PTE_OFFSET 10
#define ACP_CAPTURE_PTE_OFFSET 0
#define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
#define ACP_ONION_CNTL_DEFAULT 0x00000FB4
#define ACP_PHYSICAL_BASE 0x14000
/* Playback SRAM address (as a destination in dma descriptor) */
#define ACP_SHARED_RAM_BANK_1_ADDRESS 0x4002000
/* Capture SRAM address (as a source in dma descriptor) */
#define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000
#define ACP_DMA_RESET_TIME 10000
#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
#define ACP_DMA_COMPLETE_TIME_OUT_VALUE 0x000000FF
#define ACP_SRAM_BASE_ADDRESS 0x4000000
#define ACP_DAGB_GRP_SRAM_BASE_ADDRESS 0x4001000
#define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET 0x1000
#define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 0x00000000
#define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS 0x01800000
#define TO_ACP_I2S_1 0x2
#define TO_ACP_I2S_2 0x4
#define FROM_ACP_I2S_1 0xa
#define FROM_ACP_I2S_2 0xb
#define ACP_TILE_ON_MASK 0x03
#define ACP_TILE_OFF_MASK 0x02
#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
#define ACP_TILE_P1_MASK 0x3e
#define ACP_TILE_P2_MASK 0x3d
#define ACP_TILE_DSP0_MASK 0x3b
#define ACP_TILE_DSP1_MASK 0x37
#define ACP_TILE_DSP2_MASK 0x2f
/* Playback DMA channels */
#define SYSRAM_TO_ACP_CH_NUM 12
#define ACP_TO_I2S_DMA_CH_NUM 13
/* Capture DMA channels */
#define ACP_TO_SYSRAM_CH_NUM 14
#define I2S_TO_ACP_DMA_CH_NUM 15
#define NUM_DSCRS_PER_CHANNEL 2
#define PLAYBACK_START_DMA_DESCR_CH12 0
#define PLAYBACK_END_DMA_DESCR_CH12 1
#define PLAYBACK_START_DMA_DESCR_CH13 2
#define PLAYBACK_END_DMA_DESCR_CH13 3
#define CAPTURE_START_DMA_DESCR_CH14 4
#define CAPTURE_END_DMA_DESCR_CH14 5
#define CAPTURE_START_DMA_DESCR_CH15 6
#define CAPTURE_END_DMA_DESCR_CH15 7
enum acp_dma_priority_level {
/* 0x0 Specifies the DMA channel is given normal priority */
ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
/* 0x1 Specifies the DMA channel is given high priority */
ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
};
struct audio_substream_data {
struct page *pg;
unsigned int order;
u16 num_of_pages;
u16 direction;
uint64_t size;
void __iomem *acp_mmio;
};
enum {
ACP_TILE_P1 = 0,
ACP_TILE_P2,
ACP_TILE_DSP0,
ACP_TILE_DSP1,
ACP_TILE_DSP2,
};
enum {
ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0,
ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8,
ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF
};
typedef struct acp_dma_dscr_transfer {
/* Specifies the source memory location for the DMA data transfer. */
u32 src;
/* Specifies the destination memory location to where the data will
* be transferred.
*/
u32 dest;
/* Specifies the number of bytes need to be transferred
* from source to destination memory.Transfer direction & IOC enable
*/
u32 xfer_val;
/* Reserved for future use */
u32 reserved;
} acp_dma_dscr_transfer_t;
#endif /*__ACP_HW_H */
sound/soc/amd/include/acp_2_2_d.h 0 → 100644
View file @ 188bdf72
/*
* ACP_2_2 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef ACP_2_2_D_H
#define ACP_2_2_D_H
#define mmACP_DMA_CNTL_0 0x5000
#define mmACP_DMA_CNTL_1 0x5001
#define mmACP_DMA_CNTL_2 0x5002
#define mmACP_DMA_CNTL_3 0x5003
#define mmACP_DMA_CNTL_4 0x5004
#define mmACP_DMA_CNTL_5 0x5005
#define mmACP_DMA_CNTL_6 0x5006
#define mmACP_DMA_CNTL_7 0x5007
#define mmACP_DMA_CNTL_8 0x5008
#define mmACP_DMA_CNTL_9 0x5009
#define mmACP_DMA_CNTL_10 0x500a
#define mmACP_DMA_CNTL_11 0x500b
#define mmACP_DMA_CNTL_12 0x500c
#define mmACP_DMA_CNTL_13 0x500d
#define mmACP_DMA_CNTL_14 0x500e
#define mmACP_DMA_CNTL_15 0x500f
#define mmACP_DMA_DSCR_STRT_IDX_0 0x5010
#define mmACP_DMA_DSCR_STRT_IDX_1 0x5011
#define mmACP_DMA_DSCR_STRT_IDX_2 0x5012
#define mmACP_DMA_DSCR_STRT_IDX_3 0x5013
#define mmACP_DMA_DSCR_STRT_IDX_4 0x5014
#define mmACP_DMA_DSCR_STRT_IDX_5 0x5015
#define mmACP_DMA_DSCR_STRT_IDX_6 0x5016
#define mmACP_DMA_DSCR_STRT_IDX_7 0x5017
#define mmACP_DMA_DSCR_STRT_IDX_8 0x5018
#define mmACP_DMA_DSCR_STRT_IDX_9 0x5019
#define mmACP_DMA_DSCR_STRT_IDX_10 0x501a
#define mmACP_DMA_DSCR_STRT_IDX_11 0x501b
#define mmACP_DMA_DSCR_STRT_IDX_12 0x501c
#define mmACP_DMA_DSCR_STRT_IDX_13 0x501d
#define mmACP_DMA_DSCR_STRT_IDX_14 0x501e
#define mmACP_DMA_DSCR_STRT_IDX_15 0x501f
#define mmACP_DMA_DSCR_CNT_0 0x5020
#define mmACP_DMA_DSCR_CNT_1 0x5021
#define mmACP_DMA_DSCR_CNT_2 0x5022
#define mmACP_DMA_DSCR_CNT_3 0x5023
#define mmACP_DMA_DSCR_CNT_4 0x5024
#define mmACP_DMA_DSCR_CNT_5 0x5025
#define mmACP_DMA_DSCR_CNT_6 0x5026
#define mmACP_DMA_DSCR_CNT_7 0x5027
#define mmACP_DMA_DSCR_CNT_8 0x5028
#define mmACP_DMA_DSCR_CNT_9 0x5029
#define mmACP_DMA_DSCR_CNT_10 0x502a
#define mmACP_DMA_DSCR_CNT_11 0x502b
#define mmACP_DMA_DSCR_CNT_12 0x502c
#define mmACP_DMA_DSCR_CNT_13 0x502d
#define mmACP_DMA_DSCR_CNT_14 0x502e
#define mmACP_DMA_DSCR_CNT_15 0x502f
#define mmACP_DMA_PRIO_0 0x5030
#define mmACP_DMA_PRIO_1 0x5031
#define mmACP_DMA_PRIO_2 0x5032
#define mmACP_DMA_PRIO_3 0x5033
#define mmACP_DMA_PRIO_4 0x5034
#define mmACP_DMA_PRIO_5 0x5035
#define mmACP_DMA_PRIO_6 0x5036
#define mmACP_DMA_PRIO_7 0x5037
#define mmACP_DMA_PRIO_8 0x5038
#define mmACP_DMA_PRIO_9 0x5039
#define mmACP_DMA_PRIO_10 0x503a
#define mmACP_DMA_PRIO_11 0x503b
#define mmACP_DMA_PRIO_12 0x503c
#define mmACP_DMA_PRIO_13 0x503d
#define mmACP_DMA_PRIO_14 0x503e
#define mmACP_DMA_PRIO_15 0x503f
#define mmACP_DMA_CUR_DSCR_0 0x5040
#define mmACP_DMA_CUR_DSCR_1 0x5041
#define mmACP_DMA_CUR_DSCR_2 0x5042
#define mmACP_DMA_CUR_DSCR_3 0x5043
#define mmACP_DMA_CUR_DSCR_4 0x5044
#define mmACP_DMA_CUR_DSCR_5 0x5045
#define mmACP_DMA_CUR_DSCR_6 0x5046
#define mmACP_DMA_CUR_DSCR_7 0x5047
#define mmACP_DMA_CUR_DSCR_8 0x5048
#define mmACP_DMA_CUR_DSCR_9 0x5049
#define mmACP_DMA_CUR_DSCR_10 0x504a
#define mmACP_DMA_CUR_DSCR_11 0x504b
#define mmACP_DMA_CUR_DSCR_12 0x504c
#define mmACP_DMA_CUR_DSCR_13 0x504d
#define mmACP_DMA_CUR_DSCR_14 0x504e
#define mmACP_DMA_CUR_DSCR_15 0x504f
#define mmACP_DMA_CUR_TRANS_CNT_0 0x5050
#define mmACP_DMA_CUR_TRANS_CNT_1 0x5051
#define mmACP_DMA_CUR_TRANS_CNT_2 0x5052
#define mmACP_DMA_CUR_TRANS_CNT_3 0x5053
#define mmACP_DMA_CUR_TRANS_CNT_4 0x5054
#define mmACP_DMA_CUR_TRANS_CNT_5 0x5055
#define mmACP_DMA_CUR_TRANS_CNT_6 0x5056
#define mmACP_DMA_CUR_TRANS_CNT_7 0x5057
#define mmACP_DMA_CUR_TRANS_CNT_8 0x5058
#define mmACP_DMA_CUR_TRANS_CNT_9 0x5059
#define mmACP_DMA_CUR_TRANS_CNT_10 0x505a
#define mmACP_DMA_CUR_TRANS_CNT_11 0x505b
#define mmACP_DMA_CUR_TRANS_CNT_12 0x505c
#define mmACP_DMA_CUR_TRANS_CNT_13 0x505d
#define mmACP_DMA_CUR_TRANS_CNT_14 0x505e
#define mmACP_DMA_CUR_TRANS_CNT_15 0x505f
#define mmACP_DMA_ERR_STS_0 0x5060
#define mmACP_DMA_ERR_STS_1 0x5061
#define mmACP_DMA_ERR_STS_2 0x5062
#define mmACP_DMA_ERR_STS_3 0x5063
#define mmACP_DMA_ERR_STS_4 0x5064
#define mmACP_DMA_ERR_STS_5 0x5065
#define mmACP_DMA_ERR_STS_6 0x5066
#define mmACP_DMA_ERR_STS_7 0x5067
#define mmACP_DMA_ERR_STS_8 0x5068
#define mmACP_DMA_ERR_STS_9 0x5069
#define mmACP_DMA_ERR_STS_10 0x506a
#define mmACP_DMA_ERR_STS_11 0x506b
#define mmACP_DMA_ERR_STS_12 0x506c
#define mmACP_DMA_ERR_STS_13 0x506d
#define mmACP_DMA_ERR_STS_14 0x506e
#define mmACP_DMA_ERR_STS_15 0x506f
#define mmACP_DMA_DESC_BASE_ADDR 0x5070
#define mmACP_DMA_DESC_MAX_NUM_DSCR 0x5071
#define mmACP_DMA_CH_STS 0x5072
#define mmACP_DMA_CH_GROUP 0x5073
#define mmACP_DSP0_CACHE_OFFSET0 0x5078
#define mmACP_DSP0_CACHE_SIZE0 0x5079
#define mmACP_DSP0_CACHE_OFFSET1 0x507a
#define mmACP_DSP0_CACHE_SIZE1 0x507b
#define mmACP_DSP0_CACHE_OFFSET2 0x507c
#define mmACP_DSP0_CACHE_SIZE2 0x507d
#define mmACP_DSP0_CACHE_OFFSET3 0x507e
#define mmACP_DSP0_CACHE_SIZE3 0x507f
#define mmACP_DSP0_CACHE_OFFSET4 0x5080
#define mmACP_DSP0_CACHE_SIZE4 0x5081
#define mmACP_DSP0_CACHE_OFFSET5 0x5082
#define mmACP_DSP0_CACHE_SIZE5 0x5083
#define mmACP_DSP0_CACHE_OFFSET6 0x5084
#define mmACP_DSP0_CACHE_SIZE6 0x5085
#define mmACP_DSP0_CACHE_OFFSET7 0x5086
#define mmACP_DSP0_CACHE_SIZE7 0x5087
#define mmACP_DSP0_CACHE_OFFSET8 0x5088
#define mmACP_DSP0_CACHE_SIZE8 0x5089
#define mmACP_DSP0_NONCACHE_OFFSET0 0x508a
#define mmACP_DSP0_NONCACHE_SIZE0 0x508b
#define mmACP_DSP0_NONCACHE_OFFSET1 0x508c
#define mmACP_DSP0_NONCACHE_SIZE1 0x508d
#define mmACP_DSP0_DEBUG_PC 0x508e
#define mmACP_DSP0_NMI_SEL 0x508f
#define mmACP_DSP0_CLKRST_CNTL 0x5090
#define mmACP_DSP0_RUNSTALL 0x5091
#define mmACP_DSP0_OCD_HALT_ON_RST 0x5092
#define mmACP_DSP0_WAIT_MODE 0x5093
#define mmACP_DSP0_VECT_SEL 0x5094
#define mmACP_DSP0_DEBUG_REG1 0x5095
#define mmACP_DSP0_DEBUG_REG2 0x5096
#define mmACP_DSP0_DEBUG_REG3 0x5097
#define mmACP_DSP1_CACHE_OFFSET0 0x509d
#define mmACP_DSP1_CACHE_SIZE0 0x509e
#define mmACP_DSP1_CACHE_OFFSET1 0x509f
#define mmACP_DSP1_CACHE_SIZE1 0x50a0
#define mmACP_DSP1_CACHE_OFFSET2 0x50a1
#define mmACP_DSP1_CACHE_SIZE2 0x50a2
#define mmACP_DSP1_CACHE_OFFSET3 0x50a3
#define mmACP_DSP1_CACHE_SIZE3 0x50a4
#define mmACP_DSP1_CACHE_OFFSET4 0x50a5
#define mmACP_DSP1_CACHE_SIZE4 0x50a6
#define mmACP_DSP1_CACHE_OFFSET5 0x50a7
#define mmACP_DSP1_CACHE_SIZE5 0x50a8
#define mmACP_DSP1_CACHE_OFFSET6 0x50a9
#define mmACP_DSP1_CACHE_SIZE6 0x50aa
#define mmACP_DSP1_CACHE_OFFSET7 0x50ab
#define mmACP_DSP1_CACHE_SIZE7 0x50ac
#define mmACP_DSP1_CACHE_OFFSET8 0x50ad
#define mmACP_DSP1_CACHE_SIZE8 0x50ae
#define mmACP_DSP1_NONCACHE_OFFSET0 0x50af
#define mmACP_DSP1_NONCACHE_SIZE0 0x50b0
#define mmACP_DSP1_NONCACHE_OFFSET1 0x50b1
#define mmACP_DSP1_NONCACHE_SIZE1 0x50b2
#define mmACP_DSP1_DEBUG_PC 0x50b3
#define mmACP_DSP1_NMI_SEL 0x50b4
#define mmACP_DSP1_CLKRST_CNTL 0x50b5
#define mmACP_DSP1_RUNSTALL 0x50b6
#define mmACP_DSP1_OCD_HALT_ON_RST 0x50b7
#define mmACP_DSP1_WAIT_MODE 0x50b8
#define mmACP_DSP1_VECT_SEL 0x50b9
#define mmACP_DSP1_DEBUG_REG1 0x50ba
#define mmACP_DSP1_DEBUG_REG2 0x50bb
#define mmACP_DSP1_DEBUG_REG3 0x50bc
#define mmACP_DSP2_CACHE_OFFSET0 0x50c2
#define mmACP_DSP2_CACHE_SIZE0 0x50c3
#define mmACP_DSP2_CACHE_OFFSET1 0x50c4
#define mmACP_DSP2_CACHE_SIZE1 0x50c5
#define mmACP_DSP2_CACHE_OFFSET2 0x50c6
#define mmACP_DSP2_CACHE_SIZE2 0x50c7
#define mmACP_DSP2_CACHE_OFFSET3 0x50c8
#define mmACP_DSP2_CACHE_SIZE3 0x50c9
#define mmACP_DSP2_CACHE_OFFSET4 0x50ca
#define mmACP_DSP2_CACHE_SIZE4 0x50cb
#define mmACP_DSP2_CACHE_OFFSET5 0x50cc
#define mmACP_DSP2_CACHE_SIZE5 0x50cd
#define mmACP_DSP2_CACHE_OFFSET6 0x50ce
#define mmACP_DSP2_CACHE_SIZE6 0x50cf
#define mmACP_DSP2_CACHE_OFFSET7 0x50d0
#define mmACP_DSP2_CACHE_SIZE7 0x50d1
#define mmACP_DSP2_CACHE_OFFSET8 0x50d2
#define mmACP_DSP2_CACHE_SIZE8 0x50d3
#define mmACP_DSP2_NONCACHE_OFFSET0 0x50d4
#define mmACP_DSP2_NONCACHE_SIZE0 0x50d5
#define mmACP_DSP2_NONCACHE_OFFSET1 0x50d6
#define mmACP_DSP2_NONCACHE_SIZE1 0x50d7
#define mmACP_DSP2_DEBUG_PC 0x50d8
#define mmACP_DSP2_NMI_SEL 0x50d9
#define mmACP_DSP2_CLKRST_CNTL 0x50da
#define mmACP_DSP2_RUNSTALL 0x50db
#define mmACP_DSP2_OCD_HALT_ON_RST 0x50dc
#define mmACP_DSP2_WAIT_MODE 0x50dd
#define mmACP_DSP2_VECT_SEL 0x50de
#define mmACP_DSP2_DEBUG_REG1 0x50df
#define mmACP_DSP2_DEBUG_REG2 0x50e0
#define mmACP_DSP2_DEBUG_REG3 0x50e1
#define mmACP_AXI2DAGB_ONION_CNTL 0x50e7
#define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR 0x50e8
#define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD 0x50e9
#define mmACP_DAGB_Onion_TransPerf_Counter_Control 0x50ea
#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current 0x50eb
#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak 0x50ec
#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current 0x50ed
#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak 0x50ee
#define mmACP_AXI2DAGB_GARLIC_CNTL 0x50f3
#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR 0x50f4
#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD 0x50f5
#define mmACP_DAGB_Garlic_TransPerf_Counter_Control 0x50f6
#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current 0x50f7
#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak 0x50f8
#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current 0x50f9
#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak 0x50fa
#define mmACP_DAGB_PAGE_SIZE_GRP_1 0x50ff
#define mmACP_DAGB_BASE_ADDR_GRP_1 0x5100
#define mmACP_DAGB_PAGE_SIZE_GRP_2 0x5101
#define mmACP_DAGB_BASE_ADDR_GRP_2 0x5102
#define mmACP_DAGB_PAGE_SIZE_GRP_3 0x5103
#define mmACP_DAGB_BASE_ADDR_GRP_3 0x5104
#define mmACP_DAGB_PAGE_SIZE_GRP_4 0x5105
#define mmACP_DAGB_BASE_ADDR_GRP_4 0x5106
#define mmACP_DAGB_PAGE_SIZE_GRP_5 0x5107
#define mmACP_DAGB_BASE_ADDR_GRP_5 0x5108
#define mmACP_DAGB_PAGE_SIZE_GRP_6 0x5109
#define mmACP_DAGB_BASE_ADDR_GRP_6 0x510a
#define mmACP_DAGB_PAGE_SIZE_GRP_7 0x510b
#define mmACP_DAGB_BASE_ADDR_GRP_7 0x510c
#define mmACP_DAGB_PAGE_SIZE_GRP_8 0x510d
#define mmACP_DAGB_BASE_ADDR_GRP_8 0x510e
#define mmACP_DAGB_ATU_CTRL 0x510f
#define mmACP_CONTROL 0x5131
#define mmACP_STATUS 0x5133
#define mmACP_SOFT_RESET 0x5134
#define mmACP_PwrMgmt_CNTL 0x5135
#define mmACP_CAC_INDICATOR_CONTROL 0x5136
#define mmACP_SMU_MAILBOX 0x5137
#define mmACP_FUTURE_REG_SCLK_0 0x5138
#define mmACP_FUTURE_REG_SCLK_1 0x5139
#define mmACP_FUTURE_REG_SCLK_2 0x513a
#define mmACP_FUTURE_REG_SCLK_3 0x513b
#define mmACP_FUTURE_REG_SCLK_4 0x513c
#define mmACP_DAGB_DEBUG_CNT_ENABLE 0x513d
#define mmACP_DAGBG_WR_ASK_CNT 0x513e
#define mmACP_DAGBG_WR_GO_CNT 0x513f
#define mmACP_DAGBG_WR_EXP_RESP_CNT 0x5140
#define mmACP_DAGBG_WR_ACTUAL_RESP_CNT 0x5141
#define mmACP_DAGBG_RD_ASK_CNT 0x5142
#define mmACP_DAGBG_RD_GO_CNT 0x5143
#define mmACP_DAGBG_RD_EXP_RESP_CNT 0x5144
#define mmACP_DAGBG_RD_ACTUAL_RESP_CNT 0x5145
#define mmACP_DAGBO_WR_ASK_CNT 0x5146
#define mmACP_DAGBO_WR_GO_CNT 0x5147
#define mmACP_DAGBO_WR_EXP_RESP_CNT 0x5148
#define mmACP_DAGBO_WR_ACTUAL_RESP_CNT 0x5149
#define mmACP_DAGBO_RD_ASK_CNT 0x514a
#define mmACP_DAGBO_RD_GO_CNT 0x514b
#define mmACP_DAGBO_RD_EXP_RESP_CNT 0x514c
#define mmACP_DAGBO_RD_ACTUAL_RESP_CNT 0x514d
#define mmACP_BRB_CONTROL 0x5156
#define mmACP_EXTERNAL_INTR_ENB 0x5157
#define mmACP_EXTERNAL_INTR_CNTL 0x5158
#define mmACP_ERROR_SOURCE_STS 0x5159
#define mmACP_DSP_SW_INTR_TRIG 0x515a
#define mmACP_DSP_SW_INTR_CNTL 0x515b
#define mmACP_DAGBG_TIMEOUT_CNTL 0x515c
#define mmACP_DAGBO_TIMEOUT_CNTL 0x515d
#define mmACP_EXTERNAL_INTR_STAT 0x515e
#define mmACP_DSP_SW_INTR_STAT 0x515f
#define mmACP_DSP0_INTR_CNTL 0x5160
#define mmACP_DSP0_INTR_STAT 0x5161
#define mmACP_DSP0_TIMEOUT_CNTL 0x5162
#define mmACP_DSP1_INTR_CNTL 0x5163
#define mmACP_DSP1_INTR_STAT 0x5164
#define mmACP_DSP1_TIMEOUT_CNTL 0x5165
#define mmACP_DSP2_INTR_CNTL 0x5166
#define mmACP_DSP2_INTR_STAT 0x5167
#define mmACP_DSP2_TIMEOUT_CNTL 0x5168
#define mmACP_DSP0_EXT_TIMER_CNTL 0x5169
#define mmACP_DSP1_EXT_TIMER_CNTL 0x516a
#define mmACP_DSP2_EXT_TIMER_CNTL 0x516b
#define mmACP_AXI2DAGB_SEM_0 0x516c
#define mmACP_AXI2DAGB_SEM_1 0x516d
#define mmACP_AXI2DAGB_SEM_2 0x516e
#define mmACP_AXI2DAGB_SEM_3 0x516f
#define mmACP_AXI2DAGB_SEM_4 0x5170
#define mmACP_AXI2DAGB_SEM_5 0x5171
#define mmACP_AXI2DAGB_SEM_6 0x5172
#define mmACP_AXI2DAGB_SEM_7 0x5173
#define mmACP_AXI2DAGB_SEM_8 0x5174
#define mmACP_AXI2DAGB_SEM_9 0x5175
#define mmACP_AXI2DAGB_SEM_10 0x5176
#define mmACP_AXI2DAGB_SEM_11 0x5177
#define mmACP_AXI2DAGB_SEM_12 0x5178
#define mmACP_AXI2DAGB_SEM_13 0x5179
#define mmACP_AXI2DAGB_SEM_14 0x517a
#define mmACP_AXI2DAGB_SEM_15 0x517b
#define mmACP_AXI2DAGB_SEM_16 0x517c
#define mmACP_AXI2DAGB_SEM_17 0x517d
#define mmACP_AXI2DAGB_SEM_18 0x517e
#define mmACP_AXI2DAGB_SEM_19 0x517f
#define mmACP_AXI2DAGB_SEM_20 0x5180
#define mmACP_AXI2DAGB_SEM_21 0x5181
#define mmACP_AXI2DAGB_SEM_22 0x5182
#define mmACP_AXI2DAGB_SEM_23 0x5183
#define mmACP_AXI2DAGB_SEM_24 0x5184
#define mmACP_AXI2DAGB_SEM_25 0x5185
#define mmACP_AXI2DAGB_SEM_26 0x5186
#define mmACP_AXI2DAGB_SEM_27 0x5187
#define mmACP_AXI2DAGB_SEM_28 0x5188
#define mmACP_AXI2DAGB_SEM_29 0x5189
#define mmACP_AXI2DAGB_SEM_30 0x518a
#define mmACP_AXI2DAGB_SEM_31 0x518b
#define mmACP_AXI2DAGB_SEM_32 0x518c
#define mmACP_AXI2DAGB_SEM_33 0x518d
#define mmACP_AXI2DAGB_SEM_34 0x518e
#define mmACP_AXI2DAGB_SEM_35 0x518f
#define mmACP_AXI2DAGB_SEM_36 0x5190
#define mmACP_AXI2DAGB_SEM_37 0x5191
#define mmACP_AXI2DAGB_SEM_38 0x5192
#define mmACP_AXI2DAGB_SEM_39 0x5193
#define mmACP_AXI2DAGB_SEM_40 0x5194
#define mmACP_AXI2DAGB_SEM_41 0x5195
#define mmACP_AXI2DAGB_SEM_42 0x5196
#define mmACP_AXI2DAGB_SEM_43 0x5197
#define mmACP_AXI2DAGB_SEM_44 0x5198
#define mmACP_AXI2DAGB_SEM_45 0x5199
#define mmACP_AXI2DAGB_SEM_46 0x519a
#define mmACP_AXI2DAGB_SEM_47 0x519b
#define mmACP_SRBM_Client_Base_Addr 0x519c
#define mmACP_SRBM_Client_RDDATA 0x519d
#define mmACP_SRBM_Cycle_Sts 0x519e
#define mmACP_SRBM_Targ_Idx_Addr 0x519f
#define mmACP_SRBM_Targ_Idx_Data 0x51a0
#define mmACP_SEMA_ADDR_LOW 0x51a1
#define mmACP_SEMA_ADDR_HIGH 0x51a2
#define mmACP_SEMA_CMD 0x51a3
#define mmACP_SEMA_STS 0x51a4
#define mmACP_SEMA_REQ 0x51a5
#define mmACP_FW_STATUS 0x51a6
#define mmACP_FUTURE_REG_ACLK_0 0x51a7
#define mmACP_FUTURE_REG_ACLK_1 0x51a8
#define mmACP_FUTURE_REG_ACLK_2 0x51a9
#define mmACP_FUTURE_REG_ACLK_3 0x51aa
#define mmACP_FUTURE_REG_ACLK_4 0x51ab
#define mmACP_TIMER 0x51ac
#define mmACP_TIMER_CNTL 0x51ad
#define mmACP_DSP0_TIMER 0x51ae
#define mmACP_DSP1_TIMER 0x51af
#define mmACP_DSP2_TIMER 0x51b0
#define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH 0x51b1
#define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW 0x51b2
#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH 0x51b3
#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW 0x51b4
#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH 0x51b5
#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW 0x51b6
#define mmACP_DSP0_CS_STATE 0x51b7
#define mmACP_DSP1_CS_STATE 0x51b8
#define mmACP_DSP2_CS_STATE 0x51b9
#define mmACP_SCRATCH_REG_BASE_ADDR 0x51ba
#define mmCC_ACP_EFUSE 0x51c8
#define mmACP_PGFSM_RETAIN_REG 0x51c9
#define mmACP_PGFSM_CONFIG_REG 0x51ca
#define mmACP_PGFSM_WRITE_REG 0x51cb
#define mmACP_PGFSM_READ_REG_0 0x51cc
#define mmACP_PGFSM_READ_REG_1 0x51cd
#define mmACP_PGFSM_READ_REG_2 0x51ce
#define mmACP_PGFSM_READ_REG_3 0x51cf
#define mmACP_PGFSM_READ_REG_4 0x51d0
#define mmACP_PGFSM_READ_REG_5 0x51d1
#define mmACP_IP_PGFSM_ENABLE 0x51d2
#define mmACP_I2S_PIN_CONFIG 0x51d3
#define mmACP_AZALIA_I2S_SELECT 0x51d4
#define mmACP_CHIP_PKG_FOR_PAD_ISOLATION 0x51d5
#define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL 0x51d6
#define mmACP_BT_UART_PAD_SEL 0x51d7
#define mmACP_SCRATCH_REG_0 0x52c0
#define mmACP_SCRATCH_REG_1 0x52c1
#define mmACP_SCRATCH_REG_2 0x52c2
#define mmACP_SCRATCH_REG_3 0x52c3
#define mmACP_SCRATCH_REG_4 0x52c4
#define mmACP_SCRATCH_REG_5 0x52c5
#define mmACP_SCRATCH_REG_6 0x52c6
#define mmACP_SCRATCH_REG_7 0x52c7
#define mmACP_SCRATCH_REG_8 0x52c8
#define mmACP_SCRATCH_REG_9 0x52c9
#define mmACP_SCRATCH_REG_10 0x52ca
#define mmACP_SCRATCH_REG_11 0x52cb
#define mmACP_SCRATCH_REG_12 0x52cc
#define mmACP_SCRATCH_REG_13 0x52cd
#define mmACP_SCRATCH_REG_14 0x52ce
#define mmACP_SCRATCH_REG_15 0x52cf
#define mmACP_SCRATCH_REG_16 0x52d0
#define mmACP_SCRATCH_REG_17 0x52d1
#define mmACP_SCRATCH_REG_18 0x52d2
#define mmACP_SCRATCH_REG_19 0x52d3
#define mmACP_SCRATCH_REG_20 0x52d4
#define mmACP_SCRATCH_REG_21 0x52d5
#define mmACP_SCRATCH_REG_22 0x52d6
#define mmACP_SCRATCH_REG_23 0x52d7
#define mmACP_SCRATCH_REG_24 0x52d8
#define mmACP_SCRATCH_REG_25 0x52d9
#define mmACP_SCRATCH_REG_26 0x52da
#define mmACP_SCRATCH_REG_27 0x52db
#define mmACP_SCRATCH_REG_28 0x52dc
#define mmACP_SCRATCH_REG_29 0x52dd
#define mmACP_SCRATCH_REG_30 0x52de
#define mmACP_SCRATCH_REG_31 0x52df
#define mmACP_SCRATCH_REG_32 0x52e0
#define mmACP_SCRATCH_REG_33 0x52e1
#define mmACP_SCRATCH_REG_34 0x52e2
#define mmACP_SCRATCH_REG_35 0x52e3
#define mmACP_SCRATCH_REG_36 0x52e4
#define mmACP_SCRATCH_REG_37 0x52e5
#define mmACP_SCRATCH_REG_38 0x52e6
#define mmACP_SCRATCH_REG_39 0x52e7
#define mmACP_SCRATCH_REG_40 0x52e8
#define mmACP_SCRATCH_REG_41 0x52e9
#define mmACP_SCRATCH_REG_42 0x52ea
#define mmACP_SCRATCH_REG_43 0x52eb
#define mmACP_SCRATCH_REG_44 0x52ec
#define mmACP_SCRATCH_REG_45 0x52ed
#define mmACP_SCRATCH_REG_46 0x52ee
#define mmACP_SCRATCH_REG_47 0x52ef
#define mmACP_VOICE_WAKEUP_ENABLE 0x51e8
#define mmACP_VOICE_WAKEUP_STATUS 0x51e9
#define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD 0x51ea
#define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD 0x51eb
#define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES 0x51ec
#define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS 0x51ed
#define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS 0x51ee
#define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION 0x51ef
#define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH 0x51f0
#define mmI2S_VOICE_WAKEUP_DATA_POINTER 0x51f1
#define mmI2S_VOICE_WAKEUP_AUTH_MATCH 0x51f2
#define mmI2S_VOICE_WAKEUP_8KB_WRAP 0x51f3
#define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH 0x51f4
#define mmACP_I2S_RECEIVED_BYTE_CNT_LOW 0x51f5
#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH 0x51f6
#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW 0x51f7
#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
#define mmACP_MEM_DEEP_SLEEP_REQ_LO 0x51fc
#define mmACP_MEM_DEEP_SLEEP_REQ_HI 0x51fd
#define mmACP_MEM_DEEP_SLEEP_STS_LO 0x51fe
#define mmACP_MEM_DEEP_SLEEP_STS_HI 0x51ff
#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO 0x5200
#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI 0x5201
#define mmACP_MEM_WAKEUP_FROM_SLEEP_LO 0x5202
#define mmACP_MEM_WAKEUP_FROM_SLEEP_HI 0x5203
#define mmACP_I2SSP_IER 0x5210
#define mmACP_I2SSP_IRER 0x5211
#define mmACP_I2SSP_ITER 0x5212
#define mmACP_I2SSP_CER 0x5213
#define mmACP_I2SSP_CCR 0x5214
#define mmACP_I2SSP_RXFFR 0x5215
#define mmACP_I2SSP_TXFFR 0x5216
#define mmACP_I2SSP_LRBR0 0x5218
#define mmACP_I2SSP_RRBR0 0x5219
#define mmACP_I2SSP_RER0 0x521a
#define mmACP_I2SSP_TER0 0x521b
#define mmACP_I2SSP_RCR0 0x521c
#define mmACP_I2SSP_TCR0 0x521d
#define mmACP_I2SSP_ISR0 0x521e
#define mmACP_I2SSP_IMR0 0x521f
#define mmACP_I2SSP_ROR0 0x5220
#define mmACP_I2SSP_TOR0 0x5221
#define mmACP_I2SSP_RFCR0 0x5222
#define mmACP_I2SSP_TFCR0 0x5223
#define mmACP_I2SSP_RFF0 0x5224
#define mmACP_I2SSP_TFF0 0x5225
#define mmACP_I2SSP_RXDMA 0x5226
#define mmACP_I2SSP_RRXDMA 0x5227
#define mmACP_I2SSP_TXDMA 0x5228
#define mmACP_I2SSP_RTXDMA 0x5229
#define mmACP_I2SSP_COMP_PARAM_2 0x522a
#define mmACP_I2SSP_COMP_PARAM_1 0x522b
#define mmACP_I2SSP_COMP_VERSION 0x522c
#define mmACP_I2SSP_COMP_TYPE 0x522d
#define mmACP_I2SMICSP_IER 0x522e
#define mmACP_I2SMICSP_IRER 0x522f
#define mmACP_I2SMICSP_ITER 0x5230
#define mmACP_I2SMICSP_CER 0x5231
#define mmACP_I2SMICSP_CCR 0x5232
#define mmACP_I2SMICSP_RXFFR 0x5233
#define mmACP_I2SMICSP_TXFFR 0x5234
#define mmACP_I2SMICSP_LRBR0 0x5236
#define mmACP_I2SMICSP_RRBR0 0x5237
#define mmACP_I2SMICSP_RER0 0x5238
#define mmACP_I2SMICSP_TER0 0x5239
#define mmACP_I2SMICSP_RCR0 0x523a
#define mmACP_I2SMICSP_TCR0 0x523b
#define mmACP_I2SMICSP_ISR0 0x523c
#define mmACP_I2SMICSP_IMR0 0x523d
#define mmACP_I2SMICSP_ROR0 0x523e
#define mmACP_I2SMICSP_TOR0 0x523f
#define mmACP_I2SMICSP_RFCR0 0x5240
#define mmACP_I2SMICSP_TFCR0 0x5241
#define mmACP_I2SMICSP_RFF0 0x5242
#define mmACP_I2SMICSP_TFF0 0x5243
#define mmACP_I2SMICSP_LRBR1 0x5246
#define mmACP_I2SMICSP_RRBR1 0x5247
#define mmACP_I2SMICSP_RER1 0x5248
#define mmACP_I2SMICSP_TER1 0x5249
#define mmACP_I2SMICSP_RCR1 0x524a
#define mmACP_I2SMICSP_TCR1 0x524b
#define mmACP_I2SMICSP_ISR1 0x524c
#define mmACP_I2SMICSP_IMR1 0x524d
#define mmACP_I2SMICSP_ROR1 0x524e
#define mmACP_I2SMICSP_TOR1 0x524f
#define mmACP_I2SMICSP_RFCR1 0x5250
#define mmACP_I2SMICSP_TFCR1 0x5251
#define mmACP_I2SMICSP_RFF1 0x5252
#define mmACP_I2SMICSP_TFF1 0x5253
#define mmACP_I2SMICSP_RXDMA 0x5254
#define mmACP_I2SMICSP_RRXDMA 0x5255
#define mmACP_I2SMICSP_TXDMA 0x5256
#define mmACP_I2SMICSP_RTXDMA 0x5257
#define mmACP_I2SMICSP_COMP_PARAM_2 0x5258
#define mmACP_I2SMICSP_COMP_PARAM_1 0x5259
#define mmACP_I2SMICSP_COMP_VERSION 0x525a
#define mmACP_I2SMICSP_COMP_TYPE 0x525b
#define mmACP_I2SBT_IER 0x525c
#define mmACP_I2SBT_IRER 0x525d
#define mmACP_I2SBT_ITER 0x525e
#define mmACP_I2SBT_CER 0x525f
#define mmACP_I2SBT_CCR 0x5260
#define mmACP_I2SBT_RXFFR 0x5261
#define mmACP_I2SBT_TXFFR 0x5262
#define mmACP_I2SBT_LRBR0 0x5264
#define mmACP_I2SBT_RRBR0 0x5265
#define mmACP_I2SBT_RER0 0x5266
#define mmACP_I2SBT_TER0 0x5267
#define mmACP_I2SBT_RCR0 0x5268
#define mmACP_I2SBT_TCR0 0x5269
#define mmACP_I2SBT_ISR0 0x526a
#define mmACP_I2SBT_IMR0 0x526b
#define mmACP_I2SBT_ROR0 0x526c
#define mmACP_I2SBT_TOR0 0x526d
#define mmACP_I2SBT_RFCR0 0x526e
#define mmACP_I2SBT_TFCR0 0x526f
#define mmACP_I2SBT_RFF0 0x5270
#define mmACP_I2SBT_TFF0 0x5271
#define mmACP_I2SBT_LRBR1 0x5274
#define mmACP_I2SBT_RRBR1 0x5275
#define mmACP_I2SBT_RER1 0x5276
#define mmACP_I2SBT_TER1 0x5277
#define mmACP_I2SBT_RCR1 0x5278
#define mmACP_I2SBT_TCR1 0x5279
#define mmACP_I2SBT_ISR1 0x527a
#define mmACP_I2SBT_IMR1 0x527b
#define mmACP_I2SBT_ROR1 0x527c
#define mmACP_I2SBT_TOR1 0x527d
#define mmACP_I2SBT_RFCR1 0x527e
#define mmACP_I2SBT_TFCR1 0x527f
#define mmACP_I2SBT_RFF1 0x5280
#define mmACP_I2SBT_TFF1 0x5281
#define mmACP_I2SBT_RXDMA 0x5282
#define mmACP_I2SBT_RRXDMA 0x5283
#define mmACP_I2SBT_TXDMA 0x5284
#define mmACP_I2SBT_RTXDMA 0x5285
#define mmACP_I2SBT_COMP_PARAM_2 0x5286
#define mmACP_I2SBT_COMP_PARAM_1 0x5287
#define mmACP_I2SBT_COMP_VERSION 0x5288
#define mmACP_I2SBT_COMP_TYPE 0x5289
#endif /* ACP_2_2_D_H */
sound/soc/amd/include/acp_2_2_enum.h 0 → 100644
View file @ 188bdf72
/*
* ACP_2_2 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef ACP_2_2_ENUM_H
#define ACP_2_2_ENUM_H
typedef enum DebugBlockId {
DBG_BLOCK_ID_RESERVED = 0x0,
DBG_BLOCK_ID_DBG = 0x1,
DBG_BLOCK_ID_VMC = 0x2,
DBG_BLOCK_ID_PDMA = 0x3,
DBG_BLOCK_ID_CG = 0x4,
DBG_BLOCK_ID_SRBM = 0x5,
DBG_BLOCK_ID_GRBM = 0x6,
DBG_BLOCK_ID_RLC = 0x7,
DBG_BLOCK_ID_CSC = 0x8,
DBG_BLOCK_ID_SEM = 0x9,
DBG_BLOCK_ID_IH = 0xa,
DBG_BLOCK_ID_SC = 0xb,
DBG_BLOCK_ID_SQ = 0xc,
DBG_BLOCK_ID_UVDU = 0xd,
DBG_BLOCK_ID_SQA = 0xe,
DBG_BLOCK_ID_SDMA0 = 0xf,
DBG_BLOCK_ID_SDMA1 = 0x10,
DBG_BLOCK_ID_SPIM = 0x11,
DBG_BLOCK_ID_GDS = 0x12,
DBG_BLOCK_ID_VC0 = 0x13,
DBG_BLOCK_ID_VC1 = 0x14,
DBG_BLOCK_ID_PA0 = 0x15,
DBG_BLOCK_ID_PA1 = 0x16,
DBG_BLOCK_ID_CP0 = 0x17,
DBG_BLOCK_ID_CP1 = 0x18,
DBG_BLOCK_ID_CP2 = 0x19,
DBG_BLOCK_ID_XBR = 0x1a,
DBG_BLOCK_ID_UVDM = 0x1b,
DBG_BLOCK_ID_VGT0 = 0x1c,
DBG_BLOCK_ID_VGT1 = 0x1d,
DBG_BLOCK_ID_IA = 0x1e,
DBG_BLOCK_ID_SXM0 = 0x1f,
DBG_BLOCK_ID_SXM1 = 0x20,
DBG_BLOCK_ID_SCT0 = 0x21,
DBG_BLOCK_ID_SCT1 = 0x22,
DBG_BLOCK_ID_SPM0 = 0x23,
DBG_BLOCK_ID_SPM1 = 0x24,
DBG_BLOCK_ID_UNUSED0 = 0x25,
DBG_BLOCK_ID_UNUSED1 = 0x26,
DBG_BLOCK_ID_TCAA = 0x27,
DBG_BLOCK_ID_TCAB = 0x28,
DBG_BLOCK_ID_TCCA = 0x29,
DBG_BLOCK_ID_TCCB = 0x2a,
DBG_BLOCK_ID_MCC0 = 0x2b,
DBG_BLOCK_ID_MCC1 = 0x2c,
DBG_BLOCK_ID_MCC2 = 0x2d,
DBG_BLOCK_ID_MCC3 = 0x2e,
DBG_BLOCK_ID_SXS0 = 0x2f,
DBG_BLOCK_ID_SXS1 = 0x30,
DBG_BLOCK_ID_SXS2 = 0x31,
DBG_BLOCK_ID_SXS3 = 0x32,
DBG_BLOCK_ID_SXS4 = 0x33,
DBG_BLOCK_ID_SXS5 = 0x34,
DBG_BLOCK_ID_SXS6 = 0x35,
DBG_BLOCK_ID_SXS7 = 0x36,
DBG_BLOCK_ID_SXS8 = 0x37,
DBG_BLOCK_ID_SXS9 = 0x38,
DBG_BLOCK_ID_BCI0 = 0x39,
DBG_BLOCK_ID_BCI1 = 0x3a,
DBG_BLOCK_ID_BCI2 = 0x3b,
DBG_BLOCK_ID_BCI3 = 0x3c,
DBG_BLOCK_ID_MCB = 0x3d,
DBG_BLOCK_ID_UNUSED6 = 0x3e,
DBG_BLOCK_ID_SQA00 = 0x3f,
DBG_BLOCK_ID_SQA01 = 0x40,
DBG_BLOCK_ID_SQA02 = 0x41,
DBG_BLOCK_ID_SQA10 = 0x42,
DBG_BLOCK_ID_SQA11 = 0x43,
DBG_BLOCK_ID_SQA12 = 0x44,
DBG_BLOCK_ID_UNUSED7 = 0x45,
DBG_BLOCK_ID_UNUSED8 = 0x46,
DBG_BLOCK_ID_SQB00 = 0x47,
DBG_BLOCK_ID_SQB01 = 0x48,
DBG_BLOCK_ID_SQB10 = 0x49,
DBG_BLOCK_ID_SQB11 = 0x4a,
DBG_BLOCK_ID_SQ00 = 0x4b,
DBG_BLOCK_ID_SQ01 = 0x4c,
DBG_BLOCK_ID_SQ10 = 0x4d,
DBG_BLOCK_ID_SQ11 = 0x4e,
DBG_BLOCK_ID_CB00 = 0x4f,
DBG_BLOCK_ID_CB01 = 0x50,
DBG_BLOCK_ID_CB02 = 0x51,
DBG_BLOCK_ID_CB03 = 0x52,
DBG_BLOCK_ID_CB04 = 0x53,
DBG_BLOCK_ID_UNUSED9 = 0x54,
DBG_BLOCK_ID_UNUSED10 = 0x55,
DBG_BLOCK_ID_UNUSED11 = 0x56,
DBG_BLOCK_ID_CB10 = 0x57,
DBG_BLOCK_ID_CB11 = 0x58,
DBG_BLOCK_ID_CB12 = 0x59,
DBG_BLOCK_ID_CB13 = 0x5a,
DBG_BLOCK_ID_CB14 = 0x5b,
DBG_BLOCK_ID_UNUSED12 = 0x5c,
DBG_BLOCK_ID_UNUSED13 = 0x5d,
DBG_BLOCK_ID_UNUSED14 = 0x5e,
DBG_BLOCK_ID_TCP0 = 0x5f,
DBG_BLOCK_ID_TCP1 = 0x60,
DBG_BLOCK_ID_TCP2 = 0x61,
DBG_BLOCK_ID_TCP3 = 0x62,
DBG_BLOCK_ID_TCP4 = 0x63,
DBG_BLOCK_ID_TCP5 = 0x64,
DBG_BLOCK_ID_TCP6 = 0x65,
DBG_BLOCK_ID_TCP7 = 0x66,
DBG_BLOCK_ID_TCP8 = 0x67,
DBG_BLOCK_ID_TCP9 = 0x68,
DBG_BLOCK_ID_TCP10 = 0x69,
DBG_BLOCK_ID_TCP11 = 0x6a,
DBG_BLOCK_ID_TCP12 = 0x6b,
DBG_BLOCK_ID_TCP13 = 0x6c,
DBG_BLOCK_ID_TCP14 = 0x6d,
DBG_BLOCK_ID_TCP15 = 0x6e,
DBG_BLOCK_ID_TCP16 = 0x6f,
DBG_BLOCK_ID_TCP17 = 0x70,
DBG_BLOCK_ID_TCP18 = 0x71,
DBG_BLOCK_ID_TCP19 = 0x72,
DBG_BLOCK_ID_TCP20 = 0x73,
DBG_BLOCK_ID_TCP21 = 0x74,
DBG_BLOCK_ID_TCP22 = 0x75,
DBG_BLOCK_ID_TCP23 = 0x76,
DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
DBG_BLOCK_ID_DB00 = 0x7f,
DBG_BLOCK_ID_DB01 = 0x80,
DBG_BLOCK_ID_DB02 = 0x81,
DBG_BLOCK_ID_DB03 = 0x82,
DBG_BLOCK_ID_DB04 = 0x83,
DBG_BLOCK_ID_UNUSED15 = 0x84,
DBG_BLOCK_ID_UNUSED16 = 0x85,
DBG_BLOCK_ID_UNUSED17 = 0x86,
DBG_BLOCK_ID_DB10 = 0x87,
DBG_BLOCK_ID_DB11 = 0x88,
DBG_BLOCK_ID_DB12 = 0x89,
DBG_BLOCK_ID_DB13 = 0x8a,
DBG_BLOCK_ID_DB14 = 0x8b,
DBG_BLOCK_ID_UNUSED18 = 0x8c,
DBG_BLOCK_ID_UNUSED19 = 0x8d,
DBG_BLOCK_ID_UNUSED20 = 0x8e,
DBG_BLOCK_ID_TCC0 = 0x8f,
DBG_BLOCK_ID_TCC1 = 0x90,
DBG_BLOCK_ID_TCC2 = 0x91,
DBG_BLOCK_ID_TCC3 = 0x92,
DBG_BLOCK_ID_TCC4 = 0x93,
DBG_BLOCK_ID_TCC5 = 0x94,
DBG_BLOCK_ID_TCC6 = 0x95,
DBG_BLOCK_ID_TCC7 = 0x96,
DBG_BLOCK_ID_SPS00 = 0x97,
DBG_BLOCK_ID_SPS01 = 0x98,
DBG_BLOCK_ID_SPS02 = 0x99,
DBG_BLOCK_ID_SPS10 = 0x9a,
DBG_BLOCK_ID_SPS11 = 0x9b,
DBG_BLOCK_ID_SPS12 = 0x9c,
DBG_BLOCK_ID_UNUSED21 = 0x9d,
DBG_BLOCK_ID_UNUSED22 = 0x9e,
DBG_BLOCK_ID_TA00 = 0x9f,
DBG_BLOCK_ID_TA01 = 0xa0,
DBG_BLOCK_ID_TA02 = 0xa1,
DBG_BLOCK_ID_TA03 = 0xa2,
DBG_BLOCK_ID_TA04 = 0xa3,
DBG_BLOCK_ID_TA05 = 0xa4,
DBG_BLOCK_ID_TA06 = 0xa5,
DBG_BLOCK_ID_TA07 = 0xa6,
DBG_BLOCK_ID_TA08 = 0xa7,
DBG_BLOCK_ID_TA09 = 0xa8,
DBG_BLOCK_ID_TA0A = 0xa9,
DBG_BLOCK_ID_TA0B = 0xaa,
DBG_BLOCK_ID_UNUSED23 = 0xab,
DBG_BLOCK_ID_UNUSED24 = 0xac,
DBG_BLOCK_ID_UNUSED25 = 0xad,
DBG_BLOCK_ID_UNUSED26 = 0xae,
DBG_BLOCK_ID_TA10 = 0xaf,
DBG_BLOCK_ID_TA11 = 0xb0,
DBG_BLOCK_ID_TA12 = 0xb1,
DBG_BLOCK_ID_TA13 = 0xb2,
DBG_BLOCK_ID_TA14 = 0xb3,
DBG_BLOCK_ID_TA15 = 0xb4,
DBG_BLOCK_ID_TA16 = 0xb5,
DBG_BLOCK_ID_TA17 = 0xb6,
DBG_BLOCK_ID_TA18 = 0xb7,
DBG_BLOCK_ID_TA19 = 0xb8,
DBG_BLOCK_ID_TA1A = 0xb9,
DBG_BLOCK_ID_TA1B = 0xba,
DBG_BLOCK_ID_UNUSED27 = 0xbb,
DBG_BLOCK_ID_UNUSED28 = 0xbc,
DBG_BLOCK_ID_UNUSED29 = 0xbd,
DBG_BLOCK_ID_UNUSED30 = 0xbe,
DBG_BLOCK_ID_TD00 = 0xbf,
DBG_BLOCK_ID_TD01 = 0xc0,
DBG_BLOCK_ID_TD02 = 0xc1,
DBG_BLOCK_ID_TD03 = 0xc2,
DBG_BLOCK_ID_TD04 = 0xc3,
DBG_BLOCK_ID_TD05 = 0xc4,
DBG_BLOCK_ID_TD06 = 0xc5,
DBG_BLOCK_ID_TD07 = 0xc6,
DBG_BLOCK_ID_TD08 = 0xc7,
DBG_BLOCK_ID_TD09 = 0xc8,
DBG_BLOCK_ID_TD0A = 0xc9,
DBG_BLOCK_ID_TD0B = 0xca,
DBG_BLOCK_ID_UNUSED31 = 0xcb,
DBG_BLOCK_ID_UNUSED32 = 0xcc,
DBG_BLOCK_ID_UNUSED33 = 0xcd,
DBG_BLOCK_ID_UNUSED34 = 0xce,
DBG_BLOCK_ID_TD10 = 0xcf,
DBG_BLOCK_ID_TD11 = 0xd0,
DBG_BLOCK_ID_TD12 = 0xd1,
DBG_BLOCK_ID_TD13 = 0xd2,
DBG_BLOCK_ID_TD14 = 0xd3,
DBG_BLOCK_ID_TD15 = 0xd4,
DBG_BLOCK_ID_TD16 = 0xd5,
DBG_BLOCK_ID_TD17 = 0xd6,
DBG_BLOCK_ID_TD18 = 0xd7,
DBG_BLOCK_ID_TD19 = 0xd8,
DBG_BLOCK_ID_TD1A = 0xd9,
DBG_BLOCK_ID_TD1B = 0xda,
DBG_BLOCK_ID_UNUSED35 = 0xdb,
DBG_BLOCK_ID_UNUSED36 = 0xdc,
DBG_BLOCK_ID_UNUSED37 = 0xdd,
DBG_BLOCK_ID_UNUSED38 = 0xde,
DBG_BLOCK_ID_LDS00 = 0xdf,
DBG_BLOCK_ID_LDS01 = 0xe0,
DBG_BLOCK_ID_LDS02 = 0xe1,
DBG_BLOCK_ID_LDS03 = 0xe2,
DBG_BLOCK_ID_LDS04 = 0xe3,
DBG_BLOCK_ID_LDS05 = 0xe4,
DBG_BLOCK_ID_LDS06 = 0xe5,
DBG_BLOCK_ID_LDS07 = 0xe6,
DBG_BLOCK_ID_LDS08 = 0xe7,
DBG_BLOCK_ID_LDS09 = 0xe8,
DBG_BLOCK_ID_LDS0A = 0xe9,
DBG_BLOCK_ID_LDS0B = 0xea,
DBG_BLOCK_ID_UNUSED39 = 0xeb,
DBG_BLOCK_ID_UNUSED40 = 0xec,
DBG_BLOCK_ID_UNUSED41 = 0xed,
DBG_BLOCK_ID_UNUSED42 = 0xee,
DBG_BLOCK_ID_LDS10 = 0xef,
DBG_BLOCK_ID_LDS11 = 0xf0,
DBG_BLOCK_ID_LDS12 = 0xf1,
DBG_BLOCK_ID_LDS13 = 0xf2,
DBG_BLOCK_ID_LDS14 = 0xf3,
DBG_BLOCK_ID_LDS15 = 0xf4,
DBG_BLOCK_ID_LDS16 = 0xf5,
DBG_BLOCK_ID_LDS17 = 0xf6,
DBG_BLOCK_ID_LDS18 = 0xf7,
DBG_BLOCK_ID_LDS19 = 0xf8,
DBG_BLOCK_ID_LDS1A = 0xf9,
DBG_BLOCK_ID_LDS1B = 0xfa,
DBG_BLOCK_ID_UNUSED43 = 0xfb,
DBG_BLOCK_ID_UNUSED44 = 0xfc,
DBG_BLOCK_ID_UNUSED45 = 0xfd,
DBG_BLOCK_ID_UNUSED46 = 0xfe,
} DebugBlockId;
typedef enum DebugBlockId_BY2 {
DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
DBG_BLOCK_ID_VMC_BY2 = 0x1,
DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
DBG_BLOCK_ID_GRBM_BY2 = 0x3,
DBG_BLOCK_ID_CSC_BY2 = 0x4,
DBG_BLOCK_ID_IH_BY2 = 0x5,
DBG_BLOCK_ID_SQ_BY2 = 0x6,
DBG_BLOCK_ID_UVD_BY2 = 0x7,
DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
DBG_BLOCK_ID_SPIM_BY2 = 0x9,
DBG_BLOCK_ID_VC0_BY2 = 0xa,
DBG_BLOCK_ID_PA_BY2 = 0xb,
DBG_BLOCK_ID_CP0_BY2 = 0xc,
DBG_BLOCK_ID_CP2_BY2 = 0xd,
DBG_BLOCK_ID_PC0_BY2 = 0xe,
DBG_BLOCK_ID_BCI0_BY2 = 0xf,
DBG_BLOCK_ID_SXM0_BY2 = 0x10,
DBG_BLOCK_ID_SCT0_BY2 = 0x11,
DBG_BLOCK_ID_SPM0_BY2 = 0x12,
DBG_BLOCK_ID_BCI2_BY2 = 0x13,
DBG_BLOCK_ID_TCA_BY2 = 0x14,
DBG_BLOCK_ID_TCCA_BY2 = 0x15,
DBG_BLOCK_ID_MCC_BY2 = 0x16,
DBG_BLOCK_ID_MCC2_BY2 = 0x17,
DBG_BLOCK_ID_MCD_BY2 = 0x18,
DBG_BLOCK_ID_MCD2_BY2 = 0x19,
DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
DBG_BLOCK_ID_MCB_BY2 = 0x1b,
DBG_BLOCK_ID_SQA_BY2 = 0x1c,
DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
DBG_BLOCK_ID_SQB_BY2 = 0x20,
DBG_BLOCK_ID_SQB10_BY2 = 0x21,
DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
DBG_BLOCK_ID_CB_BY2 = 0x24,
DBG_BLOCK_ID_CB02_BY2 = 0x25,
DBG_BLOCK_ID_CB10_BY2 = 0x26,
DBG_BLOCK_ID_CB12_BY2 = 0x27,
DBG_BLOCK_ID_SXS_BY2 = 0x28,
DBG_BLOCK_ID_SXS2_BY2 = 0x29,
DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
DBG_BLOCK_ID_DB_BY2 = 0x2c,
DBG_BLOCK_ID_DB02_BY2 = 0x2d,
DBG_BLOCK_ID_DB10_BY2 = 0x2e,
DBG_BLOCK_ID_DB12_BY2 = 0x2f,
DBG_BLOCK_ID_TCP_BY2 = 0x30,
DBG_BLOCK_ID_TCP2_BY2 = 0x31,
DBG_BLOCK_ID_TCP4_BY2 = 0x32,
DBG_BLOCK_ID_TCP6_BY2 = 0x33,
DBG_BLOCK_ID_TCP8_BY2 = 0x34,
DBG_BLOCK_ID_TCP10_BY2 = 0x35,
DBG_BLOCK_ID_TCP12_BY2 = 0x36,
DBG_BLOCK_ID_TCP14_BY2 = 0x37,
DBG_BLOCK_ID_TCP16_BY2 = 0x38,
DBG_BLOCK_ID_TCP18_BY2 = 0x39,
DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
DBG_BLOCK_ID_TCC_BY2 = 0x40,
DBG_BLOCK_ID_TCC2_BY2 = 0x41,
DBG_BLOCK_ID_TCC4_BY2 = 0x42,
DBG_BLOCK_ID_TCC6_BY2 = 0x43,
DBG_BLOCK_ID_SPS_BY2 = 0x44,
DBG_BLOCK_ID_SPS02_BY2 = 0x45,
DBG_BLOCK_ID_SPS11_BY2 = 0x46,
DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
DBG_BLOCK_ID_TA_BY2 = 0x48,
DBG_BLOCK_ID_TA02_BY2 = 0x49,
DBG_BLOCK_ID_TA04_BY2 = 0x4a,
DBG_BLOCK_ID_TA06_BY2 = 0x4b,
DBG_BLOCK_ID_TA08_BY2 = 0x4c,
DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
DBG_BLOCK_ID_TA10_BY2 = 0x50,
DBG_BLOCK_ID_TA12_BY2 = 0x51,
DBG_BLOCK_ID_TA14_BY2 = 0x52,
DBG_BLOCK_ID_TA16_BY2 = 0x53,
DBG_BLOCK_ID_TA18_BY2 = 0x54,
DBG_BLOCK_ID_TA1A_BY2 = 0x55,
DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
DBG_BLOCK_ID_TD_BY2 = 0x58,
DBG_BLOCK_ID_TD02_BY2 = 0x59,
DBG_BLOCK_ID_TD04_BY2 = 0x5a,
DBG_BLOCK_ID_TD06_BY2 = 0x5b,
DBG_BLOCK_ID_TD08_BY2 = 0x5c,
DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
DBG_BLOCK_ID_TD10_BY2 = 0x60,
DBG_BLOCK_ID_TD12_BY2 = 0x61,
DBG_BLOCK_ID_TD14_BY2 = 0x62,
DBG_BLOCK_ID_TD16_BY2 = 0x63,
DBG_BLOCK_ID_TD18_BY2 = 0x64,
DBG_BLOCK_ID_TD1A_BY2 = 0x65,
DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
DBG_BLOCK_ID_LDS_BY2 = 0x68,
DBG_BLOCK_ID_LDS02_BY2 = 0x69,
DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
DBG_BLOCK_ID_LDS10_BY2 = 0x70,
DBG_BLOCK_ID_LDS12_BY2 = 0x71,
DBG_BLOCK_ID_LDS14_BY2 = 0x72,
DBG_BLOCK_ID_LDS16_BY2 = 0x73,
DBG_BLOCK_ID_LDS18_BY2 = 0x74,
DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
} DebugBlockId_BY2;
typedef enum DebugBlockId_BY4 {
DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
DBG_BLOCK_ID_CSC_BY4 = 0x2,
DBG_BLOCK_ID_SQ_BY4 = 0x3,
DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
DBG_BLOCK_ID_VC0_BY4 = 0x5,
DBG_BLOCK_ID_CP0_BY4 = 0x6,
DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
DBG_BLOCK_ID_SXM0_BY4 = 0x8,
DBG_BLOCK_ID_SPM0_BY4 = 0x9,
DBG_BLOCK_ID_TCAA_BY4 = 0xa,
DBG_BLOCK_ID_MCC_BY4 = 0xb,
DBG_BLOCK_ID_MCD_BY4 = 0xc,
DBG_BLOCK_ID_MCD4_BY4 = 0xd,
DBG_BLOCK_ID_SQA_BY4 = 0xe,
DBG_BLOCK_ID_SQA11_BY4 = 0xf,
DBG_BLOCK_ID_SQB_BY4 = 0x10,
DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
DBG_BLOCK_ID_CB_BY4 = 0x12,
DBG_BLOCK_ID_CB10_BY4 = 0x13,
DBG_BLOCK_ID_SXS_BY4 = 0x14,
DBG_BLOCK_ID_SXS4_BY4 = 0x15,
DBG_BLOCK_ID_DB_BY4 = 0x16,
DBG_BLOCK_ID_DB10_BY4 = 0x17,
DBG_BLOCK_ID_TCP_BY4 = 0x18,
DBG_BLOCK_ID_TCP4_BY4 = 0x19,
DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
DBG_BLOCK_ID_TCC_BY4 = 0x20,
DBG_BLOCK_ID_TCC4_BY4 = 0x21,
DBG_BLOCK_ID_SPS_BY4 = 0x22,
DBG_BLOCK_ID_SPS11_BY4 = 0x23,
DBG_BLOCK_ID_TA_BY4 = 0x24,
DBG_BLOCK_ID_TA04_BY4 = 0x25,
DBG_BLOCK_ID_TA08_BY4 = 0x26,
DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
DBG_BLOCK_ID_TA10_BY4 = 0x28,
DBG_BLOCK_ID_TA14_BY4 = 0x29,
DBG_BLOCK_ID_TA18_BY4 = 0x2a,
DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
DBG_BLOCK_ID_TD_BY4 = 0x2c,
DBG_BLOCK_ID_TD04_BY4 = 0x2d,
DBG_BLOCK_ID_TD08_BY4 = 0x2e,
DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
DBG_BLOCK_ID_TD10_BY4 = 0x30,
DBG_BLOCK_ID_TD14_BY4 = 0x31,
DBG_BLOCK_ID_TD18_BY4 = 0x32,
DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
DBG_BLOCK_ID_LDS_BY4 = 0x34,
DBG_BLOCK_ID_LDS04_BY4 = 0x35,
DBG_BLOCK_ID_LDS08_BY4 = 0x36,
DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
DBG_BLOCK_ID_LDS10_BY4 = 0x38,
DBG_BLOCK_ID_LDS14_BY4 = 0x39,
DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
} DebugBlockId_BY4;
typedef enum DebugBlockId_BY8 {
DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
DBG_BLOCK_ID_CSC_BY8 = 0x1,
DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
DBG_BLOCK_ID_CP0_BY8 = 0x3,
DBG_BLOCK_ID_SXM0_BY8 = 0x4,
DBG_BLOCK_ID_TCA_BY8 = 0x5,
DBG_BLOCK_ID_MCD_BY8 = 0x6,
DBG_BLOCK_ID_SQA_BY8 = 0x7,
DBG_BLOCK_ID_SQB_BY8 = 0x8,
DBG_BLOCK_ID_CB_BY8 = 0x9,
DBG_BLOCK_ID_SXS_BY8 = 0xa,
DBG_BLOCK_ID_DB_BY8 = 0xb,
DBG_BLOCK_ID_TCP_BY8 = 0xc,
DBG_BLOCK_ID_TCP8_BY8 = 0xd,
DBG_BLOCK_ID_TCP16_BY8 = 0xe,
DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
DBG_BLOCK_ID_TCC_BY8 = 0x10,
DBG_BLOCK_ID_SPS_BY8 = 0x11,
DBG_BLOCK_ID_TA_BY8 = 0x12,
DBG_BLOCK_ID_TA08_BY8 = 0x13,
DBG_BLOCK_ID_TA10_BY8 = 0x14,
DBG_BLOCK_ID_TA18_BY8 = 0x15,
DBG_BLOCK_ID_TD_BY8 = 0x16,
DBG_BLOCK_ID_TD08_BY8 = 0x17,
DBG_BLOCK_ID_TD10_BY8 = 0x18,
DBG_BLOCK_ID_TD18_BY8 = 0x19,
DBG_BLOCK_ID_LDS_BY8 = 0x1a,
DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
} DebugBlockId_BY8;
typedef enum DebugBlockId_BY16 {
DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
DBG_BLOCK_ID_SXM_BY16 = 0x2,
DBG_BLOCK_ID_MCD_BY16 = 0x3,
DBG_BLOCK_ID_SQB_BY16 = 0x4,
DBG_BLOCK_ID_SXS_BY16 = 0x5,
DBG_BLOCK_ID_TCP_BY16 = 0x6,
DBG_BLOCK_ID_TCP16_BY16 = 0x7,
DBG_BLOCK_ID_TCC_BY16 = 0x8,
DBG_BLOCK_ID_TA_BY16 = 0x9,
DBG_BLOCK_ID_TA10_BY16 = 0xa,
DBG_BLOCK_ID_TD_BY16 = 0xb,
DBG_BLOCK_ID_TD10_BY16 = 0xc,
DBG_BLOCK_ID_LDS_BY16 = 0xd,
DBG_BLOCK_ID_LDS10_BY16 = 0xe,
} DebugBlockId_BY16;
typedef enum SurfaceEndian {
ENDIAN_NONE = 0x0,
ENDIAN_8IN16 = 0x1,
ENDIAN_8IN32 = 0x2,
ENDIAN_8IN64 = 0x3,
} SurfaceEndian;
typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL = 0x0,
ARRAY_LINEAR_ALIGNED = 0x1,
ARRAY_1D_TILED_THIN1 = 0x2,
ARRAY_1D_TILED_THICK = 0x3,
ARRAY_2D_TILED_THIN1 = 0x4,
ARRAY_PRT_TILED_THIN1 = 0x5,
ARRAY_PRT_2D_TILED_THIN1 = 0x6,
ARRAY_2D_TILED_THICK = 0x7,
ARRAY_2D_TILED_XTHICK = 0x8,
ARRAY_PRT_TILED_THICK = 0x9,
ARRAY_PRT_2D_TILED_THICK = 0xa,
ARRAY_PRT_3D_TILED_THIN1 = 0xb,
ARRAY_3D_TILED_THIN1 = 0xc,
ARRAY_3D_TILED_THICK = 0xd,
ARRAY_3D_TILED_XTHICK = 0xe,
ARRAY_PRT_3D_TILED_THICK = 0xf,
} ArrayMode;
typedef enum PipeTiling {
CONFIG_1_PIPE = 0x0,
CONFIG_2_PIPE = 0x1,
CONFIG_4_PIPE = 0x2,
CONFIG_8_PIPE = 0x3,
} PipeTiling;
typedef enum BankTiling {
CONFIG_4_BANK = 0x0,
CONFIG_8_BANK = 0x1,
} BankTiling;
typedef enum GroupInterleave {
CONFIG_256B_GROUP = 0x0,
CONFIG_512B_GROUP = 0x1,
} GroupInterleave;
typedef enum RowTiling {
CONFIG_1KB_ROW = 0x0,
CONFIG_2KB_ROW = 0x1,
CONFIG_4KB_ROW = 0x2,
CONFIG_8KB_ROW = 0x3,
CONFIG_1KB_ROW_OPT = 0x4,
CONFIG_2KB_ROW_OPT = 0x5,
CONFIG_4KB_ROW_OPT = 0x6,
CONFIG_8KB_ROW_OPT = 0x7,
} RowTiling;
typedef enum BankSwapBytes {
CONFIG_128B_SWAPS = 0x0,
CONFIG_256B_SWAPS = 0x1,
CONFIG_512B_SWAPS = 0x2,
CONFIG_1KB_SWAPS = 0x3,
} BankSwapBytes;
typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT = 0x0,
CONFIG_2KB_SPLIT = 0x1,
CONFIG_4KB_SPLIT = 0x2,
CONFIG_8KB_SPLIT = 0x3,
} SampleSplitBytes;
typedef enum NumPipes {
ADDR_CONFIG_1_PIPE = 0x0,
ADDR_CONFIG_2_PIPE = 0x1,
ADDR_CONFIG_4_PIPE = 0x2,
ADDR_CONFIG_8_PIPE = 0x3,
} NumPipes;
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
} PipeInterleaveSize;
typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
} BankInterleaveSize;
typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
} NumShaderEngines;
typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16 = 0x0,
ADDR_CONFIG_SE_TILE_32 = 0x1,
} ShaderEngineTileSize;
typedef enum NumGPUs {
ADDR_CONFIG_1_GPU = 0x0,
ADDR_CONFIG_2_GPU = 0x1,
ADDR_CONFIG_4_GPU = 0x2,
} NumGPUs;
typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16 = 0x0,
ADDR_CONFIG_GPU_TILE_32 = 0x1,
ADDR_CONFIG_GPU_TILE_64 = 0x2,
ADDR_CONFIG_GPU_TILE_128 = 0x3,
} MultiGPUTileSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x0,
ADDR_CONFIG_2KB_ROW = 0x1,
ADDR_CONFIG_4KB_ROW = 0x2,
} RowSize;
typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES = 0x0,
ADDR_CONFIG_2_LOWER_PIPES = 0x1,
} NumLowerPipes;
typedef enum ColorTransform {
DCC_CT_AUTO = 0x0,
DCC_CT_NONE = 0x1,
ABGR_TO_A_BG_G_RB = 0x2,
BGRA_TO_BG_G_RB_A = 0x3,
} ColorTransform;
typedef enum CompareRef {
REF_NEVER = 0x0,
REF_LESS = 0x1,
REF_EQUAL = 0x2,
REF_LEQUAL = 0x3,
REF_GREATER = 0x4,
REF_NOTEQUAL = 0x5,
REF_GEQUAL = 0x6,
REF_ALWAYS = 0x7,
} CompareRef;
typedef enum ReadSize {
READ_256_BITS = 0x0,
READ_512_BITS = 0x1,
} ReadSize;
typedef enum DepthFormat {
DEPTH_INVALID = 0x0,
DEPTH_16 = 0x1,
DEPTH_X8_24 = 0x2,
DEPTH_8_24 = 0x3,
DEPTH_X8_24_FLOAT = 0x4,
DEPTH_8_24_FLOAT = 0x5,
DEPTH_32_FLOAT = 0x6,
DEPTH_X24_8_32_FLOAT = 0x7,
} DepthFormat;
typedef enum ZFormat {
Z_INVALID = 0x0,
Z_16 = 0x1,
Z_24 = 0x2,
Z_32_FLOAT = 0x3,
} ZFormat;
typedef enum StencilFormat {
STENCIL_INVALID = 0x0,
STENCIL_8 = 0x1,
} StencilFormat;
typedef enum CmaskMode {
CMASK_CLEAR_NONE = 0x0,
CMASK_CLEAR_ONE = 0x1,
CMASK_CLEAR_ALL = 0x2,
CMASK_ANY_EXPANDED = 0x3,
CMASK_ALPHA0_FRAG1 = 0x4,
CMASK_ALPHA0_FRAG2 = 0x5,
CMASK_ALPHA0_FRAG4 = 0x6,
CMASK_ALPHA0_FRAGS = 0x7,
CMASK_ALPHA1_FRAG1 = 0x8,
CMASK_ALPHA1_FRAG2 = 0x9,
CMASK_ALPHA1_FRAG4 = 0xa,
CMASK_ALPHA1_FRAGS = 0xb,
CMASK_ALPHAX_FRAG1 = 0xc,
CMASK_ALPHAX_FRAG2 = 0xd,
CMASK_ALPHAX_FRAG4 = 0xe,
CMASK_ALPHAX_FRAGS = 0xf,
} CmaskMode;
typedef enum QuadExportFormat {
EXPORT_UNUSED = 0x0,
EXPORT_32_R = 0x1,
EXPORT_32_GR = 0x2,
EXPORT_32_AR = 0x3,
EXPORT_FP16_ABGR = 0x4,
EXPORT_UNSIGNED16_ABGR = 0x5,
EXPORT_SIGNED16_ABGR = 0x6,
EXPORT_32_ABGR = 0x7,
} QuadExportFormat;
typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR = 0x0,
EXPORT_4P_16BPC_ABGR = 0x1,
EXPORT_4P_32BPC_GR = 0x2,
EXPORT_4P_32BPC_AR = 0x3,
EXPORT_2P_32BPC_ABGR = 0x4,
EXPORT_8P_32BPC_R = 0x5,
} QuadExportFormatOld;
typedef enum ColorFormat {
COLOR_INVALID = 0x0,
COLOR_8 = 0x1,
COLOR_16 = 0x2,
COLOR_8_8 = 0x3,
COLOR_32 = 0x4,
COLOR_16_16 = 0x5,
COLOR_10_11_11 = 0x6,
COLOR_11_11_10 = 0x7,
COLOR_10_10_10_2 = 0x8,
COLOR_2_10_10_10 = 0x9,
COLOR_8_8_8_8 = 0xa,
COLOR_32_32 = 0xb,
COLOR_16_16_16_16 = 0xc,
COLOR_RESERVED_13 = 0xd,
COLOR_32_32_32_32 = 0xe,
COLOR_RESERVED_15 = 0xf,
COLOR_5_6_5 = 0x10,
COLOR_1_5_5_5 = 0x11,
COLOR_5_5_5_1 = 0x12,
COLOR_4_4_4_4 = 0x13,
COLOR_8_24 = 0x14,
COLOR_24_8 = 0x15,
COLOR_X24_8_32_FLOAT = 0x16,
COLOR_RESERVED_23 = 0x17,
} ColorFormat;
typedef enum SurfaceFormat {
FMT_INVALID = 0x0,
FMT_8 = 0x1,
FMT_16 = 0x2,
FMT_8_8 = 0x3,
FMT_32 = 0x4,
FMT_16_16 = 0x5,
FMT_10_11_11 = 0x6,
FMT_11_11_10 = 0x7,
FMT_10_10_10_2 = 0x8,
FMT_2_10_10_10 = 0x9,
FMT_8_8_8_8 = 0xa,
FMT_32_32 = 0xb,
FMT_16_16_16_16 = 0xc,
FMT_32_32_32 = 0xd,
FMT_32_32_32_32 = 0xe,
FMT_RESERVED_4 = 0xf,
FMT_5_6_5 = 0x10,
FMT_1_5_5_5 = 0x11,
FMT_5_5_5_1 = 0x12,
FMT_4_4_4_4 = 0x13,
FMT_8_24 = 0x14,
FMT_24_8 = 0x15,
FMT_X24_8_32_FLOAT = 0x16,
FMT_RESERVED_33 = 0x17,
FMT_11_11_10_FLOAT = 0x18,
FMT_16_FLOAT = 0x19,
FMT_32_FLOAT = 0x1a,
FMT_16_16_FLOAT = 0x1b,
FMT_8_24_FLOAT = 0x1c,
FMT_24_8_FLOAT = 0x1d,
FMT_32_32_FLOAT = 0x1e,
FMT_10_11_11_FLOAT = 0x1f,
FMT_16_16_16_16_FLOAT = 0x20,
FMT_3_3_2 = 0x21,
FMT_6_5_5 = 0x22,
FMT_32_32_32_32_FLOAT = 0x23,
FMT_RESERVED_36 = 0x24,
FMT_1 = 0x25,
FMT_1_REVERSED = 0x26,
FMT_GB_GR = 0x27,
FMT_BG_RG = 0x28,
FMT_32_AS_8 = 0x29,
FMT_32_AS_8_8 = 0x2a,
FMT_5_9_9_9_SHAREDEXP = 0x2b,
FMT_8_8_8 = 0x2c,
FMT_16_16_16 = 0x2d,
FMT_16_16_16_FLOAT = 0x2e,
FMT_4_4 = 0x2f,
FMT_32_32_32_FLOAT = 0x30,
FMT_BC1 = 0x31,
FMT_BC2 = 0x32,
FMT_BC3 = 0x33,
FMT_BC4 = 0x34,
FMT_BC5 = 0x35,
FMT_BC6 = 0x36,
FMT_BC7 = 0x37,
FMT_32_AS_32_32_32_32 = 0x38,
FMT_APC3 = 0x39,
FMT_APC4 = 0x3a,
FMT_APC5 = 0x3b,
FMT_APC6 = 0x3c,
FMT_APC7 = 0x3d,
FMT_CTX1 = 0x3e,
FMT_RESERVED_63 = 0x3f,
} SurfaceFormat;
typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID = 0x0,
BUF_DATA_FORMAT_8 = 0x1,
BUF_DATA_FORMAT_16 = 0x2,
BUF_DATA_FORMAT_8_8 = 0x3,
BUF_DATA_FORMAT_32 = 0x4,
BUF_DATA_FORMAT_16_16 = 0x5,
BUF_DATA_FORMAT_10_11_11 = 0x6,
BUF_DATA_FORMAT_11_11_10 = 0x7,
BUF_DATA_FORMAT_10_10_10_2 = 0x8,
BUF_DATA_FORMAT_2_10_10_10 = 0x9,
BUF_DATA_FORMAT_8_8_8_8 = 0xa,
BUF_DATA_FORMAT_32_32 = 0xb,
BUF_DATA_FORMAT_16_16_16_16 = 0xc,
BUF_DATA_FORMAT_32_32_32 = 0xd,
BUF_DATA_FORMAT_32_32_32_32 = 0xe,
BUF_DATA_FORMAT_RESERVED_15 = 0xf,
} BUF_DATA_FORMAT;
typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID = 0x0,
IMG_DATA_FORMAT_8 = 0x1,
IMG_DATA_FORMAT_16 = 0x2,
IMG_DATA_FORMAT_8_8 = 0x3,
IMG_DATA_FORMAT_32 = 0x4,
IMG_DATA_FORMAT_16_16 = 0x5,
IMG_DATA_FORMAT_10_11_11 = 0x6,
IMG_DATA_FORMAT_11_11_10 = 0x7,
IMG_DATA_FORMAT_10_10_10_2 = 0x8,
IMG_DATA_FORMAT_2_10_10_10 = 0x9,
IMG_DATA_FORMAT_8_8_8_8 = 0xa,
IMG_DATA_FORMAT_32_32 = 0xb,
IMG_DATA_FORMAT_16_16_16_16 = 0xc,
IMG_DATA_FORMAT_32_32_32 = 0xd,
IMG_DATA_FORMAT_32_32_32_32 = 0xe,
IMG_DATA_FORMAT_RESERVED_15 = 0xf,
IMG_DATA_FORMAT_5_6_5 = 0x10,
IMG_DATA_FORMAT_1_5_5_5 = 0x11,
IMG_DATA_FORMAT_5_5_5_1 = 0x12,
IMG_DATA_FORMAT_4_4_4_4 = 0x13,
IMG_DATA_FORMAT_8_24 = 0x14,
IMG_DATA_FORMAT_24_8 = 0x15,
IMG_DATA_FORMAT_X24_8_32 = 0x16,
IMG_DATA_FORMAT_RESERVED_23 = 0x17,
IMG_DATA_FORMAT_RESERVED_24 = 0x18,
IMG_DATA_FORMAT_RESERVED_25 = 0x19,
IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
IMG_DATA_FORMAT_GB_GR = 0x20,
IMG_DATA_FORMAT_BG_RG = 0x21,
IMG_DATA_FORMAT_5_9_9_9 = 0x22,
IMG_DATA_FORMAT_BC1 = 0x23,
IMG_DATA_FORMAT_BC2 = 0x24,
IMG_DATA_FORMAT_BC3 = 0x25,
IMG_DATA_FORMAT_BC4 = 0x26,
IMG_DATA_FORMAT_BC5 = 0x27,
IMG_DATA_FORMAT_BC6 = 0x28,
IMG_DATA_FORMAT_BC7 = 0x29,
IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
IMG_DATA_FORMAT_4_4 = 0x39,
IMG_DATA_FORMAT_6_5_5 = 0x3a,
IMG_DATA_FORMAT_1 = 0x3b,
IMG_DATA_FORMAT_1_REVERSED = 0x3c,
IMG_DATA_FORMAT_32_AS_8 = 0x3d,
IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
} IMG_DATA_FORMAT;
typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM = 0x0,
BUF_NUM_FORMAT_SNORM = 0x1,
BUF_NUM_FORMAT_USCALED = 0x2,
BUF_NUM_FORMAT_SSCALED = 0x3,
BUF_NUM_FORMAT_UINT = 0x4,
BUF_NUM_FORMAT_SINT = 0x5,
BUF_NUM_FORMAT_RESERVED_6 = 0x6,
BUF_NUM_FORMAT_FLOAT = 0x7,
} BUF_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM = 0x0,
IMG_NUM_FORMAT_SNORM = 0x1,
IMG_NUM_FORMAT_USCALED = 0x2,
IMG_NUM_FORMAT_SSCALED = 0x3,
IMG_NUM_FORMAT_UINT = 0x4,
IMG_NUM_FORMAT_SINT = 0x5,
IMG_NUM_FORMAT_RESERVED_6 = 0x6,
IMG_NUM_FORMAT_FLOAT = 0x7,
IMG_NUM_FORMAT_RESERVED_8 = 0x8,
IMG_NUM_FORMAT_SRGB = 0x9,
IMG_NUM_FORMAT_RESERVED_10 = 0xa,
IMG_NUM_FORMAT_RESERVED_11 = 0xb,
IMG_NUM_FORMAT_RESERVED_12 = 0xc,
IMG_NUM_FORMAT_RESERVED_13 = 0xd,
IMG_NUM_FORMAT_RESERVED_14 = 0xe,
IMG_NUM_FORMAT_RESERVED_15 = 0xf,
} IMG_NUM_FORMAT;
typedef enum TileType {
ARRAY_COLOR_TILE = 0x0,
ARRAY_DEPTH_TILE = 0x1,
} TileType;
typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
} NonDispTilingOrder;
typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
ADDR_SURF_THIN_MICRO_TILING = 0x1,
ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
ADDR_SURF_THICK_MICRO_TILING = 0x4,
} MicroTileMode;
typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B = 0x0,
ADDR_SURF_TILE_SPLIT_128B = 0x1,
ADDR_SURF_TILE_SPLIT_256B = 0x2,
ADDR_SURF_TILE_SPLIT_512B = 0x3,
ADDR_SURF_TILE_SPLIT_1KB = 0x4,
ADDR_SURF_TILE_SPLIT_2KB = 0x5,
ADDR_SURF_TILE_SPLIT_4KB = 0x6,
} TileSplit;
typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
} SampleSplit;
typedef enum PipeConfig {
ADDR_SURF_P2 = 0x0,
ADDR_SURF_P2_RESERVED0 = 0x1,
ADDR_SURF_P2_RESERVED1 = 0x2,
ADDR_SURF_P2_RESERVED2 = 0x3,
ADDR_SURF_P4_8x16 = 0x4,
ADDR_SURF_P4_16x16 = 0x5,
ADDR_SURF_P4_16x32 = 0x6,
ADDR_SURF_P4_32x32 = 0x7,
ADDR_SURF_P8_16x16_8x16 = 0x8,
ADDR_SURF_P8_16x32_8x16 = 0x9,
ADDR_SURF_P8_32x32_8x16 = 0xa,
ADDR_SURF_P8_16x32_16x16 = 0xb,
ADDR_SURF_P8_32x32_16x16 = 0xc,
ADDR_SURF_P8_32x32_16x32 = 0xd,
ADDR_SURF_P8_32x64_32x32 = 0xe,
ADDR_SURF_P8_RESERVED0 = 0xf,
ADDR_SURF_P16_32x32_8x16 = 0x10,
ADDR_SURF_P16_32x32_16x16 = 0x11,
} PipeConfig;
typedef enum NumBanks {
ADDR_SURF_2_BANK = 0x0,
ADDR_SURF_4_BANK = 0x1,
ADDR_SURF_8_BANK = 0x2,
ADDR_SURF_16_BANK = 0x3,
} NumBanks;
typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1 = 0x0,
ADDR_SURF_BANK_WIDTH_2 = 0x1,
ADDR_SURF_BANK_WIDTH_4 = 0x2,
ADDR_SURF_BANK_WIDTH_8 = 0x3,
} BankWidth;
typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1 = 0x0,
ADDR_SURF_BANK_HEIGHT_2 = 0x1,
ADDR_SURF_BANK_HEIGHT_4 = 0x2,
ADDR_SURF_BANK_HEIGHT_8 = 0x3,
} BankHeight;
typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1 = 0x0,
ADDR_SURF_BANK_WH_2 = 0x1,
ADDR_SURF_BANK_WH_4 = 0x2,
ADDR_SURF_BANK_WH_8 = 0x3,
} BankWidthHeight;
typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1 = 0x0,
ADDR_SURF_MACRO_ASPECT_2 = 0x1,
ADDR_SURF_MACRO_ASPECT_4 = 0x2,
ADDR_SURF_MACRO_ASPECT_8 = 0x3,
} MacroTileAspect;
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x0,
GATCL1_TYPE_SHOOTDOWN = 0x1,
GATCL1_TYPE_BYPASS = 0x2,
} GATCL1RequestType;
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x0,
TCC_CACHE_POLICY_STREAM = 0x1,
} TCC_CACHE_POLICIES;
typedef enum MTYPE {
MTYPE_NC_NV = 0x0,
MTYPE_NC = 0x1,
MTYPE_CC = 0x2,
MTYPE_UC = 0x3,
} MTYPE;
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x0,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
PERFMON_COUNTER_MODE_MAX = 0x2,
PERFMON_COUNTER_MODE_DIRTY = 0x3,
PERFMON_COUNTER_MODE_SAMPLE = 0x4,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
PERFMON_COUNTER_MODE_RESERVED = 0xf,
} PERFMON_COUNTER_MODE;
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x0,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
PERFMON_SPM_MODE_RESERVED_5 = 0x5,
PERFMON_SPM_MODE_RESERVED_6 = 0x6,
PERFMON_SPM_MODE_RESERVED_7 = 0x7,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
} PERFMON_SPM_MODE;
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x0,
ARRAY_TILED = 0x1,
} SurfaceTiling;
typedef enum SurfaceArray {
ARRAY_1D = 0x0,
ARRAY_2D = 0x1,
ARRAY_3D = 0x2,
ARRAY_3D_SLICE = 0x3,
} SurfaceArray;
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x0,
ARRAY_2D_COLOR = 0x1,
ARRAY_3D_SLICE_COLOR = 0x3,
} ColorArray;
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x0,
ARRAY_2D_DEPTH = 0x1,
} DepthArray;
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x4,
} ENUM_NUM_SIMD_PER_CU;
typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST = 0x0,
FORCE_LIGHT_SLEEP_REQUEST = 0x1,
FORCE_DEEP_SLEEP_REQUEST = 0x2,
FORCE_SHUT_DOWN_REQUEST = 0x3,
} MEM_PWR_FORCE_CTRL;
typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ = 0x0,
FORCE_LIGHT_SLEEP_REQ = 0x1,
} MEM_PWR_FORCE_CTRL2;
typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL = 0x0,
DISABLE_MEM_PWR_CTRL = 0x1,
} MEM_PWR_DIS_CTRL;
typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
} MEM_PWR_SEL_CTRL;
typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN = 0x0,
DYNAMIC_LIGHT_SLEEP_EN = 0x1,
} MEM_PWR_SEL_CTRL2;
#endif /* ACP_2_2_ENUM_H */
sound/soc/amd/include/acp_2_2_sh_mask.h 0 → 100644
View file @ 188bdf72
This source diff could not be displayed because it is too large. You can view the blob instead.
sound/soc/codecs/wm5110.c
View file @ 188bdf72
......@@ -2173,10 +2173,23 @@ static int wm5110_open(struct snd_compr_stream *stream)
return wm_adsp_compr_open(&priv->core.adsp[n_adsp], stream);
}
static irqreturn_t wm5110_adsp2_irq(int irq, void *data)
{
struct wm5110_priv *florida = data;
int ret;
ret = wm_adsp_compr_handle_irq(&florida->core.adsp[2]);
if (ret == -ENODEV)
return IRQ_NONE;
return IRQ_HANDLED;
}
static int wm5110_codec_probe(struct snd_soc_codec *codec)
{
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct wm5110_priv *priv = snd_soc_codec_get_drvdata(codec);
struct arizona *arizona = priv->core.arizona;
int i, ret;
priv->core.arizona->dapm = dapm;
......@@ -2185,6 +2198,14 @@ static int wm5110_codec_probe(struct snd_soc_codec *codec)
arizona_init_gpio(codec);
arizona_init_mono(codec);
ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", wm5110_adsp2_irq,
priv);
if (ret != 0) {
dev_err(codec->dev, "Failed to request DSP IRQ: %d\n", ret);
return ret;
}
for (i = 0; i < WM5110_NUM_ADSP; ++i) {
ret = wm_adsp2_codec_probe(&priv->core.adsp[i], codec);
if (ret)
......@@ -2205,12 +2226,15 @@ static int wm5110_codec_probe(struct snd_soc_codec *codec)
for (--i; i >= 0; --i)
wm_adsp2_codec_remove(&priv->core.adsp[i], codec);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);
return ret;
}
static int wm5110_codec_remove(struct snd_soc_codec *codec)
{
struct wm5110_priv *priv = snd_soc_codec_get_drvdata(codec);
struct arizona *arizona = priv->core.arizona;
int i;
for (i = 0; i < WM5110_NUM_ADSP; ++i)
......@@ -2218,6 +2242,8 @@ static int wm5110_codec_remove(struct snd_soc_codec *codec)
priv->core.arizona->dapm = NULL;
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);
return 0;
}
......@@ -2269,6 +2295,8 @@ static struct snd_compr_ops wm5110_compr_ops = {
.set_params = wm_adsp_compr_set_params,
.get_caps = wm_adsp_compr_get_caps,
.trigger = wm_adsp_compr_trigger,
.pointer = wm_adsp_compr_pointer,
.copy = wm_adsp_compr_copy,
};
static struct snd_soc_platform_driver wm5110_compr_platform = {
......
sound/soc/codecs/wm_adsp.c
View file @ 188bdf72
......@@ -279,6 +279,11 @@ struct wm_adsp_compr_buf {
struct wm_adsp_buffer_region *regions;
u32 host_buf_ptr;
u32 error;
u32 irq_count;
int read_index;
int avail;
};
struct wm_adsp_compr {
......@@ -287,6 +292,9 @@ struct wm_adsp_compr {
struct snd_compr_stream *stream;
struct snd_compressed_buffer size;
u32 *raw_buf;
unsigned int copied_total;
};
#define WM_ADSP_DATA_WORD_SIZE 3
......@@ -2378,6 +2386,7 @@ int wm_adsp_compr_free(struct snd_compr_stream *stream)
dsp->compr = NULL;
kfree(compr->raw_buf);
kfree(compr);
mutex_unlock(&dsp->pwr_lock);
......@@ -2436,10 +2445,16 @@ static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
return -EINVAL;
}
static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
{
return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
}
int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
struct snd_compr_params *params)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
unsigned int size;
int ret;
ret = wm_adsp_compr_check_params(stream, params);
......@@ -2451,6 +2466,11 @@ int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
compr->size.fragment_size, compr->size.fragments);
size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
if (!compr->raw_buf)
return -ENOMEM;
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
......@@ -2622,6 +2642,8 @@ static int wm_adsp_buffer_init(struct wm_adsp *dsp)
return -ENOMEM;
buf->dsp = dsp;
buf->read_index = -1;
buf->irq_count = 0xFFFFFFFF;
ret = wm_adsp_buffer_locate(buf);
if (ret < 0) {
......@@ -2705,6 +2727,16 @@ int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
ret);
break;
}
/* Trigger the IRQ at one fragment of data */
ret = wm_adsp_buffer_write(compr->buf,
HOST_BUFFER_FIELD(high_water_mark),
wm_adsp_compr_frag_words(compr));
if (ret < 0) {
adsp_err(dsp, "Failed to set high water mark: %d\n",
ret);
break;
}
break;
case SNDRV_PCM_TRIGGER_STOP:
break;
......@@ -2719,4 +2751,298 @@ int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
{
int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
return buf->regions[last_region].cumulative_size;
}
static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
{
u32 next_read_index, next_write_index;
int write_index, read_index, avail;
int ret;
/* Only sync read index if we haven't already read a valid index */
if (buf->read_index < 0) {
ret = wm_adsp_buffer_read(buf,
HOST_BUFFER_FIELD(next_read_index),
&next_read_index);
if (ret < 0)
return ret;
read_index = sign_extend32(next_read_index, 23);
if (read_index < 0) {
adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
return 0;
}
buf->read_index = read_index;
}
ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
&next_write_index);
if (ret < 0)
return ret;
write_index = sign_extend32(next_write_index, 23);
avail = write_index - buf->read_index;
if (avail < 0)
avail += wm_adsp_buffer_size(buf);
adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
buf->read_index, write_index, avail);
buf->avail = avail;
return 0;
}
int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
{
struct wm_adsp_compr_buf *buf = dsp->buffer;
struct wm_adsp_compr *compr = dsp->compr;
int ret = 0;
mutex_lock(&dsp->pwr_lock);
if (!buf) {
adsp_err(dsp, "Spurious buffer IRQ\n");
ret = -ENODEV;
goto out;
}
adsp_dbg(dsp, "Handling buffer IRQ\n");
ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
if (ret < 0) {
adsp_err(dsp, "Failed to check buffer error: %d\n", ret);
goto out;
}
if (buf->error != 0) {
adsp_err(dsp, "Buffer error occurred: %d\n", buf->error);
ret = -EIO;
goto out;
}
ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
&buf->irq_count);
if (ret < 0) {
adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
goto out;
}
ret = wm_adsp_buffer_update_avail(buf);
if (ret < 0) {
adsp_err(dsp, "Error reading avail: %d\n", ret);
goto out;
}
if (compr->stream)
snd_compr_fragment_elapsed(compr->stream);
out:
mutex_unlock(&dsp->pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
{
if (buf->irq_count & 0x01)
return 0;
adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
buf->irq_count);
buf->irq_count |= 0x01;
return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
buf->irq_count);
}
int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp_compr_buf *buf = compr->buf;
struct wm_adsp *dsp = compr->dsp;
int ret = 0;
adsp_dbg(dsp, "Pointer request\n");
mutex_lock(&dsp->pwr_lock);
if (!compr->buf) {
ret = -ENXIO;
goto out;
}
if (compr->buf->error) {
ret = -EIO;
goto out;
}
if (buf->avail < wm_adsp_compr_frag_words(compr)) {
ret = wm_adsp_buffer_update_avail(buf);
if (ret < 0) {
adsp_err(dsp, "Error reading avail: %d\n", ret);
goto out;
}
/*
* If we really have less than 1 fragment available tell the
* DSP to inform us once a whole fragment is available.
*/
if (buf->avail < wm_adsp_compr_frag_words(compr)) {
ret = wm_adsp_buffer_reenable_irq(buf);
if (ret < 0) {
adsp_err(dsp,
"Failed to re-enable buffer IRQ: %d\n",
ret);
goto out;
}
}
}
tstamp->copied_total = compr->copied_total;
tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
out:
mutex_unlock(&dsp->pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
{
struct wm_adsp_compr_buf *buf = compr->buf;
u8 *pack_in = (u8 *)compr->raw_buf;
u8 *pack_out = (u8 *)compr->raw_buf;
unsigned int adsp_addr;
int mem_type, nwords, max_read;
int i, j, ret;
/* Calculate read parameters */
for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
if (buf->read_index < buf->regions[i].cumulative_size)
break;
if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
return -EINVAL;
mem_type = buf->regions[i].mem_type;
adsp_addr = buf->regions[i].base_addr +
(buf->read_index - buf->regions[i].offset);
max_read = wm_adsp_compr_frag_words(compr);
nwords = buf->regions[i].cumulative_size - buf->read_index;
if (nwords > target)
nwords = target;
if (nwords > buf->avail)
nwords = buf->avail;
if (nwords > max_read)
nwords = max_read;
if (!nwords)
return 0;
/* Read data from DSP */
ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
nwords, compr->raw_buf);
if (ret < 0)
return ret;
/* Remove the padding bytes from the data read from the DSP */
for (i = 0; i < nwords; i++) {
for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
*pack_out++ = *pack_in++;
pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
}
/* update read index to account for words read */
buf->read_index += nwords;
if (buf->read_index == wm_adsp_buffer_size(buf))
buf->read_index = 0;
ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
buf->read_index);
if (ret < 0)
return ret;
/* update avail to account for words read */
buf->avail -= nwords;
return nwords;
}
static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
char __user *buf, size_t count)
{
struct wm_adsp *dsp = compr->dsp;
int ntotal = 0;
int nwords, nbytes;
adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
if (!compr->buf)
return -ENXIO;
if (compr->buf->error)
return -EIO;
count /= WM_ADSP_DATA_WORD_SIZE;
do {
nwords = wm_adsp_buffer_capture_block(compr, count);
if (nwords < 0) {
adsp_err(dsp, "Failed to capture block: %d\n", nwords);
return nwords;
}
nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
adsp_dbg(dsp, "Read %d bytes\n", nbytes);
if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
ntotal, nbytes);
return -EFAULT;
}
count -= nwords;
ntotal += nbytes;
} while (nwords > 0 && count > 0);
compr->copied_total += ntotal;
return ntotal;
}
int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
size_t count)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp *dsp = compr->dsp;
int ret;
mutex_lock(&dsp->pwr_lock);
if (stream->direction == SND_COMPRESS_CAPTURE)
ret = wm_adsp_compr_read(compr, buf, count);
else
ret = -ENOTSUPP;
mutex_unlock(&dsp->pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
MODULE_LICENSE("GPL v2");
sound/soc/codecs/wm_adsp.h
View file @ 188bdf72
......@@ -112,5 +112,10 @@ extern int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
extern int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
struct snd_compr_caps *caps);
extern int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd);
extern int wm_adsp_compr_handle_irq(struct wm_adsp *dsp);
extern int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp);
extern int wm_adsp_compr_copy(struct snd_compr_stream *stream,
char __user *buf, size_t count);
#endif
sound/soc/dwc/designware_i2s.c
View file @ 188bdf72
......@@ -500,6 +500,10 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
u32 idx;
if (dev->capability & DWC_I2S_RECORD &&
dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
comp1 = comp1 & ~BIT(5);
if (COMP1_TX_ENABLED(comp1)) {
dev_dbg(dev->dev, " designware: play supported\n");
idx = COMP1_TX_WORDSIZE_0(comp1);
......
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