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Commit 1b66a76f authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk 

into evo.osdl.org:/home/torvalds/v2.6/linux
parents 56d1317d 1b26d7ab
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Documentation/arm/memory.txt
View file @ 1b66a76f
Kernel Memory Layout on ARM Linux
Russell King <rmk@arm.linux.org.uk>
April 27, 2003 (2.5.68)
May 21, 2004 (2.6.6)
This document describes the virtual memory layout which the Linux
kernel uses for ARM processors. It indicates which regions are
......@@ -29,32 +29,30 @@ ffff0000 ffff0fff CPU vector page.
CPU supports vector relocation (control
register V bit.)
ffe00000 fffeffff Free for platform use, not recommended.
ffc00000 fffeffff DMA memory mapping region. Memory returned
by the dma_alloc_xxx functions will be
dynamically mapped here.
ffc00000 ffdfffff 2MB consistent memory mapping.
Memory returned by the consistent_alloc
low level function will be dynamically
mapped here.
ff000000 ffbfffff Reserved for future expansion of DMA
mapping region.
ff000000 ffbfffff Free for platform use, not recommended.
VMALLOC_END feffffff Free for platform use, recommended.
VMALLOC_END ff000000 Free for platform use, recommended.
VMALLOC_START VMALLOC_END vmalloc() / ioremap() space.
VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
Memory returned by vmalloc/ioremap will
be dynamically placed in this region.
VMALLOC_START may be based upon the value
of the high_memory variable.
PAGE_OFFSET high_memory Kernel direct-mapped RAM region.
PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region.
This maps the platforms RAM, and typically
maps all platform RAM in a 1:1 relationship.
TASK_SIZE PAGE_OFFSET Kernel module space
TASK_SIZE PAGE_OFFSET-1 Kernel module space
Kernel modules inserted via insmod are
placed here using dynamic mappings.
00001000 TASK_SIZE User space mappings
00001000 TASK_SIZE-1 User space mappings
Per-thread mappings are placed here via
the mmap() system call.
......
arch/arm/boot/compressed/head.S
View file @ 1b66a76f
......@@ -86,6 +86,20 @@
.macro writeb, rb
strb \rb, [r3, #0]
.endm
#elif defined(CONFIG_ARCH_OMAP)
.macro loadsp, rb
mov \rb, #0xff000000 @ physical base address
add \rb, \rb, #0x00fb0000
#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
add \rb, \rb, #0x00000800
#endif
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
add \rb, \rb, #0x00009000
#endif
.endm
.macro writeb, rb
strb \rb, [r3]
.endm
#else
#error no serial architecture defined
#endif
......
arch/arm/kernel/signal.c
View file @ 1b66a76f
......@@ -253,6 +253,9 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
goto badframe;
if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->ARM_sp) == -EFAULT)
goto badframe;
/* Send SIGTRAP if we're single-stepping */
if (current->ptrace & PT_SINGLESTEP) {
ptrace_cancel_bpt(current);
......@@ -402,6 +405,7 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
sigset_t *set, struct pt_regs *regs)
{
struct rt_sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame));
stack_t stack;
int err = 0;
if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
......@@ -411,8 +415,14 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
__put_user_error(&frame->uc, &frame->puc, err);
err |= copy_siginfo_to_user(&frame->info, info);
/* Clear all the bits of the ucontext we don't use. */
err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
__put_user_error(0, &frame->uc.uc_flags, err);
__put_user_error(NULL, &frame->uc.uc_link, err);
memset(&stack, 0, sizeof(stack));
stack.ss_sp = (void *)current->sas_ss_sp;
stack.ss_flags = sas_ss_flags(regs->ARM_sp);
stack.ss_size = current->sas_ss_size;
err |= __copy_to_user(&frame->uc.uc_stack, &stack, sizeof(stack));
err |= setup_sigcontext(&frame->uc.uc_mcontext, /*&frame->fpstate,*/
regs, set->sig[0]);
......
arch/arm/lib/Makefile
View file @ 1b66a76f
......@@ -24,7 +24,6 @@ lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
lib-$(CONFIG_ARCH_CLPS7500) += io-acorn.o
lib-$(CONFIG_ARCH_L7200) += io-acorn.o
lib-$(CONFIG_ARCH_SHARK) += io-shark.o
lib-$(CONFIG_ARCH_CLPS711X) += io-acorn.o
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
arch/arm/lib/io-acorn.S
View file @ 1b66a76f
......@@ -17,31 +17,6 @@
.text
.align
.equ diff_pcio_base, PCIO_BASE - IO_BASE
.macro outw2 rd
mov r8, \rd, lsl #16
orr r8, r8, r8, lsr #16
str r8, [r3, r0, lsl #2]
mov r8, \rd, lsr #16
orr r8, r8, r8, lsl #16
str r8, [r3, r0, lsl #2]
.endm
.macro inw2 rd, mask, temp
ldr \rd, [r0]
and \rd, \rd, \mask
ldr \temp, [r0]
orr \rd, \rd, \temp, lsl #16
.endm
.macro addr rd
tst \rd, #0x80000000
mov \rd, \rd, lsl #2
add \rd, \rd, #IO_BASE
addeq \rd, \rd, #diff_pcio_base
.endm
.iosl_warning:
.ascii "<4>insl/outsl not implemented, called from %08lX\0"
.align
......
arch/arm/mach-clps711x/Kconfig
View file @ 1b66a76f
if ARCH_CLPS711X
menu "CLPS711X/EP721X Implementations"
config ARCH_AUTCPU12
bool "AUTCPU12"
depends on ARCH_CLPS711X
help
Say Y if you intend to run the kernel on the autronix autcpu12
board. This board is based on a Cirrus Logic CS89712.
config ARCH_CDB89712
bool "CDB89712"
depends on ARCH_CLPS711X
help
This is an evaluation board from Cirrus for the CS89712 processor.
The board includes 2 serial ports, Ethernet, IRDA, and expansion
......@@ -18,32 +17,27 @@ config ARCH_CDB89712
config ARCH_CEIVA
bool "CEIVA"
depends on ARCH_CLPS711X
help
Say Y here if you intend to run this kernel on the Ceiva/Polaroid
PhotoMax Digital Picture Frame.
config ARCH_CLEP7312
bool "CLEP7312"
depends on ARCH_CLPS711X
config ARCH_EDB7211
bool "EDB7211"
depends on ARCH_CLPS711X
help
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
evaluation board.
config ARCH_P720T
bool "P720T"
depends on ARCH_CLPS711X
help
Say Y here if you intend to run this kernel on the ARM Prospector
720T.
config ARCH_FORTUNET
bool "FORTUNET"
depends on ARCH_CLPS711X
# XXX Maybe these should indicate register compatibility
# instead of being mutually exclusive.
......@@ -74,3 +68,4 @@ config EP72XX_ROM_BOOT
endmenu
endif
arch/arm/mach-epxa10db/Kconfig
View file @ 1b66a76f
if ARCH_CAMELOT
menu "Epxa10db"
comment "PLD hotswap support"
depends on ARCH_CAMELOT
config PLD
bool
depends on ARCH_CAMELOT
default y
config PLD_HOTSWAP
bool "Support for PLD device hotplugging (experimental)"
depends on ARCH_CAMELOT && EXPERIMENTAL
depends on EXPERIMENTAL
help
This enables support for the dynamic loading and configuration of
compatible drivers when the contents of the PLD are changed. This
......@@ -21,3 +20,4 @@ config PLD_HOTSWAP
endmenu
endif
arch/arm/mach-footbridge/Kconfig
View file @ 1b66a76f
if ARCH_FOOTBRIDGE
menu "Footbridge Implementations"
config ARCH_CATS
bool "CATS"
depends on ARCH_FOOTBRIDGE
help
Say Y here if you intend to run this kernel on the CATS.
......@@ -11,7 +11,6 @@ config ARCH_CATS
config ARCH_PERSONAL_SERVER
bool "Compaq Personal Server"
depends on ARCH_FOOTBRIDGE
---help---
Say Y here if you intend to run this kernel on the Compaq
Personal Server.
......@@ -29,7 +28,6 @@ config ARCH_PERSONAL_SERVER
config ARCH_EBSA285_ADDIN
bool "EBSA285 (addin mode)"
depends on ARCH_FOOTBRIDGE
help
Say Y here if you intend to run this kernel on the EBSA285 card
in addin mode.
......@@ -38,7 +36,6 @@ config ARCH_EBSA285_ADDIN
config ARCH_EBSA285_HOST
bool "EBSA285 (host mode)"
depends on ARCH_FOOTBRIDGE
help
Say Y here if you intend to run this kernel on the EBSA285 card
in host ("central function") mode.
......@@ -47,7 +44,6 @@ config ARCH_EBSA285_HOST
config ARCH_NETWINDER
bool "NetWinder"
depends on ARCH_FOOTBRIDGE
help
Say Y here if you intend to run this kernel on the Rebel.COM
NetWinder. Information about this machine can be found at:
......@@ -58,3 +54,4 @@ config ARCH_NETWINDER
endmenu
endif
arch/arm/mach-integrator/Kconfig
View file @ 1b66a76f
if ARCH_INTEGRATOR
menu "Integrator Options"
depends on ARCH_INTEGRATOR
config ARCH_INTEGRATOR_AP
bool "Support Integrator/AP and Integrator/PP2 platforms"
......@@ -28,3 +29,5 @@ config INTEGRATOR_IMPD1
module will be called impd1.
endmenu
endif
arch/arm/mach-iop3xx/Kconfig
View file @ 1b66a76f
if ARCH_IOP3XX
menu "IOP3xx Implementation Options"
choice
prompt "IOP3xx System Type"
default ARCH_IQ80310
depends on ARCH_IOP3XX
config ARCH_IQ80310
bool "IQ80310"
......@@ -36,19 +36,20 @@ comment "IOP3xx Chipset Features"
config IOP3XX_AAU
bool "Support Intel IOP3xx Application Accelerator Unit (EXPERIMENTAL)"
depends on ARCH_IOP3XX && EXPERIMENTAL
depends on EXPERIMENTAL
config IOP3XX_DMA
bool "Support Intel IOP3xx DMA (EXPERIMENTAL)"
depends on ARCH_IOP3XX && EXPERIMENTAL
depends on EXPERIMENTAL
config IOP3XX_MU
bool "Support Intel IOP3xx Messaging Unit (EXPERIMENTAL)"
depends on ARCH_IOP3XX && EXPERIMENTAL
depends on EXPERIMENTAL
config IOP3XX_PMON
bool "Support Intel IOP3xx Performance Monitor (EXPERIMENTAL)"
depends on ARCH_IOP3XX && EXPERIMENTAL
depends on EXPERIMENTAL
endmenu
endif
arch/arm/mach-ixp4xx/Kconfig
View file @ 1b66a76f
if ARCH_IXP4XX
config ARCH_SUPPORTS_BIG_ENDIAN
bool
depends on ARCH_IXP4XX
default y
menu "Intel IXP4xx Implementation Options"
......@@ -10,7 +10,6 @@ comment "IXP4xx Platforms"
config ARCH_AVILA
bool "Avila"
depends on ARCH_IXP4XX
help
Say 'Y' here if you want your kernel to support the Gateworks
Avila Network Platform. For more information on this platform,
......@@ -18,7 +17,6 @@ config ARCH_AVILA
config ARCH_ADI_COYOTE
bool "Coyote"
depends on ARCH_IXP4XX
help
Say 'Y' here if you want your kernel to support the ADI
Engineering Coyote Gateway Reference Platform. For more
......@@ -26,7 +24,6 @@ config ARCH_ADI_COYOTE
config ARCH_IXDP425
bool "IXDP425"
depends on ARCH_IXP4XX
help
Say 'Y' here if you want your kernel to support Intel's
IXDP425 Development Platform (Also known as Richfield).
......@@ -44,7 +41,6 @@ config ARCH_IXCDP1100
config ARCH_PRPMC1100
bool "PrPMC1100"
depends on ARCH_IXP4XX
help
Say 'Y' here if you want your kernel to support the Motorola
PrPCM1100 Processor Mezanine Module. For more information on
......@@ -62,7 +58,6 @@ comment "IXP4xx Options"
config IXP4XX_INDIRECT_PCI
bool "Use indirect PCI memory access"
depends on ARCH_IXP4XX
help
IXP4xx provides two methods of accessing PCI memory space:
......@@ -87,3 +82,5 @@ config IXP4XX_INDIRECT_PCI
what you need, leave this option unselected.
endmenu
endif
arch/arm/mach-lh7a40x/Kconfig
View file @ 1b66a76f
if ARCH_LH7A40X
menu "LH7A40X Implementations"
config MACH_KEV7A400
bool "KEV7A400"
depends on ARCH_LH7A40X
select ARCH_LH7A400
help
Say Y here if you are using the Sharp KEV7A400 development
......@@ -12,9 +12,8 @@ config MACH_KEV7A400
config MACH_LPD7A400
bool "LPD7A400 Card Engine"
depends on ARCH_LH7A40X
select ARCH_LH7A400
select IDE_POLL
# select IDE_POLL
help
Say Y here if you are using Logic Product Development's
LPD7A400 CardEngine. For the time being, the LPD7A400 and
......@@ -22,9 +21,8 @@ config MACH_LPD7A400
config MACH_LPD7A404
bool "LPD7A404 Card Engine"
depends on ARCH_LH7A40X
select ARCH_LH7A404
select IDE_POLL
# select IDE_POLL
help
Say Y here if you are using Logic Product Development's
LPD7A404 CardEngine. For the time being, the LPD7A400 and
......@@ -37,3 +35,5 @@ config ARCH_LH7A404
bool
endmenu
endif
arch/arm/mach-omap/Kconfig
View file @ 1b66a76f
if ARCH_OMAP
menu "TI OMAP Implementations"
comment "OMAP Core Type"
config ARCH_OMAP730
depends on ARCH_OMAP
bool "OMAP730 Based System"
select CPU_ARM926T
config ARCH_OMAP1510
depends on ARCH_OMAP
default y
bool "OMAP1510 Based System"
select CPU_ARM925T
select CPU_DCACHE_WRITETHROUGH
config ARCH_OMAP1610
depends on ARCH_OMAP
bool "OMAP1610 Based System"
select CPU_ARM926T
config ARCH_OMAP5912
depends on ARCH_OMAP
bool "OMAP5912 Based System"
select CPU_ARM926T
......@@ -87,7 +84,6 @@ comment "OMAP Feature Selections"
#config OMAP_BOOT_TAG
# bool "OMAP bootloader information passing"
# depends on ARCH_OMAP
# default n
# help
# Say Y, if you have a bootloader which passes information
......@@ -95,7 +91,6 @@ comment "OMAP Feature Selections"
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
......@@ -113,7 +108,6 @@ config OMAP_MUX_DEBUG
choice
prompt "Low-level debug console UART"
depends on ARCH_OMAP
default OMAP_LL_DEBUG_UART1
config OMAP_LL_DEBUG_UART1
......@@ -171,3 +165,5 @@ config OMAP_ARM_30MHZ
Enable 30MHz clock for OMAP CPU. If unsure, say N.
endmenu
endif
arch/arm/mach-omap/board-generic.c
View file @ 1b66a76f
......@@ -18,6 +18,7 @@
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -64,7 +65,7 @@ static void __init omap_generic_map_io(void)
omap_map_io();
}
MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610")
MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610/1710")
MAINTAINER("Tony Lindgren <tony@atomide.com>")
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
......
arch/arm/mach-omap/board-innovator.c
View file @ 1b66a76f
......@@ -19,8 +19,10 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -36,14 +38,14 @@ extern int omap_gpio_init(void);
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc innovator1510_io_desc[] __initdata = {
{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE,
{ OMAP1510_FPGA_BASE, OMAP1510_FPGA_START, OMAP1510_FPGA_SIZE,
MT_DEVICE },
};
static struct resource innovator1510_smc91x_resources[] = {
[0] = {
.start = OMAP1510P1_FPGA_ETHR_START, /* Physical */
.end = OMAP1510P1_FPGA_ETHR_START + 16,
.start = OMAP1510_FPGA_ETHR_START, /* Physical */
.end = OMAP1510_FPGA_ETHR_START + 16,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -132,12 +134,13 @@ static void __init innovator_map_io(void)
#ifdef CONFIG_ARCH_OMAP1510
if (cpu_is_omap1510()) {
iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
udelay(10); /* Delay needed for FPGA */
/* Dump the Innovator FPGA rev early - useful info for support. */
printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
fpga_read(OMAP1510P1_FPGA_REV_HIGH),
fpga_read(OMAP1510P1_FPGA_REV_LOW),
fpga_read(OMAP1510P1_FPGA_BOARD_REV));
fpga_read(OMAP1510_FPGA_REV_HIGH),
fpga_read(OMAP1510_FPGA_REV_LOW),
fpga_read(OMAP1510_FPGA_BOARD_REV));
}
#endif
#ifdef CONFIG_ARCH_OMAP1610
......
arch/arm/mach-omap/board-osk.c
View file @ 1b66a76f
......@@ -31,6 +31,7 @@
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......
arch/arm/mach-omap/board-perseus2.c
View file @ 1b66a76f
......@@ -3,6 +3,9 @@
*
* Modified from board-generic.c
*
* Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
* Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
......@@ -13,6 +16,7 @@
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -102,7 +106,7 @@ static void __init omap_perseus2_map_io(void)
}
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
MAINTAINER("Kevin Hilman <k-hilman@ti.com>")
MAINTAINER("Kevin Hilman <kjh@hilman.org>")
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
MAPIO(omap_perseus2_map_io)
......
arch/arm/mach-omap/bus.c
View file @ 1b66a76f
......@@ -39,6 +39,7 @@
#include <linux/spinlock.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
......@@ -265,7 +266,7 @@ static void __exit omap_bus_exit(void)
}
}
module_init(omap_bus_init);
postcore_initcall(omap_bus_init);
module_exit(omap_bus_exit);
MODULE_DESCRIPTION("Virtual bus for OMAP");
......
arch/arm/mach-omap/clocks.c
View file @ 1b66a76f
......@@ -84,7 +84,7 @@ static ck_info_t ck_info_table[] = {
}, {
.name = "ck_gen1",
.flags = CK_RATEF | CK_IDLEF,
.rate_reg = CK_DPLL1,
.rate_reg = DPLL_CTL,
.idle_reg = ARM_IDLECT1,
.idle_shift = IDLDPLL_ARM,
.parent = OMAP_CLKIN,
......@@ -629,39 +629,39 @@ init_ck(void)
omap_writew(0x1000, ARM_SYSST);
#if defined(CONFIG_OMAP_ARM_30MHZ)
omap_writew(0x1555, ARM_CKCTL);
omap_writew(0x2290, DPLL_CTL_REG);
omap_writew(0x2290, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_60MHZ)
omap_writew(0x1005, ARM_CKCTL);
omap_writew(0x2290, DPLL_CTL_REG);
omap_writew(0x2290, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_96MHZ)
omap_writew(0x1005, ARM_CKCTL);
omap_writew(0x2410, DPLL_CTL_REG);
omap_writew(0x2410, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_120MHZ)
omap_writew(0x110a, ARM_CKCTL);
omap_writew(0x2510, DPLL_CTL_REG);
omap_writew(0x2510, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_168MHZ)
omap_writew(0x110f, ARM_CKCTL);
omap_writew(0x2710, DPLL_CTL_REG);
omap_writew(0x2710, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_182MHZ) && defined(CONFIG_ARCH_OMAP730)
omap_writew(0x250E, ARM_CKCTL);
omap_writew(0x2710, DPLL_CTL_REG);
omap_writew(0x2710, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_192MHZ) && (defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912))
omap_writew(0x150f, ARM_CKCTL);
if (crystal_type == 2) {
source_clock = 13; /* MHz */
omap_writew(0x2510, DPLL_CTL_REG);
omap_writew(0x2510, DPLL_CTL);
} else
omap_writew(0x2810, DPLL_CTL_REG);
omap_writew(0x2810, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730)
omap_writew(0x250E, ARM_CKCTL);
omap_writew(0x2790, DPLL_CTL_REG);
omap_writew(0x2790, DPLL_CTL);
#else
#error "OMAP MHZ not set, please run make xconfig"
#endif
#ifdef CONFIG_MACH_OMAP_PERSEUS2
/* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL_REG) & ~0x1, OMAP730_PCC_UPLD_CTRL_REG);
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif
/* Turn off some other junk the bootloader might have turned on */
......
arch/arm/mach-omap/common.c
View file @ 1b66a76f
......@@ -23,6 +23,58 @@
#include <asm/arch/board.h>
#include <asm/io.h>
/*
* ----------------------------------------------------------------------------
* OMAP revision check
*
* Since we use the cpu_is_omapnnnn() macros, there's a chance that a board
* switches to an updated core. We want to print out the OMAP revision early.
*
* We use the system_serial registers for the revision information so we
* can see it in /proc/cpuinfo.
*
* If the OMAP detection gets more complicated, we may want to expand this
* to store the OMAP version and replace the current cpu_is_omapnnnn() macros.
*
* ----------------------------------------------------------------------------
*/
static void __init omap_check_revision(void)
{
system_serial_high = omap_readl(OMAP_ID_BASE);
system_serial_low = OMAP_ID_REG;
system_rev = (OMAP_ID_REG >> ID_SHIFT) & ID_MASK;
printk("OMAP revision: %d.%d (0x%08x) id: 0x%08x detected as OMAP-",
(system_serial_high >> 20) & 0xf,
(system_serial_high >> 16) & 0xf,
system_serial_high, system_serial_low);
switch (system_rev) {
case OMAP_ID_730:
printk("730\n");
system_rev = 0x730;
break;
case OMAP_ID_1510:
printk("1510\n");
system_rev = 0x1510;
break;
case OMAP_ID_1610:
printk("1610\n");
system_rev = 0x1610;
break;
case OMAP_ID_1710:
printk("1710\n");
system_rev = 0x1710;
break;
case OMAP_ID_5912:
printk("5912/1611B\n");
system_rev = 0x5912;
break;
default:
printk("unknown, please add support!\n");
}
}
/*
* ----------------------------------------------------------------------------
* OMAP I/O mapping
......@@ -64,7 +116,13 @@ static struct map_desc omap1610_io_desc[] __initdata = {
static struct map_desc omap5912_io_desc[] __initdata = {
{ OMAP5912_DSP_BASE, OMAP5912_DSP_START, OMAP5912_DSP_SIZE, MT_DEVICE },
{ OMAP5912_DSPREG_BASE, OMAP5912_DSPREG_START, OMAP5912_DSPREG_SIZE, MT_DEVICE },
{ OMAP5912_SRAM_BASE, OMAP5912_SRAM_START, OMAP5912_SRAM_SIZE, MT_DEVICE }
/*
* The OMAP5912 has 250kByte internal SRAM. Because the mapping is baseed on page
* size (4kByte), it seems that the last 2kByte (=0x800) of the 250kByte are not mapped.
* Add additional 2kByte (0x800) so that the last page is mapped and the last 2kByte
* can be used.
*/
{ OMAP5912_SRAM_BASE, OMAP5912_SRAM_START, OMAP5912_SRAM_SIZE + 0x800, MT_DEVICE }
};
#endif
......@@ -77,6 +135,7 @@ static void __init _omap_map_io(void)
/* We have to initialize the IO space mapping before we can run
* cpu_is_omapxxx() macros. */
iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
omap_check_revision();
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
......@@ -102,8 +161,8 @@ static void __init _omap_map_io(void)
/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
* on a Posted Write in the TIPB Bridge".
*/
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL_REG);
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL_REG);
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
/* Must init clocks early to assure that timer interrupt works
*/
......
arch/arm/mach-omap/dma.c
View file @ 1b66a76f
......@@ -92,45 +92,124 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
{
u16 w;
w = omap_readw(OMAP_DMA_CSDP_REG(lch));
w = omap_readw(OMAP_DMA_CSDP(lch));
w &= ~0x03;
w |= data_type;
omap_writew(w, OMAP_DMA_CSDP_REG(lch));
omap_writew(w, OMAP_DMA_CSDP(lch));
w = omap_readw(OMAP_DMA_CCR_REG(lch));
w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
w |= 1 << 5;
omap_writew(w, OMAP_DMA_CCR_REG(lch));
omap_writew(w, OMAP_DMA_CCR(lch));
w = omap_readw(OMAP_DMA_CCR2_REG(lch));
w = omap_readw(OMAP_DMA_CCR2(lch));
w &= ~(1 << 2);
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
w |= 1 << 2;
omap_writew(w, OMAP_DMA_CCR2_REG(lch));
omap_writew(w, OMAP_DMA_CCR2(lch));
omap_writew(elem_count, OMAP_DMA_CEN_REG(lch));
omap_writew(frame_count, OMAP_DMA_CFN_REG(lch));
omap_writew(elem_count, OMAP_DMA_CEN(lch));
omap_writew(frame_count, OMAP_DMA_CFN(lch));
}
void omap_set_dma_constant_fill(int lch, u32 color)
{
u16 w;
#ifdef CONFIG_DEBUG_KERNEL
if (omap_dma_in_1510_mode) {
printk(KERN_ERR "OMAP DMA constant fill not available in 1510 mode.");
BUG();
return;
}
#endif
w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
w |= 0x01;
omap_writew(w, OMAP_DMA_CCR2(lch));
omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
w |= 1; /* Channel type G */
omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
}
void omap_set_dma_transparent_copy(int lch, u32 color)
{
u16 w;
#ifdef CONFIG_DEBUG_KERNEL
if (omap_dma_in_1510_mode) {
printk(KERN_ERR "OMAP DMA transparent copy not available in 1510 mode.");
BUG();
}
#endif
w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
w |= 0x02;
omap_writew(w, OMAP_DMA_CCR2(lch));
omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
w |= 1; /* Channel type G */
omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
}
void omap_set_dma_src_params(int lch, int src_port, int src_amode,
unsigned long src_start)
{
u16 w;
w = omap_readw(OMAP_DMA_CSDP_REG(lch));
w = omap_readw(OMAP_DMA_CSDP(lch));
w &= ~(0x1f << 2);
w |= src_port << 2;
omap_writew(w, OMAP_DMA_CSDP_REG(lch));
omap_writew(w, OMAP_DMA_CSDP(lch));
w = omap_readw(OMAP_DMA_CCR_REG(lch));
w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~(0x03 << 12);
w |= src_amode << 12;
omap_writew(w, OMAP_DMA_CCR_REG(lch));
omap_writew(w, OMAP_DMA_CCR(lch));
omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch));
omap_writew(src_start, OMAP_DMA_CSSA_L(lch));
}
void omap_set_dma_src_index(int lch, int eidx, int fidx)
{
omap_writew(eidx, OMAP_DMA_CSEI(lch));
omap_writew(fidx, OMAP_DMA_CSFI(lch));
}
void omap_set_dma_src_data_pack(int lch, int enable)
{
u16 w;
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6);
w |= enable ? (1 << 6) : 0;
omap_writew(w, OMAP_DMA_CSDP(lch));
}
void omap_set_dma_src_burst_mode(int lch, int burst_mode)
{
u16 w;
omap_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch));
omap_writew(src_start, OMAP_DMA_CSSA_L_REG(lch));
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
switch (burst_mode) {
case OMAP_DMA_DATA_BURST_4:
w |= (0x01 << 7);
break;
case OMAP_DMA_DATA_BURST_8:
w |= (0x03 << 7);
break;
default:
printk(KERN_ERR "Invalid DMA burst mode\n");
BUG();
return;
}
omap_writew(w, OMAP_DMA_CSDP(lch));
}
void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
......@@ -138,18 +217,53 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
{
u16 w;
w = omap_readw(OMAP_DMA_CSDP_REG(lch));
w = omap_readw(OMAP_DMA_CSDP(lch));
w &= ~(0x1f << 9);
w |= dest_port << 9;
omap_writew(w, OMAP_DMA_CSDP_REG(lch));
omap_writew(w, OMAP_DMA_CSDP(lch));
w = omap_readw(OMAP_DMA_CCR_REG(lch));
w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~(0x03 << 14);
w |= dest_amode << 14;
omap_writew(w, OMAP_DMA_CCR_REG(lch));
omap_writew(w, OMAP_DMA_CCR(lch));
omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch));
omap_writew(dest_start, OMAP_DMA_CDSA_L(lch));
}
void omap_set_dma_dest_index(int lch, int eidx, int fidx)
{
omap_writew(eidx, OMAP_DMA_CDEI(lch));
omap_writew(fidx, OMAP_DMA_CDFI(lch));
}
void omap_set_dma_dest_data_pack(int lch, int enable)
{
u16 w;
omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch));
omap_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch));
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13);
w |= enable ? (1 << 13) : 0;
omap_writew(w, OMAP_DMA_CSDP(lch));
}
void omap_set_dma_dest_burst_mode(int lch, int burst_mode)
{
u16 w;
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
switch (burst_mode) {
case OMAP_DMA_DATA_BURST_4:
w |= (0x01 << 14);
break;
case OMAP_DMA_DATA_BURST_8:
w |= (0x03 << 14);
break;
default:
printk(KERN_ERR "Invalid DMA burst mode\n");
BUG();
return;
}
omap_writew(w, OMAP_DMA_CSDP(lch));
}
void omap_start_dma(int lch)
......@@ -164,38 +278,38 @@ void omap_start_dma(int lch)
/* Enable the queue, if needed so. */
if (next_lch != -1) {
/* Clear the STOP_LNK bits */
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
w &= ~(1 << 14);
omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(next_lch));
omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL(next_lch));
w &= ~(1 << 14);
omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(next_lch));
omap_writew(w, OMAP_DMA_CLNK_CTRL(next_lch));
/* And set the ENABLE_LNK bits */
omap_writew(next_lch | (1 << 15),
OMAP_DMA_CLNK_CTRL_REG(lch));
OMAP_DMA_CLNK_CTRL(lch));
/* The loop case */
if (dma_chan[next_lch].next_lch == lch)
omap_writew(lch | (1 << 15),
OMAP_DMA_CLNK_CTRL_REG(next_lch));
OMAP_DMA_CLNK_CTRL(next_lch));
/* Read CSR to make sure it's cleared. */
w = omap_readw(OMAP_DMA_CSR_REG(next_lch));
w = omap_readw(OMAP_DMA_CSR(next_lch));
/* Enable some nice interrupts. */
omap_writew(dma_chan[next_lch].enabled_irqs,
OMAP_DMA_CICR_REG(next_lch));
OMAP_DMA_CICR(next_lch));
dma_chan[next_lch].flags |= OMAP_DMA_ACTIVE;
}
}
/* Read CSR to make sure it's cleared. */
w = omap_readw(OMAP_DMA_CSR_REG(lch));
w = omap_readw(OMAP_DMA_CSR(lch));
/* Enable some nice interrupts. */
omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch));
omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch));
w = omap_readw(OMAP_DMA_CCR_REG(lch));
w = omap_readw(OMAP_DMA_CCR(lch));
w |= OMAP_DMA_CCR_EN;
omap_writew(w, OMAP_DMA_CCR_REG(lch));
omap_writew(w, OMAP_DMA_CCR(lch));
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
......@@ -205,12 +319,12 @@ void omap_stop_dma(int lch)
int next_lch;
/* Disable all interrupts on the channel */
omap_writew(0, OMAP_DMA_CICR_REG(lch));
omap_writew(0, OMAP_DMA_CICR(lch));
if (omap_dma_in_1510_mode()) {
w = omap_readw(OMAP_DMA_CCR_REG(lch));
w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~OMAP_DMA_CCR_EN;
omap_writew(w, OMAP_DMA_CCR_REG(lch));
omap_writew(w, OMAP_DMA_CCR(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
return;
}
......@@ -221,16 +335,16 @@ void omap_stop_dma(int lch)
* According to thw HW spec, enabling the STOP_LNK bit
* resets the CCR_EN bit at the same time.
*/
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
w |= (1 << 14);
w = omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(lch));
w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
if (next_lch != -1) {
omap_writew(0, OMAP_DMA_CICR_REG(next_lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(next_lch));
omap_writew(0, OMAP_DMA_CICR(next_lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL(next_lch));
w |= (1 << 14);
w = omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(next_lch));
w = omap_writew(w, OMAP_DMA_CLNK_CTRL(next_lch));
dma_chan[next_lch].flags &= ~OMAP_DMA_ACTIVE;
}
}
......@@ -253,7 +367,7 @@ static int dma_handle_ch(int ch)
csr = dma_chan[ch].saved_csr;
dma_chan[ch].saved_csr = 0;
} else
csr = omap_readw(OMAP_DMA_CSR_REG(ch));
csr = omap_readw(OMAP_DMA_CSR(ch));
if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
dma_chan[ch + 6].saved_csr = csr >> 7;
csr &= 0x7f;
......@@ -339,9 +453,9 @@ int omap_request_dma(int dev_id, const char *dev_name,
}
/* Disable the 1510 compatibility mode and set the sync device
* id. */
omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch));
omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
} else {
omap_writew(dev_id, OMAP_DMA_CCR_REG(free_ch));
omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
}
*dma_ch_out = free_ch;
......@@ -362,9 +476,9 @@ void omap_free_dma(int ch)
spin_unlock_irqrestore(&dma_chan_lock, flags);
/* Disable all DMA interrupts for the channel. */
omap_writew(0, OMAP_DMA_CICR_REG(ch));
omap_writew(0, OMAP_DMA_CICR(ch));
/* Make sure the DMA transfer is stopped. */
omap_writew(0, OMAP_DMA_CCR_REG(ch));
omap_writew(0, OMAP_DMA_CCR(ch));
}
int omap_dma_in_1510_mode(void)
......@@ -601,19 +715,19 @@ static int __init omap_init_dma(void)
enable_1510_mode = 1;
} else if (cpu_is_omap1610() || cpu_is_omap5912()) {
printk(KERN_INFO "OMAP DMA hardware version %d\n",
omap_readw(OMAP_DMA_HW_ID_REG));
omap_readw(OMAP_DMA_HW_ID));
printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
(omap_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_0_L_REG),
(omap_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_1_L_REG),
omap_readw(OMAP_DMA_CAPS_2_REG), omap_readw(OMAP_DMA_CAPS_3_REG),
omap_readw(OMAP_DMA_CAPS_4_REG));
(omap_readw(OMAP_DMA_CAPS_0_U) << 16) | omap_readw(OMAP_DMA_CAPS_0_L),
(omap_readw(OMAP_DMA_CAPS_1_U) << 16) | omap_readw(OMAP_DMA_CAPS_1_L),
omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
omap_readw(OMAP_DMA_CAPS_4));
if (!enable_1510_mode) {
u16 w;
/* Disable OMAP 3.0/3.1 compatibility mode. */
w = omap_readw(OMAP_DMA_GSCR_REG);
w = omap_readw(OMAP_DMA_GSCR);
w |= 1 << 3;
omap_writew(w, OMAP_DMA_GSCR_REG);
omap_writew(w, OMAP_DMA_GSCR);
dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
} else
dma_chan_count = 9;
......@@ -657,9 +771,21 @@ EXPORT_SYMBOL(omap_request_dma);
EXPORT_SYMBOL(omap_free_dma);
EXPORT_SYMBOL(omap_start_dma);
EXPORT_SYMBOL(omap_stop_dma);
EXPORT_SYMBOL(omap_set_dma_transfer_params);
EXPORT_SYMBOL(omap_set_dma_constant_fill);
EXPORT_SYMBOL(omap_set_dma_transparent_copy);
EXPORT_SYMBOL(omap_set_dma_src_params);
EXPORT_SYMBOL(omap_set_dma_src_index);
EXPORT_SYMBOL(omap_set_dma_src_data_pack);
EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
EXPORT_SYMBOL(omap_set_dma_dest_params);
EXPORT_SYMBOL(omap_set_dma_dest_index);
EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
EXPORT_SYMBOL(omap_dma_link_lch);
EXPORT_SYMBOL(omap_dma_unlink_lch);
......
arch/arm/mach-omap/fpga.c
View file @ 1b66a76f
......@@ -46,11 +46,11 @@ static void fpga_mask_irq(unsigned int irq)
irq -= IH_FPGA_BASE;
if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO)
& ~(1 << irq)), OMAP1510P1_FPGA_IMR_LO);
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
& ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
else if (irq < 16)
__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI)
& ~(1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI);
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
& ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
else
__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
& ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
......@@ -60,10 +60,10 @@ static void fpga_mask_irq(unsigned int irq)
static inline u32 get_fpga_unmasked_irqs(void)
{
return
((__raw_readb(OMAP1510P1_FPGA_ISR_LO) &
__raw_readb(OMAP1510P1_FPGA_IMR_LO))) |
((__raw_readb(OMAP1510P1_FPGA_ISR_HI) &
__raw_readb(OMAP1510P1_FPGA_IMR_HI)) << 8) |
((__raw_readb(OMAP1510_FPGA_ISR_LO) &
__raw_readb(OMAP1510_FPGA_IMR_LO))) |
((__raw_readb(OMAP1510_FPGA_ISR_HI) &
__raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
((__raw_readb(INNOVATOR_FPGA_ISR2) &
__raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
}
......@@ -79,11 +79,11 @@ static void fpga_unmask_irq(unsigned int irq)
irq -= IH_FPGA_BASE;
if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO) | (1 << irq)),
OMAP1510P1_FPGA_IMR_LO);
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
OMAP1510_FPGA_IMR_LO);
else if (irq < 16)
__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI)
| (1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI);
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
| (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
else
__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
| (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
......@@ -166,8 +166,8 @@ void fpga_init_irq(void)
{
int i;
__raw_writeb(0, OMAP1510P1_FPGA_IMR_LO);
__raw_writeb(0, OMAP1510P1_FPGA_IMR_HI);
__raw_writeb(0, OMAP1510_FPGA_IMR_LO);
__raw_writeb(0, OMAP1510_FPGA_IMR_HI);
__raw_writeb(0, INNOVATOR_FPGA_IMR2);
for (i = IH_FPGA_BASE; i < (IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
......
arch/arm/mach-omap/gpio.c
View file @ 1b66a76f
......@@ -22,7 +22,6 @@
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pm.h>
#include <asm/mach/irq.h>
#include <asm/io.h>
......@@ -79,7 +78,7 @@
#define OMAP730_GPIO_INT_MASK 0x10
#define OMAP730_GPIO_INT_STATUS 0x14
#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
struct gpio_bank {
u32 base;
......@@ -213,12 +212,12 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
reg += OMAP730_GPIO_DIR_CONTROL;
break;
}
l = omap_readl(reg);
l = __raw_readl(reg);
if (is_input)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
omap_writel(l, reg);
__raw_writel(l, reg);
}
void omap_set_gpio_direction(int gpio, int is_input)
......@@ -240,8 +239,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_OUTPUT_REG;
l = omap_readl(reg);
reg += OMAP_MPUIO_OUTPUT;
l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
......@@ -249,7 +248,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DATA_OUTPUT;
l = omap_readl(reg);
l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
......@@ -264,7 +263,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DATA_OUTPUT;
l = omap_readl(reg);
l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
......@@ -274,7 +273,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
BUG();
return;
}
omap_writel(l, reg);
__raw_writel(l, reg);
}
void omap_set_gpio_dataout(int gpio, int enable)
......@@ -312,7 +311,7 @@ int omap_get_gpio_datain(int gpio)
BUG();
return -1;
}
return (omap_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
}
static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
......@@ -322,22 +321,22 @@ static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_INT_EDGE_REG;
l = omap_readl(reg);
reg += OMAP_MPUIO_GPIO_INT_EDGE;
l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
omap_writel(l, reg);
__raw_writel(l, reg);
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
l = omap_readl(reg);
l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
omap_writel(l, reg);
__raw_writel(l, reg);
break;
case METHOD_GPIO_1610:
edge &= 0x03;
......@@ -346,19 +345,19 @@ static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
else
reg += OMAP1610_GPIO_EDGE_CTRL1;
gpio &= 0x07;
l = omap_readl(reg);
l = __raw_readl(reg);
l &= ~(3 << (gpio << 1));
l |= edge << (gpio << 1);
omap_writel(l, reg);
__raw_writel(l, reg);
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_CONTROL;
l = omap_readl(reg);
l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
omap_writel(l, reg);
__raw_writel(l, reg);
break;
default:
BUG();
......@@ -385,11 +384,11 @@ static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
switch (bank->method) {
case METHOD_MPUIO:
l = omap_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG);
l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
case METHOD_GPIO_1510:
l = omap_readl(reg + OMAP1510_GPIO_INT_CONTROL);
l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
case METHOD_GPIO_1610:
......@@ -397,9 +396,9 @@ static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
reg += OMAP1610_GPIO_EDGE_CTRL2;
else
reg += OMAP1610_GPIO_EDGE_CTRL1;
return (omap_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
case METHOD_GPIO_730:
l = omap_readl(reg + OMAP730_GPIO_INT_CONTROL);
l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
default:
......@@ -430,7 +429,7 @@ static void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
BUG();
return;
}
omap_writel(1 << get_gpio_index(gpio), reg);
__raw_writel(1 << get_gpio_index(gpio), reg);
}
static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
......@@ -441,7 +440,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_MASKIT;
l = omap_readl(reg);
l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
......@@ -449,7 +448,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_MASK;
l = omap_readl(reg);
l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
......@@ -465,7 +464,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_MASK;
l = omap_readl(reg);
l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
......@@ -475,7 +474,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
BUG();
return;
}
omap_writel(l, reg);
__raw_writel(l, reg);
}
int omap_request_gpio(int gpio)
......@@ -500,7 +499,7 @@ int omap_request_gpio(int gpio)
/* Claim the pin for the ARM */
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
omap_writel(omap_readl(reg) | (1 << get_gpio_index(gpio)), reg);
__raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
}
#endif
spin_unlock(&bank->lock);
......@@ -564,7 +563,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
#endif
for (;;) {
u32 isr = omap_readl(isr_reg);
u32 isr = __raw_readl(isr_reg);
unsigned int gpio_irq;
if (!isr)
......@@ -587,15 +586,15 @@ static void gpio_ack_irq(unsigned int irq)
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510)
omap_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
__raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610)
omap_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
__raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730)
omap_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
__raw_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
#endif
}
......@@ -692,26 +691,27 @@ static int __init _omap_gpio_init(void)
bank = &gpio_bank[i];
bank->reserved_map = 0;
bank->base = IO_ADDRESS(bank->base);
spin_lock_init(&bank->lock);
if (bank->method == METHOD_MPUIO) {
omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
}
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510) {
omap_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
omap_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
}
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610) {
omap_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
omap_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
}
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730) {
omap_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
omap_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
__raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
__raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
gpio_count = 32; /* 730 has 32-bit GPIOs */
}
......@@ -730,9 +730,9 @@ static int __init _omap_gpio_init(void)
}
/* Enable system clock for GPIO module.
* The CAM_CLK_CTRL_REG *is* really the right place. */
* The CAM_CLK_CTRL *is* really the right place. */
if (cpu_is_omap1610())
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG);
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
return 0;
}
......@@ -748,8 +748,11 @@ int omap_gpio_init(void)
return 0;
}
EXPORT_SYMBOL(omap_gpio_init);
EXPORT_SYMBOL(omap_request_gpio);
EXPORT_SYMBOL(omap_free_gpio);
EXPORT_SYMBOL(omap_set_gpio_direction);
EXPORT_SYMBOL(omap_set_gpio_dataout);
EXPORT_SYMBOL(omap_get_gpio_datain);
EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
arch_initcall(omap_gpio_init);
arch/arm/mach-omap/irq.c
View file @ 1b66a76f
......@@ -74,9 +74,9 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset)
static void omap_ack_irq(unsigned int irq)
{
if (irq > 31)
omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG);
omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG);
omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
}
static void omap_mask_irq(unsigned int irq)
......@@ -84,9 +84,9 @@ static void omap_mask_irq(unsigned int irq)
int bank = IRQ_BANK(irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR);
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l |= 1 << IRQ_BIT(irq);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_unmask_irq(unsigned int irq)
......@@ -94,9 +94,9 @@ static void omap_unmask_irq(unsigned int irq)
int bank = IRQ_BANK(irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR);
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l &= ~(1 << IRQ_BIT(irq));
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_mask_ack_irq(unsigned int irq)
......@@ -121,7 +121,7 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
/* FIQ is only available on bank 0 interrupts */
fiq = bank ? 0 : (fiq & 0x1);
val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
offset = IRQ_ILR0 + IRQ_BIT(irq) * 0x4;
offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
irq_bank_writel(val, bank, offset);
}
......@@ -182,13 +182,13 @@ void __init omap_init_irq(void)
/* Mask and clear all interrupts */
for (i = 0; i < irq_bank_count; i++) {
irq_bank_writel(~0x0, i, IRQ_MIR);
irq_bank_writel(0x0, i, IRQ_ITR);
irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
}
/* Clear any pending interrupts */
irq_bank_writel(0x03, 0, IRQ_CONTROL_REG);
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG);
irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
/* Install the interrupt handlers for each bank */
for (i = 0; i < irq_bank_count; i++) {
......
arch/arm/mach-omap/ocpi.c
View file @ 1b66a76f
......@@ -85,14 +85,6 @@ int ocpi_enable(void)
val &= ~0xff;
omap_writel(val, OCPI_SEC);
val = omap_readl(OCPI_SEC);
val |= 0;
omap_writel(val, OCPI_SEC);
val = omap_readl(OCPI_SINT0);
val |= 0;
omap_writel(val, OCPI_SINT1);
return 0;
}
EXPORT_SYMBOL(ocpi_enable);
......
arch/arm/mach-pxa/Kconfig
View file @ 1b66a76f
if ARCH_PXA
menu "Intel PXA2xx Implementations"
choice
prompt "Select target board"
depends on ARCH_PXA
config ARCH_LUBBOCK
bool "Intel DBPXA250 Development Platform"
......@@ -32,3 +32,4 @@ config PXA27x
help
Select code specific to PXA27x variants
endif
arch/arm/mach-s3c2410/Kconfig
View file @ 1b66a76f
if ARCH_S3C2410
menu "S3C2410 Implementations"
config ARCH_BAST
bool "Simtec Electronics BAST (EB2410ITX)"
depends on ARCH_S3C2410
help
Say Y here if you are using the Simtec Electronics EB2410ITX
development board (also known as BAST)
......@@ -11,22 +12,21 @@ config ARCH_BAST
config ARCH_H1940
bool "IPAQ H1940"
depends on ARCH_S3C2410
help
Say Y here if you are using the HP IPAQ H1940
<http://www.handhelds.org/projects/h1940.html>.
config ARCH_SMDK2410
bool "SMDK2410/A9M2410"
depends on ARCH_S3C2410
help
Say Y here if you are using the SMDK2410 or the derived module A9M2410
<http://www.fsforth.de>
config MACH_VR1000
bool "Simtec VR1000"
depends on ARCH_S3C2410
help
Say Y here if you are using the Simtec VR1000 board.
endmenu
endif
arch/arm/mach-sa1100/Kconfig
View file @ 1b66a76f
if ARCH_SA1100
menu "SA11x0 Implementations"
config SA1100_ASSABET
bool "Assabet"
depends on ARCH_SA1100
help
Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
Microprocessor Development Board (also known as the Assabet).
......@@ -18,7 +18,6 @@ config ASSABET_NEPONSET
config SA1100_ADSBITSY
bool "ADS Bitsy"
depends on ARCH_SA1100
help
Say Y here if you are using Applied Data Systems Intel(R)
StrongARM(R) 1110 based Bitsy, 3 x 5 inches in size, Compaq - IPAQ -
......@@ -28,14 +27,12 @@ config SA1100_ADSBITSY
config SA1100_BRUTUS
bool "Brutus"
depends on ARCH_SA1100
help
Say Y here if you are using the Intel(R) StrongARM(R) SA-1100
Microprocessor Development Board (also known as the Brutus).
config SA1100_CERF
bool "CerfBoard"
depends on ARCH_SA1100
help
The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued).
More information is available at:
......@@ -62,7 +59,6 @@ endchoice
config SA1100_H3100
bool "Compaq iPAQ H3100"
depends on ARCH_SA1100
help
Say Y here if you intend to run this kernel on the Compaq iPAQ
H3100 handheld computer. Information about this machine and the
......@@ -73,7 +69,6 @@ config SA1100_H3100
config SA1100_H3600
bool "Compaq iPAQ H3600/H3700"
depends on ARCH_SA1100
help
Say Y here if you intend to run this kernel on the Compaq iPAQ
H3600 handheld computer. Information about this machine and the
......@@ -84,7 +79,6 @@ config SA1100_H3600
config SA1100_H3800
bool "Compaq iPAQ H3800"
depends on ARCH_SA1100
help
Say Y here if you intend to run this kernel on the Compaq iPAQ H3800
series handheld computer. Information about this machine and the
......@@ -102,7 +96,6 @@ config SA1100_H3XXX
#dep_bool ' Empeg' CONFIG_SA1100_EMPEG $CONFIG_ARCH_SA1100
config SA1100_EXTENEX1
bool "Extenex HandHeld Theater (Squashtail)"
depends on ARCH_SA1100
config SA1100_EXTENEX1_16MB
bool "Support 16 MB of DRAM (not just 8)"
......@@ -110,7 +103,6 @@ config SA1100_EXTENEX1_16MB
config SA1100_FLEXANET
bool "FlexaNet"
depends on ARCH_SA1100
help
Say Y here if you intend to run this kernel on the FlexaNet
handheld instruments. Information about this machine can be
......@@ -118,14 +110,12 @@ config SA1100_FLEXANET
config SA1100_FREEBIRD
bool "FreeBird-v1.1"
depends on ARCH_SA1100
help
Support the FreeBird board used in Coventive embedded products. See
Documentation/arm/SA1100/Freebird for more.
config SA1100_GRAPHICSCLIENT
bool "GraphicsClient Plus"
depends on ARCH_SA1100
help
Say Y here if you are using an Applied Data Systems Intel(R)
StrongARM(R) SA-1100 based Graphics Client SBC. See
......@@ -133,7 +123,6 @@ config SA1100_GRAPHICSCLIENT
config SA1100_GRAPHICSMASTER
bool "GraphicsMaster"
depends on ARCH_SA1100
help
Say Y here if you are using an Applied Data Systems Intel(R)
StrongARM(R) SA-1100 based Graphics Master SBC with SA-1111
......@@ -143,14 +132,12 @@ config SA1100_GRAPHICSMASTER
config SA1100_BADGE4
bool "HP Labs BadgePAD 4"
depends on ARCH_SA1100
help
Say Y here if you want to build a kernel for the HP Laboratories
BadgePAD 4.
config SA1100_JORNADA720
bool "HP Jornada 720"
depends on ARCH_SA1100
help
Say Y here if you want to build a kernel for the HP Jornada 720
handheld computer. See <http://www.hp.com/jornada/products/720>
......@@ -158,14 +145,12 @@ config SA1100_JORNADA720
config SA1100_HACKKIT
bool "HackKit Core CPU Board"
depends on ARCH_SA1100
help
Say Y here to support the HackKit Core CPU Board
<http://hackkit.eletztrick.de>;
config SA1100_HUW_WEBPANEL
bool "HuW WebPanel"
depends on ARCH_SA1100
help
Say Y here to support the HuW Webpanel produced by Hoeft & Wessel
AG. English-language website is at
......@@ -174,7 +159,6 @@ config SA1100_HUW_WEBPANEL
config SA1100_ITSY
bool "Itsy"
depends on ARCH_SA1100
help
Say Y here if you are using the Compaq Itsy experimental pocket
computer. See <http://research.compaq.com/wrl/projects/itsy/> for
......@@ -182,7 +166,6 @@ config SA1100_ITSY
config SA1100_LART
bool "LART"
depends on ARCH_SA1100
help
Say Y here if you are using the Linux Advanced Radio Terminal
(also known as the LART). See <http://www.lart.tudelft.nl/> for
......@@ -190,7 +173,6 @@ config SA1100_LART
config SA1100_NANOENGINE
bool "nanoEngine"
depends on ARCH_SA1100
help
The nanoEngine is a StrongARM 1110-based single board computer
from Bright Star Engineering. More information is available at:
......@@ -201,14 +183,12 @@ config SA1100_NANOENGINE
config SA1100_OMNIMETER
bool "OmniMeter"
depends on ARCH_SA1100
help
Say Y here if you are using the inhand electronics OmniMeter. See
<http://www.inhandelectronics.com/omnimeter.asp> for details.
config SA1100_PANGOLIN
bool "Pangolin"
depends on ARCH_SA1100
help
Pangolin is a StrongARM 1110-based evaluation platform produced
by Dialogue Technology. It has EISA slots for ease of configuration
......@@ -220,7 +200,6 @@ config SA1100_PANGOLIN
config SA1100_PLEB
bool "PLEB"
depends on ARCH_SA1100
help
Say Y here if you are using a Portable Linux Embedded Board
(also known as PLEB). See <http://www.cse.unsw.edu.au/~pleb/>
......@@ -228,7 +207,6 @@ config SA1100_PLEB
config SA1100_PT_SYSTEM3
bool "PT System 3"
depends on ARCH_SA1100
help
Say Y here if you intend to build a kernel suitable to run on
a Pruftechnik Digital Board. For more information see
......@@ -236,7 +214,6 @@ config SA1100_PT_SYSTEM3
config SA1100_SHANNON
bool "Shannon"
depends on ARCH_SA1100
help
The Shannon (also known as a Tuxscreen, and also as a IS2630) was a
limited edition webphone produced by Philips. The Shannon is a SA1100
......@@ -245,7 +222,6 @@ config SA1100_SHANNON
config SA1100_SHERMAN
bool "Sherman"
depends on ARCH_SA1100
help
Say Y here to support the Blazie Engineering `Sherman' StrongARM
1110-based SBC, used primarily in assistance products for the
......@@ -255,7 +231,6 @@ config SA1100_SHERMAN
config SA1100_SIMPAD
bool "Simpad"
depends on ARCH_SA1100
help
The SIEMENS webpad SIMpad is based on the StrongARM 1110. There
are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB
......@@ -266,7 +241,6 @@ config SA1100_SIMPAD
config SA1100_PFS168
bool "Tulsa"
depends on ARCH_SA1100
help
The Radisys Corp. PFS-168 (aka Tulsa) is an Intel® StrongArm® SA-1110 based
computer which includes the SA-1111 Microprocessor Companion Chip and other
......@@ -276,7 +250,6 @@ config SA1100_PFS168
config SA1100_VICTOR
bool "Victor"
depends on ARCH_SA1100
help
Say Y here if you are using a Visu Aide Intel(R) StrongARM(R)
SA-1100 based Victor Digital Talking Book Reader. See
......@@ -285,14 +258,12 @@ config SA1100_VICTOR
config SA1100_XP860
bool "XP860"
depends on ARCH_SA1100
help
:: Config help missing ::
:: 06 August 2002 ::
config SA1100_YOPY
bool "Yopy"
depends on ARCH_SA1100
help
Say Y here to support the Yopy PDA. Product information at
<http://www.yopy.com/>. See Documentation/arm/SA1100/Yopy
......@@ -300,14 +271,12 @@ config SA1100_YOPY
config SA1100_STORK
bool "Stork"
depends on ARCH_SA1100
help
Say Y here if you intend to run this kernel on the Stork
handheld computer.
#config SA1100_TRIZEPS
# bool "Trizeps"
# depends on ARCH_SA1100
# help
# :: write me ::
......@@ -319,7 +288,6 @@ config SA1100_STORK
config SA1100_SSP
tristate "Generic PIO SSP"
depends on ARCH_SA1100
help
Say Y here to enable support for the generic PIO SSP driver.
This isn't for audio support, but for attached sensors and
......@@ -328,7 +296,6 @@ config SA1100_SSP
config SA1100_USB
tristate "SA1100 USB function support"
depends on ARCH_SA1100
config SA1100_USB_NETLINK
tristate "Support for SA11x0 USB network link function"
......@@ -349,3 +316,4 @@ config H3600_SLEEVE
endmenu
endif
include/asm-arm/arch-omap/board-innovator.h
View file @ 1b66a76f
......@@ -33,74 +33,74 @@
* OMAP-1510 FPGA
* ---------------------------------------------------------------------------
*/
#define OMAP1510P1_FPGA_BASE 0xE8000000 /* Virtual */
#define OMAP1510P1_FPGA_SIZE SZ_4K
#define OMAP1510P1_FPGA_START 0x08000000 /* Physical */
#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */
#define OMAP1510_FPGA_SIZE SZ_4K
#define OMAP1510_FPGA_START 0x08000000 /* Physical */
/* Revision */
#define OMAP1510P1_FPGA_REV_LOW (OMAP1510P1_FPGA_BASE + 0x0)
#define OMAP1510P1_FPGA_REV_HIGH (OMAP1510P1_FPGA_BASE + 0x1)
#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL (OMAP1510P1_FPGA_BASE + 0x2)
#define OMAP1510P1_FPGA_LED_DIGIT (OMAP1510P1_FPGA_BASE + 0x3)
#define INNOVATOR_FPGA_HID_SPI (OMAP1510P1_FPGA_BASE + 0x4)
#define OMAP1510P1_FPGA_POWER (OMAP1510P1_FPGA_BASE + 0x5)
#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
/* Interrupt status */
#define OMAP1510P1_FPGA_ISR_LO (OMAP1510P1_FPGA_BASE + 0x6)
#define OMAP1510P1_FPGA_ISR_HI (OMAP1510P1_FPGA_BASE + 0x7)
#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
/* Interrupt mask */
#define OMAP1510P1_FPGA_IMR_LO (OMAP1510P1_FPGA_BASE + 0x8)
#define OMAP1510P1_FPGA_IMR_HI (OMAP1510P1_FPGA_BASE + 0x9)
#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
/* Reset registers */
#define OMAP1510P1_FPGA_HOST_RESET (OMAP1510P1_FPGA_BASE + 0xa)
#define OMAP1510P1_FPGA_RST (OMAP1510P1_FPGA_BASE + 0xb)
#define OMAP1510P1_FPGA_AUDIO (OMAP1510P1_FPGA_BASE + 0xc)
#define OMAP1510P1_FPGA_DIP (OMAP1510P1_FPGA_BASE + 0xe)
#define OMAP1510P1_FPGA_FPGA_IO (OMAP1510P1_FPGA_BASE + 0xf)
#define OMAP1510P1_FPGA_UART1 (OMAP1510P1_FPGA_BASE + 0x14)
#define OMAP1510P1_FPGA_UART2 (OMAP1510P1_FPGA_BASE + 0x15)
#define OMAP1510P1_FPGA_OMAP1510_STATUS (OMAP1510P1_FPGA_BASE + 0x16)
#define OMAP1510P1_FPGA_BOARD_REV (OMAP1510P1_FPGA_BASE + 0x18)
#define OMAP1510P1_PPT_DATA (OMAP1510P1_FPGA_BASE + 0x100)
#define OMAP1510P1_PPT_STATUS (OMAP1510P1_FPGA_BASE + 0x101)
#define OMAP1510P1_PPT_CONTROL (OMAP1510P1_FPGA_BASE + 0x102)
#define OMAP1510P1_FPGA_TOUCHSCREEN (OMAP1510P1_FPGA_BASE + 0x204)
#define INNOVATOR_FPGA_INFO (OMAP1510P1_FPGA_BASE + 0x205)
#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510P1_FPGA_BASE + 0x206)
#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510P1_FPGA_BASE + 0x207)
#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510P1_FPGA_BASE + 0x208)
#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510P1_FPGA_BASE + 0x209)
#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510P1_FPGA_BASE + 0x20a)
#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510P1_FPGA_BASE + 0x20b)
#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510P1_FPGA_BASE + 0x20c)
#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510P1_FPGA_BASE + 0x20d)
#define INNOVATOR_FPGA_ISR2 (OMAP1510P1_FPGA_BASE + 0x20e)
#define INNOVATOR_FPGA_IMR2 (OMAP1510P1_FPGA_BASE + 0x210)
#define OMAP1510P1_FPGA_ETHR_START (OMAP1510P1_FPGA_START + 0x300)
#define OMAP1510P1_FPGA_ETHR_BASE (OMAP1510P1_FPGA_BASE + 0x300)
#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
#define OMAP1510_FPGA_ETHR_BASE (OMAP1510_FPGA_BASE + 0x300)
/*
* Power up Giga UART driver, turn on HID clock.
* Turn off BT power, since we're not using it and it
* draws power.
*/
#define OMAP1510P1_FPGA_RESET_VALUE 0x42
#define OMAP1510P1_FPGA_PCR_IF_PD0 (1 << 7)
#define OMAP1510P1_FPGA_PCR_COM2_EN (1 << 6)
#define OMAP1510P1_FPGA_PCR_COM1_EN (1 << 5)
#define OMAP1510P1_FPGA_PCR_EXP_PD0 (1 << 4)
#define OMAP1510P1_FPGA_PCR_EXP_PD1 (1 << 3)
#define OMAP1510P1_FPGA_PCR_48MHZ_CLK (1 << 2)
#define OMAP1510P1_FPGA_PCR_4MHZ_CLK (1 << 1)
#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0 (1 << 0)
#define OMAP1510_FPGA_RESET_VALUE 0x42
#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
/*
* Innovator/OMAP1510 FPGA HID register bit definitions
......
include/asm-arm/arch-omap/bus.h
View file @ 1b66a76f
......@@ -72,8 +72,12 @@ struct omap_driver {
* Device ID numbers for bus types
*/
#define OMAP_OCP_DEVID_USB 0
#define OMAP_TIPB_DEVID_OHCI 0
#define OMAP_TIPB_DEVID_LCD 1
#define OMAP_TIPB_DEVID_MMC 2
#define OMAP_TIPB_DEVID_OTG 3
#define OMAP_TIPB_DEVID_UDC 4
/*
* Virtual bus definitions for OMAP
......
include/asm-arm/arch-omap/dma.h
View file @ 1b66a76f
......@@ -33,10 +33,10 @@
#define OMAP_DMA_EXT_NDMA_REQ 5
#define OMAP_DMA_EXT_NDMA_REQ2 6
#define OMAP_DMA_UWIRE_TX 7
#define OMAP_DMA_MCBSP1_DMA_TX 8
#define OMAP_DMA_MCBSP1_DMA_RX 9
#define OMAP_DMA_MCBSP3_DMA_TX 10
#define OMAP_DMA_MCBSP3_DMA_RX 11
#define OMAP_DMA_MCBSP1_TX 8
#define OMAP_DMA_MCBSP1_RX 9
#define OMAP_DMA_MCBSP3_TX 10
#define OMAP_DMA_MCBSP3_RX 11
#define OMAP_DMA_UART1_TX 12
#define OMAP_DMA_UART1_RX 13
#define OMAP_DMA_UART2_TX 14
......@@ -86,75 +86,77 @@
#define OMAP_DMA_CRYPTO_DES_OUT 56
#define OMAP_DMA_BASE 0xfffed800
#define OMAP_DMA_GCR_REG (OMAP_DMA_BASE + 0x400)
#define OMAP_DMA_GSCR_REG (OMAP_DMA_BASE + 0x404)
#define OMAP_DMA_GRST_REG (OMAP_DMA_BASE + 0x408)
#define OMAP_DMA_HW_ID_REG (OMAP_DMA_BASE + 0x442)
#define OMAP_DMA_PCH2_ID_REG (OMAP_DMA_BASE + 0x444)
#define OMAP_DMA_BASE (0xfffed800)
#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
#define OMAP_DMA_CAPS_0_U_REG (OMAP_DMA_BASE + 0x44e)
#define OMAP_DMA_CAPS_0_L_REG (OMAP_DMA_BASE + 0x450)
#define OMAP_DMA_CAPS_1_U_REG (OMAP_DMA_BASE + 0x452)
#define OMAP_DMA_CAPS_1_L_REG (OMAP_DMA_BASE + 0x454)
#define OMAP_DMA_CAPS_2_REG (OMAP_DMA_BASE + 0x456)
#define OMAP_DMA_CAPS_3_REG (OMAP_DMA_BASE + 0x458)
#define OMAP_DMA_CAPS_4_REG (OMAP_DMA_BASE + 0x45a)
#define OMAP_DMA_PCH2_SR_REG (OMAP_DMA_BASE + 0x460)
#define OMAP_DMA_PCH0_SR_REG (OMAP_DMA_BASE + 0x480)
#define OMAP_DMA_PCH1_SR_REG (OMAP_DMA_BASE + 0x482)
#define OMAP_DMA_PCHD_SR_REG (OMAP_DMA_BASE + 0x4c0)
#define OMAP1510_DMA_LCD_CTRL 0xfffedb00
#define OMAP1510_DMA_LCD_TOP_F1_L 0xfffedb02
#define OMAP1510_DMA_LCD_TOP_F1_U 0xfffedb04
#define OMAP1510_DMA_LCD_BOT_F1_L 0xfffedb06
#define OMAP1510_DMA_LCD_BOT_F1_U 0xfffedb08
#define OMAP1610_DMA_LCD_CSDP 0xfffee3c0
#define OMAP1610_DMA_LCD_CCR 0xfffee3c2
#define OMAP1610_DMA_LCD_CTRL 0xfffee3c4
#define OMAP1610_DMA_LCD_TOP_B1_L 0xfffee3c8
#define OMAP1610_DMA_LCD_TOP_B1_U 0xfffee3ca
#define OMAP1610_DMA_LCD_BOT_B1_L 0xfffee3cc
#define OMAP1610_DMA_LCD_BOT_B1_U 0xfffee3ce
#define OMAP1610_DMA_LCD_TOP_B2_L 0xfffee3d0
#define OMAP1610_DMA_LCD_TOP_B2_U 0xfffee3d2
#define OMAP1610_DMA_LCD_BOT_B2_L 0xfffee3d4
#define OMAP1610_DMA_LCD_BOT_B2_U 0xfffee3d6
#define OMAP1610_DMA_LCD_SRC_EI_B1 0xfffee3d8
#define OMAP1610_DMA_LCD_SRC_FI_B1_L 0xfffee3da
#define OMAP1610_DMA_LCD_SRC_EN_B1 0xfffee3e0
#define OMAP1610_DMA_LCD_SRC_FN_B1 0xfffee3e4
#define OMAP1610_DMA_LCD_LCH_CTRL 0xfffee3ea
#define OMAP1610_DMA_LCD_SRC_FI_B1_U 0xfffee3f4
#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
#define OMAP1610_DMA_LCD_BASE (0xfffee300)
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
/* Every LCh has its own set of the registers below */
#define OMAP_DMA_CSDP_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
#define OMAP_DMA_CCR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
#define OMAP_DMA_CICR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
#define OMAP_DMA_CSR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
#define OMAP_DMA_CSSA_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
#define OMAP_DMA_CSSA_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
#define OMAP_DMA_CDSA_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
#define OMAP_DMA_CDSA_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
#define OMAP_DMA_CEN_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
#define OMAP_DMA_CFN_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
#define OMAP_DMA_CSFI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
#define OMAP_DMA_CSEI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
#define OMAP_DMA_CSAC_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
#define OMAP_DMA_CDAC_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
#define OMAP_DMA_CDEI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
#define OMAP_DMA_CDFI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
#define OMAP_DMA_COLOR_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
#define OMAP_DMA_COLOR_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
#define OMAP_DMA_CCR2_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
#define OMAP_DMA_CLNK_CTRL_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
#define OMAP_DMA_LCH_CTRL_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
#define OMAP_DMA_CSDP(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
#define OMAP_DMA_CCR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
#define OMAP_DMA_CICR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
#define OMAP_DMA_CSR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
#define OMAP_DMA_CSSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
#define OMAP_DMA_CSSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
#define OMAP_DMA_CDSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
#define OMAP_DMA_CDSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
#define OMAP_DMA_CEN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
#define OMAP_DMA_CFN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
#define OMAP_DMA_CSFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
#define OMAP_DMA_CSEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
#define OMAP_DMA_CSAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
#define OMAP_DMA_CDAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
#define OMAP_DMA_CDEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
#define OMAP_DMA_CDFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
#define OMAP_DMA_COLOR_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
#define OMAP_DMA_COLOR_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
#define OMAP_DMA_CCR2(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
#define OMAP_DMA_CLNK_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
#define OMAP_DMA_LCH_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
#define OMAP_DMA_TOUT_IRQ (1 << 0)
#define OMAP_DMA_DROP_IRQ (1 << 1)
......@@ -192,6 +194,11 @@ enum {
OMAP_LCD_DMA_B2_BOTTOM
};
enum {
OMAP_DMA_DATA_BURST_4,
OMAP_DMA_DATA_BURST_8
};
extern int omap_request_dma(int dev_id, const char *dev_name,
void (* callback)(int lch, u16 ch_status, void *data),
void *data, int *dma_ch);
......@@ -203,10 +210,20 @@ extern void omap_stop_dma(int lch);
extern void omap_set_dma_transfer_params(int lch, int data_type,
int elem_count, int frame_count,
int sync_mode);
extern void omap_set_dma_constant_fill(int lch, u32 color);
extern void omap_set_dma_transparent_copy(int lch, u32 color);
extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
unsigned long src_start);
extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
extern void omap_set_dma_src_data_pack(int lch, int enable);
extern void omap_set_dma_src_burst_mode(int lch, int burst_mode);
extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
unsigned long dest_start);
extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
extern void omap_set_dma_dest_data_pack(int lch, int enable);
extern void omap_set_dma_dest_burst_mode(int lch, int burst_mode);
extern void omap_dma_link_lch (int lch_head, int lch_queue);
extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
......
include/asm-arm/arch-omap/gpio.h
View file @ 1b66a76f
......@@ -32,18 +32,18 @@
#define OMAP_MPUIO_BASE 0xfffb5000
#define OMAP_MPUIO_INPUT_LATCH 0x00
#define OMAP_MPUIO_OUTPUT_REG 0x04
#define OMAP_MPUIO_OUTPUT 0x04
#define OMAP_MPUIO_IO_CNTL 0x08
#define OMAP_MPUIO_KBR_LATCH 0x10
#define OMAP_MPUIO_KBC_REG 0x14
#define OMAP_MPUIO_GPIO_EVENT_MODE_REG 0x18
#define OMAP_MPUIO_GPIO_INT_EDGE_REG 0x1c
#define OMAP_MPUIO_KBC 0x14
#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
#define OMAP_MPUIO_KBD_INT 0x20
#define OMAP_MPUIO_GPIO_INT 0x24
#define OMAP_MPUIO_KBD_MASKIT 0x28
#define OMAP_MPUIO_GPIO_MASKIT 0x2c
#define OMAP_MPUIO_GPIO_DEBOUNCING_REG 0x30
#define OMAP_MPUIO_LATCH_REG 0x34
#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
#define OMAP_MPUIO_LATCH 0x34
#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
......
include/asm-arm/arch-omap/hardware.h
View file @ 1b66a76f
......@@ -10,6 +10,7 @@
* Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
*
* Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
* and Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -40,49 +41,7 @@
#ifndef __ASSEMBLER__
#include <asm/types.h>
#endif
/*
* ----------------------------------------------------------------------------
* I/O mapping
* ----------------------------------------------------------------------------
*/
#define IO_PHYS 0xFFFB0000
#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
#define IO_VIRT (IO_PHYS - IO_OFFSET)
#define IO_SIZE 0x40000
#define IO_ADDRESS(x) ((x) - IO_OFFSET)
#define PCIO_BASE 0
#define io_p2v(x) ((x) - IO_OFFSET)
#define io_v2p(x) ((x) + IO_OFFSET)
#ifndef __ASSEMBLER__
/* 16 bit uses LDRH/STRH, base +/- offset_8 */
typedef struct { volatile u16 offset[256]; } __regbase16;
#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
->offset[((vaddr)&0xff)>>1]
#define __REG16(paddr) __REGV16(io_p2v(paddr))
/* 8/32 bit uses LDR/STR, base +/- offset_12 */
typedef struct { volatile u8 offset[4096]; } __regbase8;
#define __REGV8(vaddr) ((__regbase8 *)((paddr)&~4095)) \
->offset[((paddr)&4095)>>0]
#define __REG8(paddr) __REGV8(io_p2v(paddr))
typedef struct { volatile u32 offset[4096]; } __regbase32;
#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
->offset[((vaddr)&4095)>>2]
#define __REG32(paddr) __REGV32(io_p2v(paddr))
#else
#define __REG8(paddr) io_p2v(paddr)
#define __REG16(paddr) io_p2v(paddr)
#define __REG32(paddr) io_p2v(paddr)
#endif
#include <asm/arch/io.h>
/*
* ---------------------------------------------------------------------------
......@@ -97,14 +56,14 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
* Clocks
* ----------------------------------------------------------------------------
*/
#define CLKGEN_RESET_BASE (0xfffece00)
#define ARM_CKCTL (CLKGEN_RESET_BASE + 0x0)
#define ARM_IDLECT1 (CLKGEN_RESET_BASE + 0x4)
#define ARM_IDLECT2 (CLKGEN_RESET_BASE + 0x8)
#define ARM_EWUPCT (CLKGEN_RESET_BASE + 0xC)
#define ARM_RSTCT1 (CLKGEN_RESET_BASE + 0x10)
#define ARM_RSTCT2 (CLKGEN_RESET_BASE + 0x14)
#define ARM_SYSST (CLKGEN_RESET_BASE + 0x18)
#define CLKGEN_REG_BASE (0xfffece00)
#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
#define CK_RATEF 1
#define CK_IDLEF 2
......@@ -113,19 +72,27 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
#define SETARM_IDLE_SHIFT
/* DPLL control registers */
#define DPLL_CTL_REG (0xfffecf00)
#define CK_DPLL1 (0xfffecf00)
#define DPLL_CTL (0xfffecf00)
/* ULPD */
/* DSP clock control */
#define DSP_CONFIG_REG_BASE (0xe1008000)
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
/*
* ---------------------------------------------------------------------------
* UPLD
* ---------------------------------------------------------------------------
*/
#define ULPD_REG_BASE (0xfffe0800)
#define ULPD_IT_STATUS_REG (ULPD_REG_BASE + 0x14)
#define ULPD_CLOCK_CTRL_REG (ULPD_REG_BASE + 0x30)
#define ULPD_SOFT_REQ_REG (ULPD_REG_BASE + 0x34)
#define ULPD_DPLL_CTRL_REG (ULPD_REG_BASE + 0x3c)
#define ULPD_STATUS_REQ_REG (ULPD_REG_BASE + 0x40)
#define ULPD_APLL_CTRL_REG (ULPD_REG_BASE + 0x4c)
#define ULPD_POWER_CTRL_REG (ULPD_REG_BASE + 0x50)
#define ULPD_CAM_CLK_CTRL_REG (ULPD_REG_BASE + 0x7c)
#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
/*
* ---------------------------------------------------------------------------
......@@ -146,18 +113,24 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
#define TIMER32k_ARL (1<<3)
/* MPU Timer base addresses */
#define OMAP_MPUTIMER_BASE 0xfffec500
#define OMAP_MPUTIMER_OFF 0x00000100
#define OMAP_TIMER1_BASE 0xfffec500
#define OMAP_TIMER2_BASE 0xfffec600
#define OMAP_TIMER3_BASE 0xfffec700
#define OMAP_WATCHDOG_BASE 0xfffec800
#define OMAP_TIMER1_BASE (0xfffec500)
#define OMAP_TIMER2_BASE (0xfffec600)
#define OMAP_TIMER3_BASE (0xfffec700)
#define OMAP_MPUTIMER_BASE OMAP_TIMER1_BASE
#define OMAP_MPUTIMER_OFFSET 0x100
/* MPU Timer Registers */
#define CNTL_TIMER 0
#define LOAD_TIM 4
#define READ_TIM 8
#define OMAP_TIMER1_CNTL (OMAP_TIMER_BASE1 + 0x0)
#define OMAP_TIMER1_LOAD_TIM (OMAP_TIMER_BASE1 + 0x4)
#define OMAP_TIMER1_READ_TIM (OMAP_TIMER_BASE1 + 0x8)
#define OMAP_TIMER2_CNTL (OMAP_TIMER_BASE2 + 0x0)
#define OMAP_TIMER2_LOAD_TIM (OMAP_TIMER_BASE2 + 0x4)
#define OMAP_TIMER2_READ_TIM (OMAP_TIMER_BASE2 + 0x8)
#define OMAP_TIMER3_CNTL (OMAP_TIMER_BASE3 + 0x0)
#define OMAP_TIMER3_LOAD_TIM (OMAP_TIMER_BASE3 + 0x4)
#define OMAP_TIMER3_READ_TIM (OMAP_TIMER_BASE3 + 0x8)
/* CNTL_TIMER register bits */
#define MPUTIM_FREE (1<<6)
......@@ -167,6 +140,13 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
#define MPUTIM_AR (1<<1)
#define MPUTIM_ST (1<<0)
/* Watchdog */
#define OMAP_WATCHDOG_BASE (0xfffec800)
#define OMAP_WDT_TIMER (OMAP_WATCHDOG_BASE + 0x0)
#define OMAP_WDT_LOAD_TIM (OMAP_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_READ_TIM (OMAP_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_TIMER_MODE (OMAP_WATCHDOG_BASE + 0x8)
/*
* ---------------------------------------------------------------------------
* Interrupts
......@@ -174,22 +154,30 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
*/
#define OMAP_IH1_BASE 0xfffecb00
#define OMAP_IH2_BASE 0xfffe0000
#define OMAP_ITR 0x0
#define OMAP_MASK 0x4
#define IRQ_ITR 0x00
#define IRQ_MIR 0x04
#define IRQ_SIR_IRQ 0x10
#define IRQ_SIR_FIQ 0x14
#define IRQ_CONTROL_REG 0x18
#define IRQ_ISR 0x9c
#define IRQ_ILR0 0x1c
/* OMAP-1610 specific interrupt handler registers */
#define OMAP_IH2_SECT1 (OMAP_IH2_BASE)
#define OMAP_IH2_SECT2 (OMAP_IH2_BASE + 0x100)
#define OMAP_IH2_SECT3 (OMAP_IH2_BASE + 0x200)
#define OMAP_IH2_SECT4 (OMAP_IH2_BASE + 0x300)
#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
#define IRQ_ITR_REG_OFFSET 0x00
#define IRQ_MIR_REG_OFFSET 0x04
#define IRQ_SIR_IRQ_REG_OFFSET 0x10
#define IRQ_SIR_FIQ_REG_OFFSET 0x14
#define IRQ_CONTROL_REG_OFFSET 0x18
#define IRQ_ISR_REG_OFFSET 0x9c
#define IRQ_ILR0_REG_OFFSET 0x1c
/*
* ---------------------------------------------------------------------------
......@@ -198,9 +186,9 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
*/
#define TCMIF_BASE 0xfffecc00
#define IMIF_PRIO (TCMIF_BASE + 0x00)
#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04)
#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08)
#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c)
#define EMIFS_PRIO (TCMIF_BASE + 0x04)
#define EMIFF_PRIO (TCMIF_BASE + 0x08)
#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
......@@ -213,7 +201,6 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
#define TC_ENDIANISM (TCMIF_BASE + 0x34)
#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
/*
* ----------------------------------------------------------------------------
* System control registers
......@@ -265,25 +252,24 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
* ---------------------------------------------------------------------------
*/
#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8)
#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8)
#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
/*
* ----------------------------------------------------------------------------
* DSP control registers
* MPUI interface
* ----------------------------------------------------------------------------
*/
/* MPUI Interface Registers */
#define MPUI_CTRL_REG (0xfffec900)
#define MPUI_DEBUG_ADDR (0xfffec904)
#define MPUI_DEBUG_DATA (0xfffec908)
#define MPUI_DEBUG_FLAG (0xfffec90c)
#define MPUI_STATUS_REG (0xfffec910)
#define MPUI_DSP_STATUS_REG (0xfffec914)
#define MPUI_DSP_BOOT_CONFIG (0xfffec918)
#define MPUI_DSP_API_CONFIG (0xfffec91c)
#define MPUI_BASE (0xfffec900)
#define MPUI_CTRL (MPUI_BASE + 0x0)
#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
#ifndef __ASSEMBLER__
......@@ -292,34 +278,38 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
* Processor differentiation
* ---------------------------------------------------------------------------
*/
#define OMAP_ID_REG __REG32(0xfffed404)
#define OMAP_ID_BASE (0xfffed400)
#define OMAP_ID_REG __REG32(OMAP_ID_BASE + 0x04)
#define ID_SHIFT 12
#define ID_MASK 0x7fff
/* See also uncompress.h */
#define OMAP_ID_730 0xB55F
#define OMAP_ID_1510 0xB470
#define OMAP_ID_1610 0xB576
#define OMAP_ID_1710 0xB5F7
#define OMAP_ID_5912 0xB58C
#define OMAP_ID_730 0x355F
#define OMAP_ID_1510 0x3470
#define OMAP_ID_1610 0x3576
#define OMAP_ID_1710 0x35F7
#define OMAP_ID_5912 0x358C
#ifdef CONFIG_ARCH_OMAP730
#include "omap730.h"
#define cpu_is_omap730() (((OMAP_ID_REG >> 12) & 0xffff) == OMAP_ID_730)
#define cpu_is_omap730() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_730)
#else
#define cpu_is_omap730() 0
#endif
#ifdef CONFIG_ARCH_OMAP1510
#include "omap1510.h"
#define cpu_is_omap1510() (((OMAP_ID_REG >> 12) & 0xffff) == OMAP_ID_1510)
#define cpu_is_omap1510() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1510)
#else
#define cpu_is_omap1510() 0
#endif
#ifdef CONFIG_ARCH_OMAP1610
#include "omap1610.h"
#define cpu_is_omap1710() (((OMAP_ID_REG >> 12) & 0xffff) == OMAP_ID_1710)
#define cpu_is_omap1710() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710)
/* Detect 1710 as 1610 for now */
#define cpu_is_omap1610() (((OMAP_ID_REG >> 12) & 0xffff) == OMAP_ID_1610 \
#define cpu_is_omap1610() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610 \
|| cpu_is_omap1710())
#else
#define cpu_is_omap1610() 0
......@@ -328,7 +318,7 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
#ifdef CONFIG_ARCH_OMAP5912
#include "omap5912.h"
#define cpu_is_omap5912() (((OMAP_ID_REG >> 12) & 0xffff) == OMAP_ID_5912)
#define cpu_is_omap5912() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_5912)
#else
#define cpu_is_omap5912() 0
#endif
......
include/asm-arm/arch-omap/io.h
View file @ 1b66a76f
/*
* linux/include/asm-arm/arch-omap/io.h
*
* IO definitions for TI OMAP processors and boards
*
* Copied from linux/include/asm-arm/arch-sa1100/io.h
* Copyright (C) 1997-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Modifications:
* 06-12-1997 RMK Created.
* 07-04-1999 RMK Major cleanup
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
......@@ -21,6 +44,24 @@
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
/*
* ----------------------------------------------------------------------------
* I/O mapping
* ----------------------------------------------------------------------------
*/
#define IO_PHYS 0xFFFB0000
#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
#define IO_VIRT (IO_PHYS - IO_OFFSET)
#define IO_SIZE 0x40000
#define IO_ADDRESS(x) ((x) - IO_OFFSET)
#define PCIO_BASE 0
#define io_p2v(x) ((x) - IO_OFFSET)
#define io_v2p(x) ((x) + IO_OFFSET)
#ifndef __ASSEMBLER__
/*
* Functions to access the OMAP IO region
*
......@@ -38,4 +79,29 @@
#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
/* 16 bit uses LDRH/STRH, base +/- offset_8 */
typedef struct { volatile u16 offset[256]; } __regbase16;
#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
->offset[((vaddr)&0xff)>>1]
#define __REG16(paddr) __REGV16(io_p2v(paddr))
/* 8/32 bit uses LDR/STR, base +/- offset_12 */
typedef struct { volatile u8 offset[4096]; } __regbase8;
#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
->offset[((vaddr)&4095)>>0]
#define __REG8(paddr) __REGV8(io_p2v(paddr))
typedef struct { volatile u32 offset[4096]; } __regbase32;
#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
->offset[((vaddr)&4095)>>2]
#define __REG32(paddr) __REGV32(io_p2v(paddr))
#else
#define __REG8(paddr) io_p2v(paddr)
#define __REG16(paddr) io_p2v(paddr)
#define __REG32(paddr) io_p2v(paddr)
#endif
#endif
include/asm-arm/arch-omap/mux.h
View file @ 1b66a76f
......@@ -140,16 +140,20 @@ typedef enum {
R18_1510_USB_GPIO0,
W4_USB_PUEN,
W4_USB_CLKO,
W4_USB_HIGHZ,
W4_GPIO58,
/* USB1 master */
USB1_SUSP,
USB1_SEO,
W13_1610_USB1_SE0,
USB1_TXEN,
USB1_TXD,
USB1_VP,
USB1_VM,
USB1_RCV,
USB1_SPEED,
R13_1610_USB1_SPEED,
/* USB2 master */
USB2_SUSP,
......@@ -216,6 +220,7 @@ typedef enum {
/* OMAP-1610 GPIO */
P20_1610_GPIO4,
V9_1610_GPIO7,
W8_1610_GPIO9,
N19_1610_GPIO13,
P10_1610_GPIO22,
V5_1610_GPIO24,
......@@ -317,16 +322,20 @@ MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
MUX_CFG("W4_USB_PUEN", D, 3, 0, 3, 5, 1, NA, 0, 1)
MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
/* USB1 master */
MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
/* USB2 master */
MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
......@@ -394,6 +403,7 @@ MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
/* OMAP-1610 GPIO */
MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
......@@ -405,7 +415,7 @@ MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, NA, 0, 0, NA, 0, 0)
MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
/* First MMC interface, same on 1510 and 1610 */
MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
......
include/asm-arm/arch-omap/omap-h2.h deleted 100644 → 0
View file @ 56d1317d
/*
* linux/include/asm-arm/arch-omap/omap-h2.h
*
* Hardware definitions for TI OMAP1610 H2 board.
*
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_H2_H
#define __ASM_ARCH_OMAP_H2_H
/* Placeholder for H2 specific defines */
#endif /* __ASM_ARCH_OMAP_H2_H */
include/asm-arm/arch-omap/omap-innovator.h deleted 100644 → 0
View file @ 56d1317d
/*
* linux/include/asm-arm/arch-omap/omap-innovator.h
*
* Copyright (C) 2001 RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
#define __ASM_ARCH_OMAP_INNOVATOR_H
#if defined (CONFIG_ARCH_OMAP1510)
/*
* ---------------------------------------------------------------------------
* OMAP-1510 FPGA
* ---------------------------------------------------------------------------
*/
#define OMAP1510P1_FPGA_BASE 0xE8000000 /* Virtual */
#define OMAP1510P1_FPGA_SIZE SZ_4K
#define OMAP1510P1_FPGA_START 0x08000000 /* Physical */
/* Revision */
#define OMAP1510P1_FPGA_REV_LOW (OMAP1510P1_FPGA_BASE + 0x0)
#define OMAP1510P1_FPGA_REV_HIGH (OMAP1510P1_FPGA_BASE + 0x1)
#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL (OMAP1510P1_FPGA_BASE + 0x2)
#define OMAP1510P1_FPGA_LED_DIGIT (OMAP1510P1_FPGA_BASE + 0x3)
#define INNOVATOR_FPGA_HID_SPI (OMAP1510P1_FPGA_BASE + 0x4)
#define OMAP1510P1_FPGA_POWER (OMAP1510P1_FPGA_BASE + 0x5)
/* Interrupt status */
#define OMAP1510P1_FPGA_ISR_LO (OMAP1510P1_FPGA_BASE + 0x6)
#define OMAP1510P1_FPGA_ISR_HI (OMAP1510P1_FPGA_BASE + 0x7)
/* Interrupt mask */
#define OMAP1510P1_FPGA_IMR_LO (OMAP1510P1_FPGA_BASE + 0x8)
#define OMAP1510P1_FPGA_IMR_HI (OMAP1510P1_FPGA_BASE + 0x9)
/* Reset registers */
#define OMAP1510P1_FPGA_HOST_RESET (OMAP1510P1_FPGA_BASE + 0xa)
#define OMAP1510P1_FPGA_RST (OMAP1510P1_FPGA_BASE + 0xb)
#define OMAP1510P1_FPGA_AUDIO (OMAP1510P1_FPGA_BASE + 0xc)
#define OMAP1510P1_FPGA_DIP (OMAP1510P1_FPGA_BASE + 0xe)
#define OMAP1510P1_FPGA_FPGA_IO (OMAP1510P1_FPGA_BASE + 0xf)
#define OMAP1510P1_FPGA_UART1 (OMAP1510P1_FPGA_BASE + 0x14)
#define OMAP1510P1_FPGA_UART2 (OMAP1510P1_FPGA_BASE + 0x15)
#define OMAP1510P1_FPGA_OMAP1510_STATUS (OMAP1510P1_FPGA_BASE + 0x16)
#define OMAP1510P1_FPGA_BOARD_REV (OMAP1510P1_FPGA_BASE + 0x18)
#define OMAP1510P1_PPT_DATA (OMAP1510P1_FPGA_BASE + 0x100)
#define OMAP1510P1_PPT_STATUS (OMAP1510P1_FPGA_BASE + 0x101)
#define OMAP1510P1_PPT_CONTROL (OMAP1510P1_FPGA_BASE + 0x102)
#define OMAP1510P1_FPGA_TOUCHSCREEN (OMAP1510P1_FPGA_BASE + 0x204)
#define INNOVATOR_FPGA_INFO (OMAP1510P1_FPGA_BASE + 0x205)
#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510P1_FPGA_BASE + 0x206)
#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510P1_FPGA_BASE + 0x207)
#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510P1_FPGA_BASE + 0x208)
#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510P1_FPGA_BASE + 0x209)
#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510P1_FPGA_BASE + 0x20a)
#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510P1_FPGA_BASE + 0x20b)
#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510P1_FPGA_BASE + 0x20c)
#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510P1_FPGA_BASE + 0x20d)
#define INNOVATOR_FPGA_ISR2 (OMAP1510P1_FPGA_BASE + 0x20e)
#define INNOVATOR_FPGA_IMR2 (OMAP1510P1_FPGA_BASE + 0x210)
#define OMAP1510P1_FPGA_ETHR_START (OMAP1510P1_FPGA_START + 0x300)
#define OMAP1510P1_FPGA_ETHR_BASE (OMAP1510P1_FPGA_BASE + 0x300)
/*
* Power up Giga UART driver, turn on HID clock.
* Turn off BT power, since we're not using it and it
* draws power.
*/
#define OMAP1510P1_FPGA_RESET_VALUE 0x42
#define OMAP1510P1_FPGA_PCR_IF_PD0 (1 << 7)
#define OMAP1510P1_FPGA_PCR_COM2_EN (1 << 6)
#define OMAP1510P1_FPGA_PCR_COM1_EN (1 << 5)
#define OMAP1510P1_FPGA_PCR_EXP_PD0 (1 << 4)
#define OMAP1510P1_FPGA_PCR_EXP_PD1 (1 << 3)
#define OMAP1510P1_FPGA_PCR_48MHZ_CLK (1 << 2)
#define OMAP1510P1_FPGA_PCR_4MHZ_CLK (1 << 1)
#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0 (1 << 0)
/*
* Innovator/OMAP1510 FPGA HID register bit definitions
*/
#define FPGA_HID_SCLK (1<<0) /* output */
#define FPGA_HID_MOSI (1<<1) /* output */
#define FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
#define FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
#define FPGA_HID_MISO (1<<4) /* input */
#define FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
#define FPGA_HID_rsrvd (1<<6)
#define FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
#ifndef OMAP_SDRAM_DEVICE
#define OMAP_SDRAM_DEVICE D256M_1X16_4B
#endif
#define OMAP1510P1_IMIF_PRI_VALUE 0x00
#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
/*
* These definitions define an area of FLASH set aside
* for the use of MTD/JFFS2. This is the area of flash
* that a JFFS2 filesystem will reside which is mounted
* at boot with the "root=/dev/mtdblock/0 rw"
* command line option. The flash address used here must
* fall within the legal range defined by rrload for storing
* the filesystem component. This address will be sufficiently
* deep into the overall flash range to avoid the other
* components also stored in flash such as the bootloader,
* the bootloader params, and the kernel.
* The SW2 settings for the map below are:
* 1 off, 2 off, 3 on, 4 off.
*/
/* Intel flash_0, partitioned as expected by rrload */
#define OMAP_FLASH_0_BASE 0xD8000000
#define OMAP_FLASH_0_START 0x00000000
#define OMAP_FLASH_0_SIZE SZ_16M
/* Intel flash_1, used for cramfs or other flash file systems */
#define OMAP_FLASH_1_BASE 0xD9000000
#define OMAP_FLASH_1_START 0x01000000
#define OMAP_FLASH_1_SIZE SZ_16M
/* The FPGA IRQ is cascaded through GPIO_13 */
#define INT_FPGA (IH_GPIO_BASE + 13)
/* IRQ Numbers for interrupts muxed through the FPGA */
#define IH_FPGA_BASE IH_BOARD_BASE
#define INT_FPGA_ATN (IH_FPGA_BASE + 0)
#define INT_FPGA_ACK (IH_FPGA_BASE + 1)
#define INT_FPGA2 (IH_FPGA_BASE + 2)
#define INT_FPGA3 (IH_FPGA_BASE + 3)
#define INT_FPGA4 (IH_FPGA_BASE + 4)
#define INT_FPGA5 (IH_FPGA_BASE + 5)
#define INT_FPGA6 (IH_FPGA_BASE + 6)
#define INT_FPGA7 (IH_FPGA_BASE + 7)
#define INT_FPGA8 (IH_FPGA_BASE + 8)
#define INT_FPGA9 (IH_FPGA_BASE + 9)
#define INT_FPGA10 (IH_FPGA_BASE + 10)
#define INT_FPGA11 (IH_FPGA_BASE + 11)
#define INT_FPGA12 (IH_FPGA_BASE + 12)
#define INT_ETHER (IH_FPGA_BASE + 13)
#define INT_FPGAUART1 (IH_FPGA_BASE + 14)
#define INT_FPGAUART2 (IH_FPGA_BASE + 15)
#define INT_FPGA_TS (IH_FPGA_BASE + 16)
#define INT_FPGA17 (IH_FPGA_BASE + 17)
#define INT_FPGA_CAM (IH_FPGA_BASE + 18)
#define INT_FPGA_RTC_A (IH_FPGA_BASE + 19)
#define INT_FPGA_RTC_B (IH_FPGA_BASE + 20)
#define INT_FPGA_CD (IH_FPGA_BASE + 21)
#define INT_FPGA22 (IH_FPGA_BASE + 22)
#define INT_FPGA23 (IH_FPGA_BASE + 23)
#define NR_FPGA_IRQS 24
#define MAXIRQNUM (IH_FPGA_BASE + NR_FPGA_IRQS - 1)
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS 256
#ifndef __ASSEMBLY__
void fpga_write(unsigned char val, int reg);
unsigned char fpga_read(int reg);
#endif
#elif defined (CONFIG_ARCH_OMAP1610)
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_BASE 0xE8000000
#define OMAP1610_ETHR_SIZE SZ_4K
#define OMAP1610_ETHR_START 0x04000000
/* Intel STRATA NOR flash at CS3 */
#define OMAP1610_NOR_FLASH_BASE 0xD8000000
#define OMAP1610_NOR_FLASH_SIZE SZ_32M
#define OMAP1610_NOR_FLASH_START 0x0C000000
#define MAXIRQNUM (IH_BOARD_BASE)
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS (MAXIRQNUM + 1)
#else
#error "Only OMAP1510 and OMAP1610 Innovator supported!"
#endif
#endif
include/asm-arm/arch-omap/omap-perseus2.h deleted 100644 → 0
View file @ 56d1317d
/*
* linux/include/asm-arm/arch-omap/omap-perseus2.h
*
* Copyright 2003 by Texas Instruments Incorporated
* OMAP730 / P2-sample additions
* Author: Jean Pihet
*
* Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
* Author: RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H
#define __ASM_ARCH_OMAP_P2SAMPLE_H
#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2)
/*
* NOTE: ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER
* P2SAMPLE_ since they are specific to the EVM and not the chip.
*/
/* ---------------------------------------------------------------------------
* OMAP730 Debug Board FPGA
* ---------------------------------------------------------------------------
*
*/
/* maps in the FPGA registers and the ETHR registers */
#define OMAP730_FPGA_BASE 0xE8000000 /* VA */
#define OMAP730_FPGA_SIZE SZ_4K /* SIZE */
#define OMAP730_FPGA_START 0x04000000 /* PA */
#define OMAP730_FPGA_ETHR_START OMAP730_FPGA_START
#define OMAP730_FPGA_ETHR_BASE OMAP730_FPGA_BASE
#define OMAP730_FPGA_FPGA_REV (OMAP730_FPGA_BASE + 0x10) /* FPGA Revision */
#define OMAP730_FPGA_BOARD_REV (OMAP730_FPGA_BASE + 0x12) /* Board Revision */
#define OMAP730_FPGA_GPIO (OMAP730_FPGA_BASE + 0x14) /* GPIO outputs */
#define OMAP730_FPGA_LEDS (OMAP730_FPGA_BASE + 0x16) /* LEDs outputs */
#define OMAP730_FPGA_MISC_INPUTS (OMAP730_FPGA_BASE + 0x18) /* Misc inputs */
#define OMAP730_FPGA_LAN_STATUS (OMAP730_FPGA_BASE + 0x1A) /* LAN Status line */
#define OMAP730_FPGA_LAN_RESET (OMAP730_FPGA_BASE + 0x1C) /* LAN Reset line */
// LEDs definition on debug board (16 LEDs)
#define OMAP730_FPGA_LED_CLAIMRELEASE (1 << 15)
#define OMAP730_FPGA_LED_STARTSTOP (1 << 14)
#define OMAP730_FPGA_LED_HALTED (1 << 13)
#define OMAP730_FPGA_LED_IDLE (1 << 12)
#define OMAP730_FPGA_LED_TIMER (1 << 11)
// cpu0 load-meter LEDs
#define OMAP730_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
#define OMAP730_FPGA_LOAD_METER_SIZE 11
#define OMAP730_FPGA_LOAD_METER_MASK ((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1)
#ifndef OMAP_SDRAM_DEVICE
#define OMAP_SDRAM_DEVICE D256M_1X16_4B
#endif
/*
* These definitions define an area of FLASH set aside
* for the use of MTD/JFFS2. This is the area of flash
* that a JFFS2 filesystem will reside which is mounted
* at boot with the "root=/dev/mtdblock/0 rw"
* command line option.
*/
/* Intel flash_0, partitioned as expected by rrload */
#define OMAP_FLASH_0_BASE 0xD8000000 /* VA */
#define OMAP_FLASH_0_START 0x00000000 /* PA */
#define OMAP_FLASH_0_SIZE SZ_32M
/* 2.9.6 Traffic Controller Memory Interface Registers */
#define OMAP_FLASH_CFG_0 0xfffecc10
#define OMAP_FLASH_ACFG_0 0xfffecc50
#define OMAP_FLASH_CFG_1 0xfffecc14
#define OMAP_FLASH_ACFG_1 0xfffecc54
/*
* Configuration Registers
*/
#define PERSEUS2_CONFIG_BASE 0xfffe1000
#define PERSEUS2_IO_CONF_0 0xfffe1070
#define PERSEUS2_IO_CONF_1 0xfffe1074
#define PERSEUS2_IO_CONF_2 0xfffe1078
#define PERSEUS2_IO_CONF_3 0xfffe107c
#define PERSEUS2_IO_CONF_4 0xfffe1080
#define PERSEUS2_IO_CONF_5 0xfffe1084
#define PERSEUS2_IO_CONF_6 0xfffe1088
#define PERSEUS2_IO_CONF_7 0xfffe108c
#define PERSEUS2_IO_CONF_8 0xfffe1090
#define PERSEUS2_IO_CONF_9 0xfffe1094
#define PERSEUS2_IO_CONF_10 0xfffe1098
#define PERSEUS2_IO_CONF_11 0xfffe109c
#define PERSEUS2_IO_CONF_12 0xfffe10a0
#define PERSEUS2_IO_CONF_13 0xfffe10a4
#define PERSEUS2_MODE_1 0xfffe1010
#define PERSEUS2_MODE_2 0xfffe1014
/* CSMI specials: in terms of base + offset */
#define PERSEUS2_MODE2_OFFSET 0x14
/* DSP control: ICR registers */
#define ICR_BASE 0xfffbb800
/* M_CTL */
#define DSP_M_CTL ((volatile __u16 *)0xfffbb804)
/* DSP control: MMU registers */
#define DSP_MMU_BASE ((volatile __u16 *)0xfffed200)
/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */
#define INT_ETHER INT_730_MPU_EXT_NIRQ
#define MAXIRQNUM IH_BOARD_BASE
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS (MAXIRQNUM + 1)
#ifndef __ASSEMBLY__
void fpga_write(unsigned char val, int reg);
unsigned char fpga_read(int reg);
#endif
/* PCC_UPLD control register: OMAP730 */
#define PCC_UPLD_CTRL_REG_BASE (0xfffe0900)
#define PCC_UPLD_CTRL_REG (volatile __u16 *)(PCC_UPLD_CTRL_REG_BASE + 0x00)
#else
#error "Only OMAP730 Perseus2 supported!"
#endif
#endif
include/asm-arm/arch-omap/omap1610.h
View file @ 1b66a76f
......@@ -48,20 +48,60 @@
#define OMAP1610_DSPREG_SIZE SZ_128K
#define OMAP1610_DSPREG_START 0xE1000000
#define OMAP_IH2_0_BASE 0xfffe0000
#define OMAP_IH2_1_BASE 0xfffe0100
#define OMAP_IH2_2_BASE 0xfffe0200
#define OMAP_IH2_3_BASE 0xfffe0300
/*
* ---------------------------------------------------------------------------
* Interrupts
* ---------------------------------------------------------------------------
*/
#define OMAP_IH2_0_BASE (0xfffe0000)
#define OMAP_IH2_1_BASE (0xfffe0100)
#define OMAP_IH2_2_BASE (0xfffe0200)
#define OMAP_IH2_3_BASE (0xfffe0300)
#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
/*
* ----------------------------------------------------------------------------
* System control registers
* Clocks
* ----------------------------------------------------------------------------
*/
#define OMAP1610_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
#define OMAP1610_RESET_CONTROL 0xfffe1140
#define OMAP1610_ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24)
#define OMAP1610_CONF_VOLTAGE_CTRL_0 0xfffe1060
/*
* ----------------------------------------------------------------------------
* Pin configuration registers
* ----------------------------------------------------------------------------
*/
#define OMAP1610_CONF_VOLTAGE_VDDSHV6 (1 << 8)
#define OMAP1610_CONF_VOLTAGE_VDDSHV7 (1 << 9)
#define OMAP1610_CONF_VOLTAGE_VDDSHV8 (1 << 10)
......@@ -73,14 +113,8 @@
* TIPB bus interface
* ---------------------------------------------------------------------------
*/
#define OMAP1610_TIPB_SWITCH 0xfffbc800
#define OMAP1610_TIPB_BRIDGE_INT 0xfffeca00 /* Private TIPB_CNTL */
#define OMAP1610_PRIVATE_MPU_TIPB_CNTL 0xfffeca08
#define OMAP1610_TIPB_BRIDGE_EXT 0xfffed300 /* Public (Shared) TIPB_CNTL */
#define OMAP1610_PUBLIC_MPU_TIPB_CNTL 0xfffed308
#define OMAP1610_TIPB_SWITCH_CFG OMAP_TIPB_SWITCH
#define OMAP1610_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_CFG + 0x160)
#define TIPB_SWITCH_BASE (0xfffbc800)
#define OMAP1610_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
#endif /* __ASM_ARCH_OMAP1610_H */
include/asm-arm/arch-omap/omap5912.h
View file @ 1b66a76f
......@@ -49,13 +49,55 @@
#define OMAP5912_DSPREG_SIZE SZ_128K
#define OMAP5912_DSPREG_START 0xE1000000
/*
* ---------------------------------------------------------------------------
* Interrupts
* ---------------------------------------------------------------------------
*/
#define OMAP_IH2_0_BASE (0xfffe0000)
#define OMAP_IH2_1_BASE (0xfffe0100)
#define OMAP_IH2_2_BASE (0xfffe0200)
#define OMAP_IH2_3_BASE (0xfffe0300)
#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
/*
* ----------------------------------------------------------------------------
* System control registers
* ----------------------------------------------------------------------------
*/
#define OMAP5912_ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24)
#define OMAP5912_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
#endif /* __ASM_ARCH_OMAP5912_H */
include/asm-arm/arch-omap/omap730.h
View file @ 1b66a76f
......@@ -105,8 +105,8 @@
* OMAP730 PCC_UPLD configuration registers
* ----------------------------------------------------------------------------
*/
#define OMAP730_PCC_UPLD_CTRL_REG_BASE (0xfffe0900)
#define OMAP730_PCC_UPLD_CTRL_REG (OMAP730_PCC_UPLD_CTRL_REG_BASE + 0x00)
#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
#endif /* __ASM_ARCH_OMAP730_H */
include/asm-arm/arch-omap/time.h
View file @ 1b66a76f
......@@ -52,7 +52,7 @@ typedef struct {
#define mputimer_base(n) \
((volatile mputimer_regs_t*)IO_ADDRESS(OMAP_MPUTIMER_BASE + \
(n)*OMAP_MPUTIMER_OFF))
(n)*OMAP_MPUTIMER_OFFSET))
static inline unsigned long timer32k_read(int reg) {
unsigned long val;
......
include/asm-arm/arch-omap/uncompress.h
View file @ 1b66a76f
......@@ -25,7 +25,7 @@
#define UART_OMAP_MDR1 0x08 /* mode definition register */
#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & 0xffff
#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
static void
puts(const char *s)
......
include/asm-arm/uaccess.h
View file @ 1b66a76f
......@@ -13,7 +13,7 @@
*/
#include <linux/sched.h>
#include <asm/errno.h>
#include <asm/arch/memory.h>
#include <asm/memory.h>
#include <asm/domain.h>
#include <asm/system.h>
......
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