Commit 1bde95fa authored by Rajkumar Manoharan's avatar Rajkumar Manoharan Committed by John W. Linville

ath9k_hw: fix incorrect LNA register settings

After a full reset, mci_reset will put LNA update to the setting
for 2G mode. Those registers need to be forced to update when
the channel is in 5G.
Signed-off-by: default avatarRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3863495b
...@@ -1013,37 +1013,31 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, ...@@ -1013,37 +1013,31 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
} }
} }
void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
{ {
struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
if (!mci->update_2g5g) if (!mci->update_2g5g && !force)
return; return;
if (mci->is_2g) { if (mci->is_2g) {
ar9003_mci_send_2g5g_status(ah, true); ar9003_mci_send_2g5g_status(ah, true);
ar9003_mci_send_lna_transfer(ah, true);
udelay(5);
REG_CLR_BIT(ah, AR_MCI_TX_CTRL, REG_SET_BIT(ah, AR_MCI_TX_CTRL,
AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
REG_SET_BIT(ah, AR_BTCOEX_CTRL, ar9003_mci_osla_setup(ah, true);
AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
} else { } else {
ar9003_mci_send_lna_take(ah, true);
udelay(5);
REG_SET_BIT(ah, AR_MCI_TX_CTRL, REG_SET_BIT(ah, AR_MCI_TX_CTRL,
AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
ar9003_mci_osla_setup(ah, false);
if (!force)
ar9003_mci_send_2g5g_status(ah, true); ar9003_mci_send_2g5g_status(ah, true);
} }
} }
...@@ -1313,7 +1307,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) ...@@ -1313,7 +1307,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
if (mci->unhalt_bt_gpm) if (mci->unhalt_bt_gpm)
ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
ar9003_mci_2g5g_switch(ah, true); ar9003_mci_2g5g_switch(ah, false);
break; break;
case MCI_STATE_SET_BT_CAL_START: case MCI_STATE_SET_BT_CAL_START:
mci->bt_state = MCI_BT_CAL_START; mci->bt_state = MCI_BT_CAL_START;
...@@ -1394,7 +1388,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) ...@@ -1394,7 +1388,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
mci->query_bt = true; mci->query_bt = true;
mci->need_flush_btinfo = true; mci->need_flush_btinfo = true;
ar9003_mci_send_coex_wlan_channels(ah, true); ar9003_mci_send_coex_wlan_channels(ah, true);
ar9003_mci_2g5g_switch(ah, true); ar9003_mci_2g5g_switch(ah, false);
break; break;
case MCI_STATE_NEED_FTP_STOMP: case MCI_STATE_NEED_FTP_STOMP:
value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP); value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
......
...@@ -276,7 +276,7 @@ void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep); ...@@ -276,7 +276,7 @@ void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable); void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
void ar9003_mci_init_cal_done(struct ath_hw *ah); void ar9003_mci_init_cal_done(struct ath_hw *ah);
void ar9003_mci_set_full_sleep(struct ath_hw *ah); void ar9003_mci_set_full_sleep(struct ath_hw *ah);
void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done); void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force);
void ar9003_mci_check_bt(struct ath_hw *ah); void ar9003_mci_check_bt(struct ath_hw *ah);
bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan); bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
......
...@@ -1711,7 +1711,7 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -1711,7 +1711,7 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
ath9k_hw_start_nfcal(ah, true); ath9k_hw_start_nfcal(ah, true);
if (ath9k_hw_mci_is_enabled(ah)) if (ath9k_hw_mci_is_enabled(ah))
ar9003_mci_2g5g_switch(ah, true); ar9003_mci_2g5g_switch(ah, false);
if (AR_SREV_9271(ah)) if (AR_SREV_9271(ah))
ar9002_hw_load_ani_reg(ah, chan); ar9002_hw_load_ani_reg(ah, chan);
......
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