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Commit 1e0c397d authored by Igor M. Liplianin's avatar Igor M. Liplianin Committed by Mauro Carvalho Chehab
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V4L/DVB (13340): stv0900: big rework to support cut 3.0. 

Patch 3 of 4.
Also patch changes logic to prevent code repetitions and big indents.
It makes checkpatch silent :)
Signed-off-by: default avatarIgor M. Liplianin <liplianin@netup.ru>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent ab7134f1
Hide whitespace changes
Inline Side-by-side
Showing with 633 additions and 820 deletions
drivers/media/dvb/frontends/stv0900_core.c
View file @ 1e0c397d
......@@ -105,7 +105,8 @@ static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
while (new_node->next_inode != NULL)
new_node = new_node->next_inode;
new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
GFP_KERNEL);
if (new_node->next_inode != NULL)
new_node = new_node->next_inode;
else
......@@ -128,13 +129,13 @@ s32 ge2comp(s32 a, s32 width)
return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
}
void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
u8 reg_data)
{
u8 data[3];
int ret;
struct i2c_msg i2cmsg = {
.addr = i_params->i2c_addr,
.addr = intp->i2c_addr,
.flags = 0,
.len = 3,
.buf = data,
......@@ -144,31 +145,31 @@ void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
data[1] = LSB(reg_addr);
data[2] = reg_data;
ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
if (ret != 1)
dprintk("%s: i2c error %d\n", __func__, ret);
}
u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg)
u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
{
int ret;
u8 b0[] = { MSB(reg), LSB(reg) };
u8 buf = 0;
struct i2c_msg msg[] = {
{
.addr = i_params->i2c_addr,
.addr = intp->i2c_addr,
.flags = 0,
.buf = b0,
.len = 2,
}, {
.addr = i_params->i2c_addr,
.addr = intp->i2c_addr,
.flags = I2C_M_RD,
.buf = &buf,
.len = 1,
},
};
ret = i2c_transfer(i_params->i2c_adap, msg, 2);
ret = i2c_transfer(intp->i2c_adap, msg, 2);
if (ret != 2)
dprintk("%s: i2c error %d, reg[0x%02x]\n",
__func__, ret, reg);
......@@ -190,94 +191,103 @@ void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
(*pos) = (i - 1);
}
void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
{
u8 reg, mask, pos;
reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
extract_mask_pos(label, &mask, &pos);
val = mask & (val << pos);
reg = (reg & (~mask)) | val;
stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
}
u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
{
u8 val = 0xff;
u8 mask, pos;
extract_mask_pos(label, &mask, &pos);
val = stv0900_read_reg(i_params, label >> 16);
val = stv0900_read_reg(intp, label >> 16);
val = (val & mask) >> pos;
return val;
}
enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
{
s32 i;
enum fe_stv0900_error error;
if (i_params != NULL) {
i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
if (i_params->errs == STV0900_NO_ERROR) {
/*Startup sequence*/
stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
msleep(3);
stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
switch (i_params->clkmode) {
case 0:
case 2:
stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
| i_params->clkmode);
break;
default:
/* preserve SELOSCI bit */
i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
break;
}
msleep(3);
for (i = 0; i < 182; i++)
stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
if (intp == NULL)
return STV0900_INVALID_HANDLE;
if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
for (i = 0; i < 32; i++)
stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
}
intp->chip_id = stv0900_read_reg(intp, R0900_MID);
stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
}
error = i_params->errs;
} else
error = STV0900_INVALID_HANDLE;
if (intp->errs != STV0900_NO_ERROR)
return intp->errs;
return error;
/*Startup sequence*/
stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
msleep(3);
stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
msleep(3);
stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
switch (intp->clkmode) {
case 0:
case 2:
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
| intp->clkmode);
break;
default:
/* preserve SELOSCI bit */
i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
break;
}
msleep(3);
for (i = 0; i < 181; i++)
stv0900_write_reg(intp, STV0900_InitVal[i][0],
STV0900_InitVal[i][1]);
if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
for (i = 0; i < 32; i++)
stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
STV0900_Cut20_AddOnVal[i][1]);
}
stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
return STV0900_NO_ERROR;
}
u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
{
u32 mclk = 90000000, div = 0, ad_div = 0;
div = stv0900_get_bits(i_params, F0900_M_DIV);
ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
div = stv0900_get_bits(intp, F0900_M_DIV);
ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
mclk = (div + 1) * ext_clk / ad_div;
......@@ -286,73 +296,60 @@ u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
return mclk;
}
enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
{
enum fe_stv0900_error error = STV0900_NO_ERROR;
u32 m_div, clk_sel;
dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
i_params->quartz);
intp->quartz);
if (i_params == NULL)
error = STV0900_INVALID_HANDLE;
else {
if (i_params->errs)
error = STV0900_I2C_ERROR;
else {
clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
stv0900_write_bits(i_params, F0900_M_DIV, m_div);
i_params->mclk = stv0900_get_mclk_freq(i_params,
i_params->quartz);
/*Set the DiseqC frequency to 22KHz */
/*
Formula:
DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
*/
m_div = i_params->mclk / 704000;
stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
if ((i_params->errs))
error = STV0900_I2C_ERROR;
}
}
if (intp == NULL)
return STV0900_INVALID_HANDLE;
return error;
if (intp->errs)
return STV0900_I2C_ERROR;
clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
m_div = ((clk_sel * mclk) / intp->quartz) - 1;
stv0900_write_bits(intp, F0900_M_DIV, m_div);
intp->mclk = stv0900_get_mclk_freq(intp,
intp->quartz);
/*Set the DiseqC frequency to 22KHz */
/*
Formula:
DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
*/
m_div = intp->mclk / 704000;
stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
if ((intp->errs))
return STV0900_I2C_ERROR;
return STV0900_NO_ERROR;
}
u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
enum fe_stv0900_demod_num demod)
{
u32 lsb, msb, hsb, err_val;
s32 err1field_hsb, err1field_msb, err1field_lsb;
s32 err2field_hsb, err2field_msb, err2field_lsb;
dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
switch (cntr) {
case 0:
default:
hsb = stv0900_get_bits(i_params, err1field_hsb);
msb = stv0900_get_bits(i_params, err1field_msb);
lsb = stv0900_get_bits(i_params, err1field_lsb);
hsb = stv0900_get_bits(intp, ERR_CNT12);
msb = stv0900_get_bits(intp, ERR_CNT11);
lsb = stv0900_get_bits(intp, ERR_CNT10);
break;
case 1:
hsb = stv0900_get_bits(i_params, err2field_hsb);
msb = stv0900_get_bits(i_params, err2field_msb);
lsb = stv0900_get_bits(i_params, err2field_lsb);
hsb = stv0900_get_bits(intp, ERR_CNT22);
msb = stv0900_get_bits(intp, ERR_CNT21);
lsb = stv0900_get_bits(intp, ERR_CNT20);
break;
}
......@@ -364,26 +361,22 @@ u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u32 fi2c;
dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
stv0900_write_bits(i_params, fi2c, enable);
stv0900_write_bits(intp, I2CT_ON, enable);
return 0;
}
static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
enum fe_stv0900_clock_type path1_ts,
enum fe_stv0900_clock_type path2_ts)
{
dprintk("%s\n", __func__);
if (i_params->chip_id >= 0x20) {
if (intp->chip_id >= 0x20) {
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
......@@ -391,20 +384,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(i_params, R0900_TSGENERAL,
stv0900_write_reg(intp, R0900_TSGENERAL,
0x00);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(i_params, R0900_TSGENERAL,
stv0900_write_reg(intp, R0900_TSGENERAL,
0x06);
stv0900_write_bits(i_params,
stv0900_write_bits(intp,
F0900_P1_TSFIFO_MANSPEED, 3);
stv0900_write_bits(i_params,
stv0900_write_bits(intp,
F0900_P2_TSFIFO_MANSPEED, 0);
stv0900_write_reg(i_params,
stv0900_write_reg(intp,
R0900_P1_TSSPEED, 0x14);
stv0900_write_reg(i_params,
stv0900_write_reg(intp,
R0900_P2_TSSPEED, 0x28);
break;
}
......@@ -416,12 +409,12 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(i_params,
stv0900_write_reg(intp,
R0900_TSGENERAL, 0x0C);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(i_params,
stv0900_write_reg(intp,
R0900_TSGENERAL, 0x0A);
dprintk("%s: 0x0a\n", __func__);
break;
......@@ -436,20 +429,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(i_params, R0900_TSGENERAL1X,
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x10);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(i_params, R0900_TSGENERAL1X,
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x16);
stv0900_write_bits(i_params,
stv0900_write_bits(intp,
F0900_P1_TSFIFO_MANSPEED, 3);
stv0900_write_bits(i_params,
stv0900_write_bits(intp,
F0900_P2_TSFIFO_MANSPEED, 0);
stv0900_write_reg(i_params, R0900_P1_TSSPEED,
stv0900_write_reg(intp, R0900_P1_TSSPEED,
0x14);
stv0900_write_reg(i_params, R0900_P2_TSSPEED,
stv0900_write_reg(intp, R0900_P2_TSSPEED,
0x28);
break;
}
......@@ -462,12 +455,12 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
stv0900_write_reg(i_params, R0900_TSGENERAL1X,
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x14);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
stv0900_write_reg(i_params, R0900_TSGENERAL1X,
stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x12);
dprintk("%s: 0x12\n", __func__);
break;
......@@ -479,20 +472,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
break;
case STV0900_DVBCI_CLOCK:
stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
break;
case STV0900_SERIAL_PUNCT_CLOCK:
stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
break;
case STV0900_SERIAL_CONT_CLOCK:
stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
break;
default:
break;
......@@ -500,29 +493,29 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
switch (path2_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
break;
case STV0900_DVBCI_CLOCK:
stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
break;
case STV0900_SERIAL_PUNCT_CLOCK:
stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
break;
case STV0900_SERIAL_CONT_CLOCK:
stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
break;
default:
break;
}
stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
}
void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
......@@ -574,7 +567,7 @@ void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
}
}
static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
const struct stv0900_table *lookup,
enum fe_stv0900_demod_num demod)
{
......@@ -586,43 +579,37 @@ static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
dprintk("%s\n", __func__);
if ((lookup != NULL) && lookup->size) {
switch (demod) {
case STV0900_DEMOD_1:
default:
agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
break;
case STV0900_DEMOD_2:
agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
break;
}
dprintk("%s: AGC Gain = 0x%x\n", __func__, agc_gain);
if ((lookup == NULL) || (lookup->size <= 0))
return 0;
imin = 0;
imax = lookup->size - 1;
if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
while ((imax - imin) > 1) {
i = (imax + imin) >> 1;
agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
stv0900_get_bits(intp, AGCIQ_VALUE0));
if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
imax = i;
else
imin = i;
}
imin = 0;
imax = lookup->size - 1;
if (INRANGE(lookup->table[imin].regval, agc_gain,
lookup->table[imax].regval)) {
while ((imax - imin) > 1) {
i = (imax + imin) >> 1;
rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
* (lookup->table[imax].realval - lookup->table[imin].realval)
/ (lookup->table[imax].regval - lookup->table[imin].regval))
+ lookup->table[imin].realval;
} else if (agc_gain > lookup->table[0].regval)
rf_lvl = 5;
else if (agc_gain < lookup->table[lookup->size-1].regval)
rf_lvl = -100;
if (INRANGE(lookup->table[imin].regval,
agc_gain,
lookup->table[i].regval))
imax = i;
else
imin = i;
}
}
rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
rf_lvl *= (lookup->table[imax].realval -
lookup->table[imin].realval);
rf_lvl /= (lookup->table[imax].regval -
lookup->table[imin].regval);
rf_lvl += lookup->table[imin].realval;
} else if (agc_gain > lookup->table[0].regval)
rf_lvl = 5;
else if (agc_gain < lookup->table[lookup->size-1].regval)
rf_lvl = -100;
dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
......@@ -648,45 +635,39 @@ static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
return 0;
}
static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
const struct stv0900_table *lookup)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 c_n = -100,
regval, imin, imax,
s32 c_n = -100,
regval,
imin,
imax,
i,
lock_flag_field,
noise_field1,
noise_field0;
dprintk("%s\n", __func__);
dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
F0900_P2_LOCK_DEFINITIF);
if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1,
F0900_P2_NOSPLHT_NORMED1);
dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
F0900_P2_NOSPLHT_NORMED0);
noise_field1 = NOSPLHT_NORMED1;
noise_field0 = NOSPLHT_NORMED0;
} else {
dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1,
F0900_P2_NOSDATAT_NORMED1);
dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
F0900_P2_NOSDATAT_NORMED0);
noise_field1 = NOSDATAT_NORMED1;
noise_field0 = NOSDATAT_NORMED0;
}
if (stv0900_get_bits(i_params, lock_flag_field)) {
if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
if ((lookup != NULL) && lookup->size) {
regval = 0;
msleep(5);
for (i = 0; i < 16; i++) {
regval += MAKEWORD(stv0900_get_bits(i_params,
regval += MAKEWORD(stv0900_get_bits(intp,
noise_field1),
stv0900_get_bits(i_params,
stv0900_get_bits(intp,
noise_field0));
msleep(1);
}
......@@ -718,18 +699,15 @@ static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
}
}
dprintk("%s: Quality = %d\n", __func__, c_n);
return c_n;
}
static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u8 err_val1, err_val0;
s32 err_field1, err_field0;
u32 header_err_val = 0;
*ucblocks = 0x0;
......@@ -737,24 +715,14 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
/* DVB-S2 delineator errors count */
/* retreiving number for errnous headers */
dmd_reg(err_field0, R0900_P1_BBFCRCKO0,
R0900_P2_BBFCRCKO0);
dmd_reg(err_field1, R0900_P1_BBFCRCKO1,
R0900_P2_BBFCRCKO1);
err_val1 = stv0900_read_reg(i_params, err_field1);
err_val0 = stv0900_read_reg(i_params, err_field0);
header_err_val = (err_val1<<8) | err_val0;
err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
header_err_val = (err_val1 << 8) | err_val0;
/* retreiving number for errnous packets */
dmd_reg(err_field0, R0900_P1_UPCRCKO0,
R0900_P2_UPCRCKO0);
dmd_reg(err_field1, R0900_P1_UPCRCKO1,
R0900_P2_UPCRCKO1);
err_val1 = stv0900_read_reg(i_params, err_field1);
err_val0 = stv0900_read_reg(i_params, err_field0);
*ucblocks = (err_val1<<8) | err_val0;
err_val1 = stv0900_read_reg(intp, UPCRCKO1);
err_val0 = stv0900_read_reg(intp, UPCRCKO0);
*ucblocks = (err_val1 << 8) | err_val0;
*ucblocks += header_err_val;
}
......@@ -777,25 +745,13 @@ static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
return 0;
}
static u32 stv0900_get_ber(struct stv0900_internal *i_params,
static u32 stv0900_get_ber(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 ber = 10000000, i;
s32 dmd_state_reg;
s32 demod_state;
s32 vstatus_reg;
s32 prvit_field;
s32 pdel_status_reg;
s32 pdel_lock_field;
dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
F0900_P2_PKTDELIN_LOCK);
demod_state = stv0900_get_bits(i_params, dmd_state_reg);
demod_state = stv0900_get_bits(intp, HEADER_MODE);
switch (demod_state) {
case STV0900_SEARCH:
......@@ -807,11 +763,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
ber = 0;
for (i = 0; i < 5; i++) {
msleep(5);
ber += stv0900_get_err_count(i_params, 0, demod);
ber += stv0900_get_err_count(intp, 0, demod);
}
ber /= 5;
if (stv0900_get_bits(i_params, prvit_field)) {
if (stv0900_get_bits(intp, PRFVIT)) {
ber *= 9766;
ber = ber >> 13;
}
......@@ -821,11 +777,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
ber = 0;
for (i = 0; i < 5; i++) {
msleep(5);
ber += stv0900_get_err_count(i_params, 0, demod);
ber += stv0900_get_err_count(intp, 0, demod);
}
ber /= 5;
if (stv0900_get_bits(i_params, pdel_lock_field)) {
if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
ber *= 9766;
ber = ber >> 13;
}
......@@ -846,20 +802,16 @@ static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
return 0;
}
int stv0900_get_demod_lock(struct stv0900_internal *i_params,
int stv0900_get_demod_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod, s32 time_out)
{
s32 timer = 0,
lock = 0,
header_field,
lock_field;
lock = 0;
enum fe_stv0900_search_state dmd_state;
dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
while ((timer < time_out) && (lock == 0)) {
dmd_state = stv0900_get_bits(i_params, header_field);
dmd_state = stv0900_get_bits(intp, HEADER_MODE);
dprintk("Demod State = %d\n", dmd_state);
switch (dmd_state) {
case STV0900_SEARCH:
......@@ -869,7 +821,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
break;
case STV0900_DVBS2_FOUND:
case STV0900_DVBS_FOUND:
lock = stv0900_get_bits(i_params, lock_field);
lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
break;
}
......@@ -887,7 +839,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
return lock;
}
void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 regflist,
......@@ -895,48 +847,32 @@ void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
dprintk("%s\n", __func__);
dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
regflist = MODCODLST0;
for (i = 0; i < 16; i++)
stv0900_write_reg(i_params, regflist + i, 0xff);
stv0900_write_reg(intp, regflist + i, 0xff);
}
void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 matype,
mod_code,
fmod,
reg_index,
field_index;
mod_code,
fmod,
reg_index,
field_index;
dprintk("%s\n", __func__);
if (i_params->chip_id <= 0x11) {
if (intp->chip_id <= 0x11) {
msleep(5);
switch (demod) {
case STV0900_DEMOD_1:
default:
mod_code = stv0900_read_reg(i_params,
R0900_P1_PLHMODCOD);
matype = mod_code & 0x3;
mod_code = (mod_code & 0x7f) >> 2;
reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
field_index = mod_code % 2;
break;
case STV0900_DEMOD_2:
mod_code = stv0900_read_reg(i_params,
R0900_P2_PLHMODCOD);
matype = mod_code & 0x3;
mod_code = (mod_code & 0x7f) >> 2;
reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
field_index = mod_code % 2;
break;
}
mod_code = stv0900_read_reg(intp, PLHMODCOD);
matype = mod_code & 0x3;
mod_code = (mod_code & 0x7f) >> 2;
reg_index = MODCODLSTF - mod_code / 2;
field_index = mod_code % 2;
switch (matype) {
case 0:
......@@ -955,70 +891,41 @@ void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
}
if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
&& (matype <= 1)) {
&& (matype <= 1)) {
if (field_index == 0)
stv0900_write_reg(i_params, reg_index,
stv0900_write_reg(intp, reg_index,
0xf0 | fmod);
else
stv0900_write_reg(i_params, reg_index,
stv0900_write_reg(intp, reg_index,
(fmod << 4) | 0xf);
}
} else if (i_params->chip_id >= 0x12) {
switch (demod) {
case STV0900_DEMOD_1:
default:
for (reg_index = 0; reg_index < 7; reg_index++)
stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
for (reg_index = 0; reg_index < 8; reg_index++)
stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
break;
case STV0900_DEMOD_2:
for (reg_index = 0; reg_index < 7; reg_index++)
stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
} else if (intp->chip_id >= 0x12) {
for (reg_index = 0; reg_index < 7; reg_index++)
stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
for (reg_index = 0; reg_index < 8; reg_index++)
stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
stv0900_write_reg(intp, MODCODLSTE, 0xff);
stv0900_write_reg(intp, MODCODLSTF, 0xcf);
for (reg_index = 0; reg_index < 8; reg_index++)
stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
break;
}
}
}
void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 reg_index;
dprintk("%s\n", __func__);
switch (demod) {
case STV0900_DEMOD_1:
default:
stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
for (reg_index = 0; reg_index < 13; reg_index++)
stv0900_write_reg(i_params,
R0900_P1_MODCODLST2 + reg_index, 0);
break;
case STV0900_DEMOD_2:
stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
for (reg_index = 0; reg_index < 13; reg_index++)
stv0900_write_reg(i_params,
R0900_P2_MODCODLST2 + reg_index, 0);
stv0900_write_reg(intp, MODCODLST0, 0xff);
stv0900_write_reg(intp, MODCODLST1, 0xf0);
stv0900_write_reg(intp, MODCODLSTF, 0x0f);
for (reg_index = 0; reg_index < 13; reg_index++)
stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
break;
}
}
static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
......@@ -1042,161 +949,118 @@ static int stb0900_get_property(struct dvb_frontend *fe,
return 0;
}
void stv0900_start_search(struct stv0900_internal *i_params,
void stv0900_start_search(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
switch (demod) {
case STV0900_DEMOD_1:
default:
stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
if (i_params->chip_id == 0x10)
stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
if (i_params->chip_id < 0x20)
stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
if (i_params->dmd1_symbol_rate <= 5000000) {
stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
u32 freq;
s16 freq_s16 ;
stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
if (intp->chip_id == 0x10)
stv0900_write_reg(intp, CORRELEXP, 0xaa);
if (intp->chip_id < 0x20)
stv0900_write_reg(intp, CARHDR, 0x55);
if (intp->chip_id <= 0x20) {
if (intp->symbol_rate[0] <= 5000000) {
stv0900_write_reg(intp, CARCFG, 0x44);
stv0900_write_reg(intp, CFRUP1, 0x0f);
stv0900_write_reg(intp, CFRUP0, 0xff);
stv0900_write_reg(intp, CFRLOW1, 0xf0);
stv0900_write_reg(intp, CFRLOW0, 0x00);
stv0900_write_reg(intp, RTCS2, 0x68);
} else {
stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
stv0900_write_reg(intp, CARCFG, 0xc4);
stv0900_write_reg(intp, RTCS2, 0x44);
}
stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
if (i_params->chip_id >= 0x20) {
stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
}
}
stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
if (i_params->chip_id >= 0x20) {
if (i_params->dmd1_symbol_rate < 2000000) {
stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
}
if (i_params->dmd1_symbol_rate < 10000000) {
stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
} else {
stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
}
} else { /*cut 3.0 above*/
if (intp->symbol_rate[demod] <= 5000000)
stv0900_write_reg(intp, RTCS2, 0x68);
else
stv0900_write_reg(intp, RTCS2, 0x44);
stv0900_write_reg(intp, CARCFG, 0x46);
if (intp->srch_algo[demod] == STV0900_WARM_START) {
freq = 1000 << 16;
freq /= (intp->mclk / 1000);
freq_s16 = (s16)freq;
} else {
if (i_params->dmd1_symbol_rate < 10000000)
stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
freq = (intp->srch_range[demod] / 2000);
if (intp->symbol_rate[demod] <= 5000000)
freq += 80;
else
stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
}
switch (i_params->dmd1_srch_algo) {
case STV0900_WARM_START:
stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
break;
case STV0900_COLD_START:
stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
break;
default:
break;
}
freq += 600;
break;
case STV0900_DEMOD_2:
stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
if (i_params->chip_id == 0x10)
stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
if (i_params->chip_id < 0x20)
stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
if (i_params->dmd2_symbol_rate <= 5000000) {
stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
} else {
stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
freq = freq << 16;
freq /= (intp->mclk / 1000);
freq_s16 = (s16)freq;
}
stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
freq_s16 *= (-1);
stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
}
if (i_params->chip_id >= 0x20) {
stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
}
}
stv0900_write_reg(intp, CFRINIT1, 0);
stv0900_write_reg(intp, CFRINIT0, 0);
stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
if (i_params->chip_id >= 0x20) {
if (i_params->dmd2_symbol_rate < 2000000) {
stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
}
if (intp->chip_id >= 0x20) {
stv0900_write_reg(intp, EQUALCFG, 0x41);
stv0900_write_reg(intp, FFECFG, 0x41);
if (i_params->dmd2_symbol_rate < 10000000) {
stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
} else {
stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
}
if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
(intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
(intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
stv0900_write_reg(intp, VITSCALE,
0x82);
stv0900_write_reg(intp, VAVSRVIT, 0x0);
}
}
stv0900_write_reg(intp, SFRSTEP, 0x00);
stv0900_write_reg(intp, TMGTHRISE, 0xe0);
stv0900_write_reg(intp, TMGTHFALL, 0xc0);
stv0900_write_bits(intp, SCAN_ENABLE, 0);
stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
stv0900_write_reg(intp, RTC, 0x88);
if (intp->chip_id >= 0x20) {
if (intp->symbol_rate[demod] < 2000000) {
if (intp->chip_id <= 0x20)
stv0900_write_reg(intp, CARFREQ, 0x39);
else /*cut 3.0*/
stv0900_write_reg(intp, CARFREQ, 0x89);
stv0900_write_reg(intp, CARHDR, 0x40);
} else if (intp->symbol_rate[demod] < 10000000) {
stv0900_write_reg(intp, CARFREQ, 0x4c);
stv0900_write_reg(intp, CARHDR, 0x20);
} else {
if (i_params->dmd2_symbol_rate < 10000000)
stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
else
stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
stv0900_write_reg(intp, CARFREQ, 0x4b);
stv0900_write_reg(intp, CARHDR, 0x20);
}
switch (i_params->dmd2_srch_algo) {
case STV0900_WARM_START:
stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
break;
case STV0900_COLD_START:
stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
break;
default:
break;
}
} else {
if (intp->symbol_rate[demod] < 10000000)
stv0900_write_reg(intp, CARFREQ, 0xef);
else
stv0900_write_reg(intp, CARFREQ, 0xed);
}
switch (intp->srch_algo[demod]) {
case STV0900_WARM_START:
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x18);
break;
case STV0900_COLD_START:
stv0900_write_reg(intp, DMDISTATE, 0x1f);
stv0900_write_reg(intp, DMDISTATE, 0x15);
break;
default:
break;
}
}
......@@ -1205,33 +1069,40 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
s32 pilot, u8 chip_id)
{
u8 aclc_value = 0x29;
s32 i;
const struct stv0900_car_loop_optim *car_loop_s2;
s32 i;
const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
dprintk("%s\n", __func__);
if (chip_id <= 0x12)
car_loop_s2 = FE_STV0900_S2CarLoop;
else if (chip_id == 0x20)
car_loop_s2 = FE_STV0900_S2CarLoopCut20;
else
car_loop_s2 = FE_STV0900_S2CarLoop;
if (chip_id <= 0x12) {
cls2 = FE_STV0900_S2CarLoop;
cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
cllas2 = FE_STV0900_S2APSKCarLoopCut30;
} else if (chip_id == 0x20) {
cls2 = FE_STV0900_S2CarLoopCut20;
cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
cllas2 = FE_STV0900_S2APSKCarLoopCut20;
} else {
cls2 = FE_STV0900_S2CarLoopCut30;
cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
cllas2 = FE_STV0900_S2APSKCarLoopCut30;
}
if (modcode < STV0900_QPSK_12) {
i = 0;
while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
while ((i < 3) && (modcode != cllqs2[i].modcode))
i++;
if (i >= 3)
i = 2;
} else {
i = 0;
while ((i < 14) && (modcode != car_loop_s2[i].modcode))
while ((i < 14) && (modcode != cls2[i].modcode))
i++;
if (i >= 14) {
i = 0;
while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
while ((i < 11) && (modcode != cllas2[i].modcode))
i++;
if (i >= 11)
......@@ -1242,77 +1113,83 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
if (modcode <= STV0900_QPSK_25) {
if (pilot) {
if (srate <= 3000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
aclc_value = cllqs2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
aclc_value = cllqs2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
aclc_value = cllqs2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
aclc_value = cllqs2[i].car_loop_pilots_on_20;
else
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
aclc_value = cllqs2[i].car_loop_pilots_on_30;
} else {
if (srate <= 3000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
aclc_value = cllqs2[i].car_loop_pilots_off_2;
else if (srate <= 7000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
aclc_value = cllqs2[i].car_loop_pilots_off_5;
else if (srate <= 15000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
aclc_value = cllqs2[i].car_loop_pilots_off_10;
else if (srate <= 25000000)
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
aclc_value = cllqs2[i].car_loop_pilots_off_20;
else
aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
aclc_value = cllqs2[i].car_loop_pilots_off_30;
}
} else if (modcode <= STV0900_8PSK_910) {
if (pilot) {
if (srate <= 3000000)
aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
aclc_value = cls2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
aclc_value = cls2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
aclc_value = cls2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
aclc_value = cls2[i].car_loop_pilots_on_20;
else
aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
aclc_value = cls2[i].car_loop_pilots_on_30;
} else {
if (srate <= 3000000)
aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
aclc_value = cls2[i].car_loop_pilots_off_2;
else if (srate <= 7000000)
aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
aclc_value = cls2[i].car_loop_pilots_off_5;
else if (srate <= 15000000)
aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
aclc_value = cls2[i].car_loop_pilots_off_10;
else if (srate <= 25000000)
aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
aclc_value = cls2[i].car_loop_pilots_off_20;
else
aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
aclc_value = cls2[i].car_loop_pilots_off_30;
}
} else {
if (srate <= 3000000)
aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
aclc_value = cllas2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
aclc_value = cllas2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
aclc_value = cllas2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
aclc_value = cllas2[i].car_loop_pilots_on_20;
else
aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
aclc_value = cllas2[i].car_loop_pilots_on_30;
}
return aclc_value;
}
u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
u8 stv0900_get_optim_short_carr_loop(s32 srate,
enum fe_stv0900_modulation modulation,
u8 chip_id)
{
const struct stv0900_short_frames_car_loop_optim *s2scl;
const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
s32 mod_index = 0;
u8 aclc_value = 0x0b;
dprintk("%s\n", __func__);
s2scl = FE_STV0900_S2ShortCarLoop;
s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
switch (modulation) {
case STV0900_QPSK:
default:
......@@ -1329,75 +1206,116 @@ u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modul
break;
}
switch (chip_id) {
case 0x20:
if (chip_id >= 0x30) {
if (srate <= 3000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
aclc_value = s2sclc30[mod_index].car_loop_2;
else if (srate <= 7000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
aclc_value = s2sclc30[mod_index].car_loop_5;
else if (srate <= 15000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
aclc_value = s2sclc30[mod_index].car_loop_10;
else if (srate <= 25000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
aclc_value = s2sclc30[mod_index].car_loop_20;
else
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
aclc_value = s2sclc30[mod_index].car_loop_30;
break;
case 0x12:
default:
} else if (chip_id >= 0x20) {
if (srate <= 3000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
aclc_value = s2scl[mod_index].car_loop_cut20_2;
else if (srate <= 7000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
aclc_value = s2scl[mod_index].car_loop_cut20_5;
else if (srate <= 15000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
aclc_value = s2scl[mod_index].car_loop_cut20_10;
else if (srate <= 25000000)
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
aclc_value = s2scl[mod_index].car_loop_cut20_20;
else
aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
aclc_value = s2scl[mod_index].car_loop_cut20_30;
} else {
if (srate <= 3000000)
aclc_value = s2scl[mod_index].car_loop_cut12_2;
else if (srate <= 7000000)
aclc_value = s2scl[mod_index].car_loop_cut12_5;
else if (srate <= 15000000)
aclc_value = s2scl[mod_index].car_loop_cut12_10;
else if (srate <= 25000000)
aclc_value = s2scl[mod_index].car_loop_cut12_20;
else
aclc_value = s2scl[mod_index].car_loop_cut12_30;
break;
}
return aclc_value;
}
static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
static
enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
enum fe_stv0900_demod_mode LDPC_Mode,
enum fe_stv0900_demod_num demod)
{
enum fe_stv0900_error error = STV0900_NO_ERROR;
s32 reg_ind;
dprintk("%s\n", __func__);
switch (LDPC_Mode) {
case STV0900_DUAL:
default:
if ((i_params->demod_mode != STV0900_DUAL)
|| (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
i_params->demod_mode = STV0900_DUAL;
stv0900_write_bits(i_params, F0900_FRESFEC, 1);
stv0900_write_bits(i_params, F0900_FRESFEC, 0);
if ((intp->demod_mode != STV0900_DUAL)
|| (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
intp->demod_mode = STV0900_DUAL;
stv0900_write_bits(intp, F0900_FRESFEC, 1);
stv0900_write_bits(intp, F0900_FRESFEC, 0);
for (reg_ind = 0; reg_ind < 7; reg_ind++)
stv0900_write_reg(intp,
R0900_P1_MODCODLST0 + reg_ind,
0xff);
for (reg_ind = 0; reg_ind < 8; reg_ind++)
stv0900_write_reg(intp,
R0900_P1_MODCODLST7 + reg_ind,
0xcc);
stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
for (reg_ind = 0; reg_ind < 7; reg_ind++)
stv0900_write_reg(intp,
R0900_P2_MODCODLST0 + reg_ind,
0xff);
for (reg_ind = 0; reg_ind < 8; reg_ind++)
stv0900_write_reg(intp,
R0900_P2_MODCODLST7 + reg_ind,
0xcc);
stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
}
break;
case STV0900_SINGLE:
if (demod == STV0900_DEMOD_2)
stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
else
stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
if (demod == STV0900_DEMOD_2) {
stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
stv0900_activate_s2_modcod_single(intp,
STV0900_DEMOD_2);
stv0900_write_reg(intp, R0900_GENCFG, 0x06);
} else {
stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
stv0900_activate_s2_modcod_single(intp,
STV0900_DEMOD_1);
stv0900_write_reg(intp, R0900_GENCFG, 0x04);
}
i_params->demod_mode = STV0900_SINGLE;
intp->demod_mode = STV0900_SINGLE;
stv0900_write_bits(i_params, F0900_FRESFEC, 1);
stv0900_write_bits(i_params, F0900_FRESFEC, 0);
stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
stv0900_write_bits(intp, F0900_FRESFEC, 1);
stv0900_write_bits(intp, F0900_FRESFEC, 0);
stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
break;
}
......@@ -1410,6 +1328,8 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
struct stv0900_state *state = fe->demodulator_priv;
enum fe_stv0900_error error = STV0900_NO_ERROR;
enum fe_stv0900_error demodError = STV0900_NO_ERROR;
struct stv0900_internal *intp = NULL;
int selosci, i;
struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
......@@ -1423,7 +1343,8 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
dprintk("%s: Find Internal Structure!\n", __func__);
return STV0900_NO_ERROR;
} else {
state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
state->internal = kmalloc(sizeof(struct stv0900_internal),
GFP_KERNEL);
temp_int = append_internal(state->internal);
state->internal->dmds_used = 1;
state->internal->i2c_adap = state->i2c_adap;
......@@ -1433,108 +1354,105 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
dprintk("%s: Create New Internal Structure!\n", __func__);
}
if (state->internal != NULL) {
demodError = stv0900_initialize(state->internal);
if (demodError == STV0900_NO_ERROR) {
error = STV0900_NO_ERROR;
} else {
if (demodError == STV0900_INVALID_HANDLE)
error = STV0900_INVALID_HANDLE;
else
error = STV0900_I2C_ERROR;
}
if (state->internal == NULL) {
error = STV0900_INVALID_HANDLE;
return error;
}
if (state->internal != NULL) {
if (error == STV0900_NO_ERROR) {
state->internal->demod_mode = p_init->demod_mode;
stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
state->internal->rolloff = p_init->rolloff;
state->internal->quartz = p_init->dmd_ref_clk;
stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
state->internal->ts_config = p_init->ts_config;
if (state->internal->ts_config == NULL)
stv0900_set_ts_parallel_serial(state->internal,
p_init->path1_ts_clock,
p_init->path2_ts_clock);
else {
for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
stv0900_write_reg(state->internal,
state->internal->ts_config[i].addr,
state->internal->ts_config[i].val);
stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
}
demodError = stv0900_initialize(state->internal);
if (demodError == STV0900_NO_ERROR) {
error = STV0900_NO_ERROR;
} else {
if (demodError == STV0900_INVALID_HANDLE)
error = STV0900_INVALID_HANDLE;
else
error = STV0900_I2C_ERROR;
stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
switch (p_init->tuner1_adc) {
case 1:
stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
break;
default:
break;
}
return error;
}
stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
switch (p_init->tuner2_adc) {
case 1:
stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
break;
default:
break;
}
if (state->internal == NULL) {
error = STV0900_INVALID_HANDLE;
return error;
}
stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
stv0900_set_mclk(state->internal, 135000000);
msleep(3);
switch (state->internal->clkmode) {
case 0:
case 2:
stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
break;
default:
selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
break;
}
msleep(3);
intp = state->internal;
state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
if (state->internal->errs)
error = STV0900_I2C_ERROR;
}
} else {
error = STV0900_INVALID_HANDLE;
}
intp->demod_mode = p_init->demod_mode;
stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
intp->chip_id = stv0900_read_reg(intp, R0900_MID);
intp->rolloff = p_init->rolloff;
intp->quartz = p_init->dmd_ref_clk;
stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
intp->ts_config = p_init->ts_config;
if (intp->ts_config == NULL)
stv0900_set_ts_parallel_serial(intp,
p_init->path1_ts_clock,
p_init->path2_ts_clock);
else {
for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
stv0900_write_reg(intp,
intp->ts_config[i].addr,
intp->ts_config[i].val);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
}
stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
switch (p_init->tuner1_adc) {
case 1:
stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
break;
default:
break;
}
stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
switch (p_init->tuner2_adc) {
case 1:
stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
break;
default:
break;
}
stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
stv0900_set_mclk(intp, 135000000);
msleep(3);
switch (intp->clkmode) {
case 0:
case 2:
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
break;
default:
selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
break;
}
msleep(3);
intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
if (intp->errs)
error = STV0900_I2C_ERROR;
return error;
}
static int stv0900_status(struct stv0900_internal *i_params,
static int stv0900_status(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
enum fe_stv0900_search_state demod_state;
s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
int locked = FALSE;
dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
demod_state = stv0900_get_bits(i_params, mode_field);
demod_state = stv0900_get_bits(intp, HEADER_MODE);
switch (demod_state) {
case STV0900_SEARCH:
case STV0900_PLH_DETECTED:
......@@ -1542,17 +1460,19 @@ static int stv0900_status(struct stv0900_internal *i_params,
locked = FALSE;
break;
case STV0900_DVBS2_FOUND:
locked = stv0900_get_bits(i_params, lock_field) &&
stv0900_get_bits(i_params, delin_field) &&
stv0900_get_bits(i_params, fifo_field);
locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
stv0900_get_bits(intp, PKTDELIN_LOCK) &&
stv0900_get_bits(intp, TSFIFO_LINEOK);
break;
case STV0900_DVBS_FOUND:
locked = stv0900_get_bits(i_params, lock_field) &&
stv0900_get_bits(i_params, lockedvit_field) &&
stv0900_get_bits(i_params, fifo_field);
locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
stv0900_get_bits(intp, LOCKEDVIT) &&
stv0900_get_bits(intp, TSFIFO_LINEOK);
break;
}
dprintk("%s: locked = %d\n", __func__, locked);
return locked;
}
......@@ -1560,7 +1480,8 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
struct dvb_frontend_parameters *params)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct stv0900_search_params p_search;
......@@ -1570,8 +1491,11 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
dprintk("%s: ", __func__);
if (!(INRANGE(100000, c->symbol_rate, 70000000)))
return DVBFE_ALGO_SEARCH_FAILED;
p_result.locked = FALSE;
p_search.path = state->demod;
p_search.path = demod;
p_search.frequency = c->frequency;
p_search.symbol_rate = c->symbol_rate;
p_search.search_range = 10000000;
......@@ -1580,93 +1504,38 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
p_search.iq_inversion = STV0900_IQ_AUTO;
p_search.search_algo = STV0900_BLIND_SEARCH;
if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
(INRANGE(100000, p_search.search_range, 50000000))) {
switch (p_search.path) {
case STV0900_DEMOD_1:
default:
i_params->dmd1_srch_standard = p_search.standard;
i_params->dmd1_symbol_rate = p_search.symbol_rate;
i_params->dmd1_srch_range = p_search.search_range;
i_params->tuner1_freq = p_search.frequency;
i_params->dmd1_srch_algo = p_search.search_algo;
i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
i_params->dmd1_fec = p_search.fec;
intp->srch_standard[demod] = p_search.standard;
intp->symbol_rate[demod] = p_search.symbol_rate;
intp->srch_range[demod] = p_search.search_range;
intp->freq[demod] = p_search.frequency;
intp->srch_algo[demod] = p_search.search_algo;
intp->srch_iq_inv[demod] = p_search.iq_inversion;
intp->fec[demod] = p_search.fec;
if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
(intp->errs == STV0900_NO_ERROR)) {
p_result.locked = intp->result[demod].locked;
p_result.standard = intp->result[demod].standard;
p_result.frequency = intp->result[demod].frequency;
p_result.symbol_rate = intp->result[demod].symbol_rate;
p_result.fec = intp->result[demod].fec;
p_result.modcode = intp->result[demod].modcode;
p_result.pilot = intp->result[demod].pilot;
p_result.frame_len = intp->result[demod].frame_len;
p_result.spectrum = intp->result[demod].spectrum;
p_result.rolloff = intp->result[demod].rolloff;
p_result.modulation = intp->result[demod].modulation;
} else {
p_result.locked = FALSE;
switch (intp->err[demod]) {
case STV0900_I2C_ERROR:
error = STV0900_I2C_ERROR;
break;
case STV0900_DEMOD_2:
i_params->dmd2_srch_stndrd = p_search.standard;
i_params->dmd2_symbol_rate = p_search.symbol_rate;
i_params->dmd2_srch_range = p_search.search_range;
i_params->tuner2_freq = p_search.frequency;
i_params->dmd2_srch_algo = p_search.search_algo;
i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
i_params->dmd2_fec = p_search.fec;
case STV0900_NO_ERROR:
default:
error = STV0900_SEARCH_FAILED;
break;
}
if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
(i_params->errs == STV0900_NO_ERROR)) {
switch (p_search.path) {
case STV0900_DEMOD_1:
default:
p_result.locked = i_params->dmd1_rslts.locked;
p_result.standard = i_params->dmd1_rslts.standard;
p_result.frequency = i_params->dmd1_rslts.frequency;
p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
p_result.fec = i_params->dmd1_rslts.fec;
p_result.modcode = i_params->dmd1_rslts.modcode;
p_result.pilot = i_params->dmd1_rslts.pilot;
p_result.frame_length = i_params->dmd1_rslts.frame_length;
p_result.spectrum = i_params->dmd1_rslts.spectrum;
p_result.rolloff = i_params->dmd1_rslts.rolloff;
p_result.modulation = i_params->dmd1_rslts.modulation;
break;
case STV0900_DEMOD_2:
p_result.locked = i_params->dmd2_rslts.locked;
p_result.standard = i_params->dmd2_rslts.standard;
p_result.frequency = i_params->dmd2_rslts.frequency;
p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
p_result.fec = i_params->dmd2_rslts.fec;
p_result.modcode = i_params->dmd2_rslts.modcode;
p_result.pilot = i_params->dmd2_rslts.pilot;
p_result.frame_length = i_params->dmd2_rslts.frame_length;
p_result.spectrum = i_params->dmd2_rslts.spectrum;
p_result.rolloff = i_params->dmd2_rslts.rolloff;
p_result.modulation = i_params->dmd2_rslts.modulation;
break;
}
} else {
p_result.locked = FALSE;
switch (p_search.path) {
case STV0900_DEMOD_1:
switch (i_params->dmd1_err) {
case STV0900_I2C_ERROR:
error = STV0900_I2C_ERROR;
break;
case STV0900_NO_ERROR:
default:
error = STV0900_SEARCH_FAILED;
break;
}
break;
case STV0900_DEMOD_2:
switch (i_params->dmd2_err) {
case STV0900_I2C_ERROR:
error = STV0900_I2C_ERROR;
break;
case STV0900_NO_ERROR:
default:
error = STV0900_SEARCH_FAILED;
break;
}
break;
}
}
} else
error = STV0900_BAD_PARAMETER;
}
if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
dprintk("Search Success\n");
......@@ -1676,7 +1545,6 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
return DVBFE_ALGO_SEARCH_FAILED;
}
return DVBFE_ALGO_SEARCH_ERROR;
}
static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
......@@ -1707,16 +1575,13 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 rst_field;
dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
if (stop_ts == TRUE)
stv0900_write_bits(i_params, rst_field, 1);
stv0900_write_bits(intp, RST_HWARE, 1);
else
stv0900_write_bits(i_params, rst_field, 0);
stv0900_write_bits(intp, RST_HWARE, 0);
return 0;
}
......@@ -1724,16 +1589,12 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
static int stv0900_diseqc_init(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 mode_field, reset_field;
dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
stv0900_write_bits(i_params, reset_field, 1);
stv0900_write_bits(i_params, reset_field, 0);
stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
stv0900_write_bits(intp, DISEQC_RESET, 1);
stv0900_write_bits(intp, DISEQC_RESET, 0);
return 0;
}
......@@ -1748,47 +1609,24 @@ static int stv0900_init(struct dvb_frontend *fe)
return 0;
}
static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
u32 NbData, enum fe_stv0900_demod_num demod)
{
s32 i = 0;
switch (demod) {
case STV0900_DEMOD_1:
default:
stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
while (i < NbData) {
while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
;/* checkpatch complains */
stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
i++;
}
stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
i = 0;
while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
msleep(10);
i++;
}
break;
case STV0900_DEMOD_2:
stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
while (i < NbData) {
while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
;/* checkpatch complains */
stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
i++;
}
stv0900_write_bits(intp, DIS_PRECHARGE, 1);
while (i < NbData) {
while (stv0900_get_bits(intp, FIFO_FULL))
;/* checkpatch complains */
stv0900_write_reg(intp, DISTXDATA, data[i]);
i++;
}
stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
i = 0;
while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
msleep(10);
i++;
}
break;
stv0900_write_bits(intp, DIS_PRECHARGE, 0);
i = 0;
while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
msleep(10);
i++;
}
return 0;
......@@ -1808,23 +1646,21 @@ static int stv0900_send_master_cmd(struct dvb_frontend *fe,
static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 mode_field;
u8 data;
dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
switch (burst) {
case SEC_MINI_A:
stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
data = 0x00;
stv0900_diseqc_send(state->internal, &data, 1, state->demod);
stv0900_diseqc_send(intp, &data, 1, state->demod);
break;
case SEC_MINI_B:
stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
data = 0xff;
stv0900_diseqc_send(state->internal, &data, 1, state->demod);
stv0900_diseqc_send(intp, &data, 1, state->demod);
break;
}
......@@ -1835,41 +1671,22 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
struct dvb_diseqc_slave_reply *reply)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 i = 0;
switch (state->demod) {
case STV0900_DEMOD_1:
default:
reply->msg_len = 0;
while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
msleep(10);
i++;
}
if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
reply->msg_len = 0;
for (i = 0; i < reply->msg_len; i++)
reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
}
break;
case STV0900_DEMOD_2:
reply->msg_len = 0;
while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
msleep(10);
i++;
}
while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
msleep(10);
i++;
}
if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
if (stv0900_get_bits(intp, RX_END)) {
reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
for (i = 0; i < reply->msg_len; i++)
reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
}
break;
for (i = 0; i < reply->msg_len; i++)
reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
}
return 0;
......@@ -1878,31 +1695,27 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
{
struct stv0900_state *state = fe->demodulator_priv;
struct stv0900_internal *i_params = state->internal;
struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
s32 mode_field, reset_field;
dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
switch (toneoff) {
case SEC_TONE_ON:
/*Set the DiseqC mode to 22Khz _continues_ tone*/
stv0900_write_bits(i_params, mode_field, 0);
stv0900_write_bits(i_params, reset_field, 1);
stv0900_write_bits(intp, DISTX_MODE, 0);
stv0900_write_bits(intp, DISEQC_RESET, 1);
/*release DiseqC reset to enable the 22KHz tone*/
stv0900_write_bits(i_params, reset_field, 0);
stv0900_write_bits(intp, DISEQC_RESET, 0);
break;
case SEC_TONE_OFF:
/*return diseqc mode to config->diseqc_mode.
Usually it's without _continues_ tone */
stv0900_write_bits(i_params, mode_field,
stv0900_write_bits(intp, DISTX_MODE,
state->config->diseqc_mode);
/*maintain the DiseqC reset to disable the 22KHz tone*/
stv0900_write_bits(i_params, reset_field, 1);
stv0900_write_bits(i_params, reset_field, 0);
stv0900_write_bits(intp, DISEQC_RESET, 1);
stv0900_write_bits(intp, DISEQC_RESET, 0);
break;
default:
return -EINVAL;
......@@ -1993,13 +1806,13 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
init_params.rolloff = STV0900_35;
init_params.path1_ts_clock = config->path1_mode;
init_params.tun1_maddress = config->tun1_maddress;
init_params.tun1_iq_inversion = STV0900_IQ_NORMAL;
init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
init_params.tuner1_adc = config->tun1_adc;
init_params.path2_ts_clock = config->path2_mode;
init_params.ts_config = config->ts_config_regs;
init_params.tun2_maddress = config->tun2_maddress;
init_params.tuner2_adc = config->tun2_adc;
init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED;
init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
err_stv0900 = stv0900_init_internal(&state->frontend,
&init_params);
......
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