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Commit 1e87347c authored by Russell King's avatar Russell King
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable

parents f29251ff 3cff484d
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Showing with 2219 additions and 3521 deletions
arch/arm/mach-dove/common.c
View file @ 1e87347c
......@@ -16,10 +16,8 @@
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/spi/orion_spi.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
......@@ -32,11 +30,12 @@
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/mv_xor.h>
#include <plat/ehci-orion.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
static int get_tclk(void);
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
......@@ -69,464 +68,107 @@ void __init dove_map_io(void)
iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data dove_ehci_data = {
.dram = &dove_mbus_dram_info,
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource dove_ehci0_resources[] = {
{
.start = DOVE_USB0_PHYS_BASE,
.end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_USB0,
.end = IRQ_DOVE_USB0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &dove_ehci_data,
},
.resource = dove_ehci0_resources,
.num_resources = ARRAY_SIZE(dove_ehci0_resources),
};
void __init dove_ehci0_init(void)
{
platform_device_register(&dove_ehci0);
orion_ehci_init(&dove_mbus_dram_info,
DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource dove_ehci1_resources[] = {
{
.start = DOVE_USB1_PHYS_BASE,
.end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_USB1,
.end = IRQ_DOVE_USB1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &dove_ehci_data,
},
.resource = dove_ehci1_resources,
.num_resources = ARRAY_SIZE(dove_ehci1_resources),
};
void __init dove_ehci1_init(void)
{
platform_device_register(&dove_ehci1);
orion_ehci_1_init(&dove_mbus_dram_info,
DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
.t_clk = 0,
.dram = &dove_mbus_dram_info,
};
static struct resource dove_ge00_shared_resources[] = {
{
.name = "ge00 base",
.start = DOVE_GE00_PHYS_BASE + 0x2000,
.end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dove_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &dove_ge00_shared_data,
},
.num_resources = 1,
.resource = dove_ge00_shared_resources,
};
static struct resource dove_ge00_resources[] = {
{
.name = "ge00 irq",
.start = IRQ_DOVE_GE00_SUM,
.end = IRQ_DOVE_GE00_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = dove_ge00_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &dove_ge00_shared;
dove_ge00.dev.platform_data = eth_data;
platform_device_register(&dove_ge00_shared);
platform_device_register(&dove_ge00);
orion_ge00_init(eth_data, &dove_mbus_dram_info,
DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
0, get_tclk());
}
/*****************************************************************************
* SoC RTC
****************************************************************************/
static struct resource dove_rtc_resource[] = {
{
.start = DOVE_RTC_PHYS_BASE,
.end = DOVE_RTC_PHYS_BASE + 32 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_RTC,
.flags = IORESOURCE_IRQ,
}
};
void __init dove_rtc_init(void)
{
platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource dove_sata_resources[] = {
{
.name = "sata base",
.start = DOVE_SATA_PHYS_BASE,
.end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_DOVE_SATA,
.end = IRQ_DOVE_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(dove_sata_resources),
.resource = dove_sata_resources,
};
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
sata_data->dram = &dove_mbus_dram_info;
dove_sata.dev.platform_data = sata_data;
platform_device_register(&dove_sata);
orion_sata_init(sata_data, &dove_mbus_dram_info,
DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port dove_uart0_data[] = {
{
.mapbase = DOVE_UART0_PHYS_BASE,
.membase = (char *)DOVE_UART0_VIRT_BASE,
.irq = IRQ_DOVE_UART_0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart0_resources[] = {
{
.start = DOVE_UART0_PHYS_BASE,
.end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_0,
.end = IRQ_DOVE_UART_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = dove_uart0_data,
},
.resource = dove_uart0_resources,
.num_resources = ARRAY_SIZE(dove_uart0_resources),
};
void __init dove_uart0_init(void)
{
platform_device_register(&dove_uart0);
orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
IRQ_DOVE_UART_0, get_tclk());
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port dove_uart1_data[] = {
{
.mapbase = DOVE_UART1_PHYS_BASE,
.membase = (char *)DOVE_UART1_VIRT_BASE,
.irq = IRQ_DOVE_UART_1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart1_resources[] = {
{
.start = DOVE_UART1_PHYS_BASE,
.end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_1,
.end = IRQ_DOVE_UART_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = dove_uart1_data,
},
.resource = dove_uart1_resources,
.num_resources = ARRAY_SIZE(dove_uart1_resources),
};
void __init dove_uart1_init(void)
{
platform_device_register(&dove_uart1);
orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
IRQ_DOVE_UART_1, get_tclk());
}
/*****************************************************************************
* UART2
****************************************************************************/
static struct plat_serial8250_port dove_uart2_data[] = {
{
.mapbase = DOVE_UART2_PHYS_BASE,
.membase = (char *)DOVE_UART2_VIRT_BASE,
.irq = IRQ_DOVE_UART_2,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart2_resources[] = {
{
.start = DOVE_UART2_PHYS_BASE,
.end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_2,
.end = IRQ_DOVE_UART_2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart2 = {
.name = "serial8250",
.id = 2,
.dev = {
.platform_data = dove_uart2_data,
},
.resource = dove_uart2_resources,
.num_resources = ARRAY_SIZE(dove_uart2_resources),
};
void __init dove_uart2_init(void)
{
platform_device_register(&dove_uart2);
orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
IRQ_DOVE_UART_2, get_tclk());
}
/*****************************************************************************
* UART3
****************************************************************************/
static struct plat_serial8250_port dove_uart3_data[] = {
{
.mapbase = DOVE_UART3_PHYS_BASE,
.membase = (char *)DOVE_UART3_VIRT_BASE,
.irq = IRQ_DOVE_UART_3,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart3_resources[] = {
{
.start = DOVE_UART3_PHYS_BASE,
.end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_3,
.end = IRQ_DOVE_UART_3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart3 = {
.name = "serial8250",
.id = 3,
.dev = {
.platform_data = dove_uart3_data,
},
.resource = dove_uart3_resources,
.num_resources = ARRAY_SIZE(dove_uart3_resources),
};
void __init dove_uart3_init(void)
{
platform_device_register(&dove_uart3);
orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
IRQ_DOVE_UART_3, get_tclk());
}
/*****************************************************************************
* SPI0
* SPI
****************************************************************************/
static struct orion_spi_info dove_spi0_data = {
.tclk = 0,
};
static struct resource dove_spi0_resources[] = {
{
.start = DOVE_SPI0_PHYS_BASE,
.end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_SPI0,
.end = IRQ_DOVE_SPI0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_spi0 = {
.name = "orion_spi",
.id = 0,
.resource = dove_spi0_resources,
.dev = {
.platform_data = &dove_spi0_data,
},
.num_resources = ARRAY_SIZE(dove_spi0_resources),
};
void __init dove_spi0_init(void)
{
platform_device_register(&dove_spi0);
orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
}
/*****************************************************************************
* SPI1
****************************************************************************/
static struct orion_spi_info dove_spi1_data = {
.tclk = 0,
};
static struct resource dove_spi1_resources[] = {
{
.start = DOVE_SPI1_PHYS_BASE,
.end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_SPI1,
.end = IRQ_DOVE_SPI1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_spi1 = {
.name = "orion_spi",
.id = 1,
.resource = dove_spi1_resources,
.dev = {
.platform_data = &dove_spi1_data,
},
.num_resources = ARRAY_SIZE(dove_spi1_resources),
};
void __init dove_spi1_init(void)
{
platform_device_register(&dove_spi1);
orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata dove_i2c_data = {
.freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource dove_i2c_resources[] = {
{
.name = "i2c base",
.start = DOVE_I2C_PHYS_BASE,
.end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "i2c irq",
.start = IRQ_DOVE_I2C,
.end = IRQ_DOVE_I2C,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(dove_i2c_resources),
.resource = dove_i2c_resources,
.dev = {
.platform_data = &dove_i2c_data,
},
};
void __init dove_i2c_init(void)
{
platform_device_register(&dove_i2c);
orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}
/*****************************************************************************
......@@ -553,209 +195,23 @@ struct sys_timer dove_timer = {
.init = dove_timer_init,
};
/*****************************************************************************
* XOR
****************************************************************************/
static struct mv_xor_platform_shared_data dove_xor_shared_data = {
.dram = &dove_mbus_dram_info,
};
/*****************************************************************************
* XOR 0
****************************************************************************/
static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
static struct resource dove_xor0_shared_resources[] = {
{
.name = "xor 0 low",
.start = DOVE_XOR0_PHYS_BASE,
.end = DOVE_XOR0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.start = DOVE_XOR0_HIGH_PHYS_BASE,
.end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dove_xor0_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &dove_xor_shared_data,
},
.num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
.resource = dove_xor0_shared_resources,
};
static struct resource dove_xor00_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_00,
.end = IRQ_DOVE_XOR_00,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor00_data = {
.shared = &dove_xor0_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor00_channel = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(dove_xor00_resources),
.resource = dove_xor00_resources,
.dev = {
.dma_mask = &dove_xor0_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor00_data,
},
};
static struct resource dove_xor01_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_01,
.end = IRQ_DOVE_XOR_01,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor01_data = {
.shared = &dove_xor0_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor01_channel = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(dove_xor01_resources),
.resource = dove_xor01_resources,
.dev = {
.dma_mask = &dove_xor0_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor01_data,
},
};
void __init dove_xor0_init(void)
{
platform_device_register(&dove_xor0_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
platform_device_register(&dove_xor00_channel);
dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
platform_device_register(&dove_xor01_channel);
orion_xor0_init(&dove_mbus_dram_info,
DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}
/*****************************************************************************
* XOR 1
****************************************************************************/
static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
static struct resource dove_xor1_shared_resources[] = {
{
.name = "xor 0 low",
.start = DOVE_XOR1_PHYS_BASE,
.end = DOVE_XOR1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.start = DOVE_XOR1_HIGH_PHYS_BASE,
.end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dove_xor1_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &dove_xor_shared_data,
},
.num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
.resource = dove_xor1_shared_resources,
};
static struct resource dove_xor10_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_10,
.end = IRQ_DOVE_XOR_10,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor10_data = {
.shared = &dove_xor1_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor10_channel = {
.name = MV_XOR_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(dove_xor10_resources),
.resource = dove_xor10_resources,
.dev = {
.dma_mask = &dove_xor1_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor10_data,
},
};
static struct resource dove_xor11_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_11,
.end = IRQ_DOVE_XOR_11,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor11_data = {
.shared = &dove_xor1_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor11_channel = {
.name = MV_XOR_NAME,
.id = 3,
.num_resources = ARRAY_SIZE(dove_xor11_resources),
.resource = dove_xor11_resources,
.dev = {
.dma_mask = &dove_xor1_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor11_data,
},
};
void __init dove_xor1_init(void)
{
platform_device_register(&dove_xor1_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
platform_device_register(&dove_xor10_channel);
dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
platform_device_register(&dove_xor11_channel);
orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}
/*****************************************************************************
......@@ -833,14 +289,6 @@ void __init dove_init(void)
#endif
dove_setup_cpu_mbus();
dove_ge00_shared_data.t_clk = tclk;
dove_uart0_data[0].uartclk = tclk;
dove_uart1_data[0].uartclk = tclk;
dove_uart2_data[0].uartclk = tclk;
dove_uart3_data[0].uartclk = tclk;
dove_spi0_data.tclk = tclk;
dove_spi1_data.tclk = tclk;
/* internal devices that every board has */
dove_rtc_init();
dove_xor0_init();
......
arch/arm/mach-dove/mpp.c
View file @ 1e87347c
......@@ -11,24 +11,17 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <plat/mpp.h>
#include <mach/dove.h>
#include "mpp.h"
#define MPP_NR_REGS 4
#define MPP_CTRL(i) ((i) == 3 ? \
DOVE_MPP_CTRL4_VIRT_BASE : \
DOVE_MPP_VIRT_BASE + (i) * 4)
#define PMU_SIG_REGS 2
#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
struct dove_mpp_grp {
int start;
int end;
};
static struct dove_mpp_grp dove_mpp_grp[] = {
/* Map a group to a range of GPIO pins in that group */
static const struct dove_mpp_grp dove_mpp_grp[] = {
[MPP_24_39] = {
.start = 24,
.end = 39,
......@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
.end = 45,
},
[MPP_46_51] = {
.start = 40,
.end = 45,
.start = 46,
.end = 51,
},
[MPP_58_61] = {
.start = 58,
......@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
},
};
/* Enable gpio for a range of pins. mode should be a combination of
GPIO_OUTPUT_OK | GPIO_INPUT_OK */
static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
{
int i;
......@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
orion_gpio_set_valid(i, gpio_mode);
}
/* Dump all the extra MPP registers. The platform code will dump the
registers for pins 0-23. */
static void dove_mpp_dump_regs(void)
{
#ifdef DEBUG
int i;
pr_debug("PMU_CTRL4_CTRL: %08x\n",
readl(DOVE_MPP_CTRL4_VIRT_BASE));
pr_debug("MPP_CTRL regs:");
for (i = 0; i < MPP_NR_REGS; i++)
printk(" %08x", readl(MPP_CTRL(i)));
printk("\n");
pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
readl(DOVE_PMU_MPP_GENERAL_CTRL));
pr_debug("PMU_SIG_CTRL regs:");
for (i = 0; i < PMU_SIG_REGS; i++)
printk(" %08x", readl(PMU_SIG_CTRL(i)));
printk("\n");
pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
#endif
}
static void dove_mpp_cfg_nfc(int sel)
......@@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
static void dove_mpp_cfg_au1(int sel)
{
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
......@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
}
static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
{
int start = dove_mpp_grp[num].start;
int end = dove_mpp_grp[num].end;
int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
*mpp_ctrl &= ~(0x1 << num);
*mpp_ctrl |= sel << num;
dove_mpp_gpio_mode(start, end, gpio_mode);
}
void __init dove_mpp_conf(unsigned int *mpp_list)
/* Configure the group registers, enabling GPIO if sel indicates the
pin is to be used for GPIO */
static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
u32 pmu_mpp_ctrl = 0;
u32 pmu_sig_ctrl[PMU_SIG_REGS];
int i;
for (i = 0; i < MPP_NR_REGS; i++)
mpp_ctrl[i] = readl(MPP_CTRL(i));
for (i = 0; i < PMU_SIG_REGS; i++)
pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
int gpio_mode;
dove_mpp_dump_regs();
for ( ; *mpp_list != MPP_END; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
pr_err("dove: invalid MPP number (%u)\n", num);
continue;
}
if (*mpp_list & MPP_NFC_MASK) {
dove_mpp_cfg_nfc(sel);
continue;
}
for ( ; *mpp_grp_list; mpp_grp_list++) {
unsigned int num = MPP_NUM(*mpp_grp_list);
unsigned int sel = MPP_SEL(*mpp_grp_list);
if (*mpp_list & MPP_AU1_MASK) {
dove_mpp_cfg_au1(sel);
if (num > MPP_GRP_MAX) {
pr_err("dove: invalid MPP GRP number (%u)\n", num);
continue;
}
if (*mpp_list & MPP_GRP_MASK) {
dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
continue;
}
shift = (num & 7) << 2;
if (*mpp_list & MPP_PMU_MASK) {
pmu_mpp_ctrl |= (0x1 << num);
pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
pmu_sig_ctrl[num / 8] |= 0xf << shift;
gpio_mode = 0;
} else {
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
}
mpp_ctrl4 &= ~(0x1 << num);
mpp_ctrl4 |= sel << num;
orion_gpio_set_valid(num, gpio_mode);
gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
dove_mpp_gpio_mode(dove_mpp_grp[num].start,
dove_mpp_grp[num].end, gpio_mode);
}
writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
}
for (i = 0; i < MPP_NR_REGS; i++)
writel(mpp_ctrl[i], MPP_CTRL(i));
/* Configure the various MPP pins on Dove */
void __init dove_mpp_conf(unsigned int *mpp_list,
unsigned int *mpp_grp_list,
unsigned int grp_au1_52_57,
unsigned int grp_nfc_64_71)
{
dove_mpp_dump_regs();
for (i = 0; i < PMU_SIG_REGS; i++)
writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
/* Use platform code for pins 0-23 */
orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
dove_mpp_conf_grp(mpp_grp_list);
dove_mpp_cfg_au1(grp_au1_52_57);
dove_mpp_cfg_nfc(grp_nfc_64_71);
dove_mpp_dump_regs();
}
arch/arm/mach-dove/mpp.h
View file @ 1e87347c
#ifndef __ARCH_DOVE_MPP_CODED_H
#define __ARCH_DOVE_MPP_CODED_H
#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \
/* MPP/group number */ ((_num) & 0xff) | \
/* MPP select value */ (((_mode) & 0xf) << 8) | \
/* MPP PMU */ ((!!(_pmu)) << 12) | \
/* group flag */ ((!!(_grp)) << 13) | \
/* AU1 flag */ ((!!(_au1)) << 14) | \
/* NFCE flag */ ((!!(_nfc)) << 15))
#define MPP_MAX 71
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)
#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)
#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)
#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)
#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)
#define MPP_PMU_DRIVE_0 0x1
#define MPP_PMU_DRIVE_1 0x2
#define MPP_PMU_SDI 0x3
#define MPP_PMU_CPU_PWRDWN 0x4
#define MPP_PMU_STBY_PWRDWN 0x5
#define MPP_PMU_CORE_PWR_GOOD 0x8
#define MPP_PMU_BAT_FAULT 0xa
#define MPP_PMU_EXT0_WU 0xb
#define MPP_PMU_EXT1_WU 0xc
#define MPP_PMU_EXT2_WU 0xd
#define MPP_PMU_BLINK 0xe
#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)
#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)
#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)
#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)
#define MPP0_GPIO0 MPP_PIN(0, 0x0)
#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)
#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)
#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)
#define MPP1_GPIO1 MPP_PIN(1, 0x0)
#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)
#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)
#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)
#define MPP2_GPIO2 MPP_PIN(2, 0x0)
#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)
#define MPP2_UA2_TXD MPP_PIN(2, 0x2)
#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)
#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)
#define MPP3_GPIO3 MPP_PIN(3, 0x0)
#define MPP3_SATA_ACT MPP_PIN(3, 0x1)
#define MPP3_UA2_RXD MPP_PIN(3, 0x2)
#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)
#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)
#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)
#define MPP4_GPIO4 MPP_PIN(4, 0x0)
#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)
#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)
#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)
#define MPP5_GPIO5 MPP_PIN(5, 0x0)
#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)
#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)
#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)
#define MPP6_GPIO6 MPP_PIN(6, 0x0)
#define MPP6_UA3_TXD MPP_PIN(6, 0x2)
#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)
#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)
#define MPP7_GPIO7 MPP_PIN(7, 0x0)
#define MPP7_UA3_RXD MPP_PIN(7, 0x2)
#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)
#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)
#define MPP8_GPIO8 MPP_PIN(8, 0x0)
#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)
#define MPP9_GPIO9 MPP_PIN(9, 0x0)
#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)
#define MPP10_GPIO10 MPP_PIN(10, 0x0)
#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)
#define MPP11_GPIO11 MPP_PIN(11, 0x0)
#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)
#define MPP11_SATA_ACT MPP_PIN(11, 0x2)
#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)
#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)
#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)
#define MPP12_GPIO12 MPP_PIN(12, 0x0)
#define MPP12_SATA_ACT MPP_PIN(12, 0x1)
#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)
#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)
#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)
#define MPP13_GPIO13 MPP_PIN(13, 0x0)
#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)
#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)
#define MPP13_SDIO1WP MPP_PIN(13, 0x4)
#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)
#define MPP14_GPIO14 MPP_PIN(14, 0x0)
#define MPP14_UA2_TXD MPP_PIN(14, 0x2)
#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)
#define MPP14_SSP_RXD MPP_PIN(14, 0x5)
#define MPP15_GPIO15 MPP_PIN(15, 0x0)
#define MPP15_UA2_RXD MPP_PIN(15, 0x2)
#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)
#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)
#define MPP16_GPIO16 MPP_PIN(16, 0x0)
#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)
#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)
#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)
#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)
#define MPP17_GPIO17 MPP_PIN(17, 0x0)
#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)
#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)
#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)
#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)
#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)
#define MPP18_GPIO18 MPP_PIN(18, 0x0)
#define MPP18_UA3_TXD MPP_PIN(18, 0x2)
#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)
#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)
#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)
#define MPP19_GPIO19 MPP_PIN(19, 0x0)
#define MPP19_UA3_RXD MPP_PIN(19, 0x2)
#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)
#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)
#define MPP20_GPIO20 MPP_PIN(20, 0x0)
#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
#define MPP21_GPIO21 MPP_PIN(21, 0x0)
#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
#define MPP22_GPIO22 MPP_PIN(22, 0x0)
#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
#define MPP23_GPIO23 MPP_PIN(23, 0x0)
#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
#define MPP(_num, _sel, _in, _out) ( \
/* MPP number */ ((_num) & 0xff) | \
/* MPP select value */ (((_sel) & 0xf) << 8) | \
/* may be input signal */ ((!!(_in)) << 12) | \
/* may be output signal */ ((!!(_out)) << 13))
#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
#define MPP_MAX 23
#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
/* for MPP groups _num is a group index */
enum dove_mpp_grp_idx {
......@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
MPP_46_51 = 1,
MPP_58_61 = 5,
MPP_62_63 = 4,
MPP_GRP_MAX = 5,
};
#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)
#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)
#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
/* The MPP[64:71] control differs from other groups */
#define MPP64_71_GPO MPP_GRP_NFC(0x1)
#define MPP64_71_NFC MPP_GRP_NFC(0x0)
#define MPP_GRP_NFC_64_71_GPO 0x1
#define MPP_GRP_NFC_64_71_NFC 0x0
/*
* The MPP[52:57] functionality is encoded by 4 bits in different
* registers. The _num field in this case encodes those bits in
* correspodence with Table 135 of 88AP510 Functional specification
*/
#define MPP52_57_AU1 MPP_GRP_AU1(0x0)
#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)
#define MPP52_57_GPIO MPP_GRP_AU1(0xa)
#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)
#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)
#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)
#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)
void dove_mpp_conf(unsigned int *mpp_list);
#define MPP_GRP_AU1_52_57_AU1 0x0
#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
#define MPP_GRP_AU1_52_57_GPIO 0xa
#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
#define MPP_GRP_AU1_52_57_SSP_TW 0xf
void dove_mpp_conf(unsigned int *mpp_list,
unsigned int *mpp_grp_list,
unsigned int grp_au1_52_57,
unsigned int grp_nfc_64_71);
#endif /* __ARCH_DOVE_MPP_CODED_H */
arch/arm/mach-kirkwood/common.c
View file @ 1e87347c
......@@ -13,11 +13,9 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/mtd/nand.h>
#include <linux/spi/orion_spi.h>
#include <linux/dma-mapping.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/timex.h>
......@@ -28,11 +26,9 @@
#include <mach/bridge-regs.h>
#include <plat/audio.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/mvsdio.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/orion_wdt.h>
#include <plat/common.h>
#include <plat/time.h>
#include "common.h"
......@@ -69,210 +65,52 @@ void __init kirkwood_map_io(void)
* registered. Some reserved bits must be set to 1.
*/
unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data kirkwood_ehci_data = {
.dram = &kirkwood_mbus_dram_info,
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = 0xffffffffUL;
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource kirkwood_ehci_resources[] = {
{
.start = USB_PHYS_BASE,
.end = USB_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_USB,
.end = IRQ_KIRKWOOD_USB,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ehci = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &kirkwood_ehci_data,
},
.resource = kirkwood_ehci_resources,
.num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
};
void __init kirkwood_ehci_init(void)
{
kirkwood_clk_ctrl |= CGC_USB0;
platform_device_register(&kirkwood_ehci);
orion_ehci_init(&kirkwood_mbus_dram_info,
USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
.dram = &kirkwood_mbus_dram_info,
};
static struct resource kirkwood_ge00_shared_resources[] = {
{
.name = "ge00 base",
.start = GE00_PHYS_BASE + 0x2000,
.end = GE00_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.name = "ge00 err irq",
.start = IRQ_KIRKWOOD_GE00_ERR,
.end = IRQ_KIRKWOOD_GE00_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &kirkwood_ge00_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
.resource = kirkwood_ge00_shared_resources,
};
static struct resource kirkwood_ge00_resources[] = {
{
.name = "ge00 irq",
.start = IRQ_KIRKWOOD_GE00_SUM,
.end = IRQ_KIRKWOOD_GE00_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = kirkwood_ge00_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
kirkwood_clk_ctrl |= CGC_GE0;
eth_data->shared = &kirkwood_ge00_shared;
kirkwood_ge00.dev.platform_data = eth_data;
platform_device_register(&kirkwood_ge00_shared);
platform_device_register(&kirkwood_ge00);
orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
}
/*****************************************************************************
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
.dram = &kirkwood_mbus_dram_info,
.shared_smi = &kirkwood_ge00_shared,
};
static struct resource kirkwood_ge01_shared_resources[] = {
{
.name = "ge01 base",
.start = GE01_PHYS_BASE + 0x2000,
.end = GE01_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.name = "ge01 err irq",
.start = IRQ_KIRKWOOD_GE01_ERR,
.end = IRQ_KIRKWOOD_GE01_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge01_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &kirkwood_ge01_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
.resource = kirkwood_ge01_shared_resources,
};
static struct resource kirkwood_ge01_resources[] = {
{
.name = "ge01 irq",
.start = IRQ_KIRKWOOD_GE01_SUM,
.end = IRQ_KIRKWOOD_GE01_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge01 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = kirkwood_ge01_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
kirkwood_clk_ctrl |= CGC_GE1;
eth_data->shared = &kirkwood_ge01_shared;
kirkwood_ge01.dev.platform_data = eth_data;
platform_device_register(&kirkwood_ge01_shared);
platform_device_register(&kirkwood_ge01);
orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
}
/*****************************************************************************
* Ethernet switch
****************************************************************************/
static struct resource kirkwood_switch_resources[] = {
{
.start = 0,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_switch_device = {
.name = "dsa",
.id = 0,
.num_resources = 0,
.resource = kirkwood_switch_resources,
};
void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
{
int i;
if (irq != NO_IRQ) {
kirkwood_switch_resources[0].start = irq;
kirkwood_switch_resources[0].end = irq;
kirkwood_switch_device.num_resources = 1;
}
d->netdev = &kirkwood_ge00.dev;
for (i = 0; i < d->nr_chips; i++)
d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
kirkwood_switch_device.dev.platform_data = d;
platform_device_register(&kirkwood_switch_device);
orion_ge00_switch_init(d, irq);
}
......@@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
/*****************************************************************************
* SoC RTC
****************************************************************************/
static struct resource kirkwood_rtc_resource = {
.start = RTC_PHYS_BASE,
.end = RTC_PHYS_BASE + SZ_16 - 1,
.flags = IORESOURCE_MEM,
};
static void __init kirkwood_rtc_init(void)
{
platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource kirkwood_sata_resources[] = {
{
.name = "sata base",
.start = SATA_PHYS_BASE,
.end = SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_KIRKWOOD_SATA,
.end = IRQ_KIRKWOOD_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(kirkwood_sata_resources),
.resource = kirkwood_sata_resources,
};
void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
{
kirkwood_clk_ctrl |= CGC_SATA0;
if (sata_data->n_ports > 1)
kirkwood_clk_ctrl |= CGC_SATA1;
sata_data->dram = &kirkwood_mbus_dram_info;
kirkwood_sata.dev.platform_data = sata_data;
platform_device_register(&kirkwood_sata);
orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
}
......@@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = {
},
};
static u64 mvsdio_dmamask = 0xffffffffUL;
static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
static struct platform_device kirkwood_sdio = {
.name = "mvsdio",
.id = -1,
.dev = {
.dma_mask = &mvsdio_dmamask,
.coherent_dma_mask = 0xffffffff,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(mvsdio_resources),
.resource = mvsdio_resources,
......@@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
/*****************************************************************************
* SPI
****************************************************************************/
static struct orion_spi_info kirkwood_spi_plat_data = {
};
static struct resource kirkwood_spi_resources[] = {
{
.start = SPI_PHYS_BASE,
.end = SPI_PHYS_BASE + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_spi = {
.name = "orion_spi",
.id = 0,
.resource = kirkwood_spi_resources,
.dev = {
.platform_data = &kirkwood_spi_plat_data,
},
.num_resources = ARRAY_SIZE(kirkwood_spi_resources),
};
void __init kirkwood_spi_init()
{
kirkwood_clk_ctrl |= CGC_RUNIT;
platform_device_register(&kirkwood_spi);
orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource kirkwood_i2c_resources[] = {
{
.start = I2C_PHYS_BASE,
.end = I2C_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_TWSI,
.end = IRQ_KIRKWOOD_TWSI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
.resource = kirkwood_i2c_resources,
.dev = {
.platform_data = &kirkwood_i2c_pdata,
},
};
void __init kirkwood_i2c_init(void)
{
platform_device_register(&kirkwood_i2c);
orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port kirkwood_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_KIRKWOOD_UART_0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource kirkwood_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_UART_0,
.end = IRQ_KIRKWOOD_UART_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = kirkwood_uart0_data,
},
.resource = kirkwood_uart0_resources,
.num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
};
void __init kirkwood_uart0_init(void)
{
platform_device_register(&kirkwood_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port kirkwood_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_KIRKWOOD_UART_1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource kirkwood_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_UART_1,
.end = IRQ_KIRKWOOD_UART_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = kirkwood_uart1_data,
},
.resource = kirkwood_uart1_resources,
.num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
};
void __init kirkwood_uart1_init(void)
{
platform_device_register(&kirkwood_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
}
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
static struct resource kirkwood_crypto_res[] = {
{
.name = "regs",
.start = CRYPTO_PHYS_BASE,
.end = CRYPTO_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
}, {
.name = "sram",
.start = KIRKWOOD_SRAM_PHYS_BASE,
.end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "crypto interrupt",
.start = IRQ_KIRKWOOD_CRYPTO,
.end = IRQ_KIRKWOOD_CRYPTO,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_crypto_device = {
.name = "mv_crypto",
.id = -1,
.num_resources = ARRAY_SIZE(kirkwood_crypto_res),
.resource = kirkwood_crypto_res,
};
void __init kirkwood_crypto_init(void)
{
kirkwood_clk_ctrl |= CGC_CRYPTO;
platform_device_register(&kirkwood_crypto_device);
orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
}
/*****************************************************************************
* XOR
****************************************************************************/
static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
.dram = &kirkwood_mbus_dram_info,
};
static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* XOR0
****************************************************************************/
static struct resource kirkwood_xor0_shared_resources[] = {
{
.name = "xor 0 low",
.start = XOR0_PHYS_BASE,
.end = XOR0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.start = XOR0_HIGH_PHYS_BASE,
.end = XOR0_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_xor0_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &kirkwood_xor_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
.resource = kirkwood_xor0_shared_resources,
};
static struct resource kirkwood_xor00_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_00,
.end = IRQ_KIRKWOOD_XOR_00,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor00_data = {
.shared = &kirkwood_xor0_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor00_channel = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
.resource = kirkwood_xor00_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor00_data,
},
};
static struct resource kirkwood_xor01_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_01,
.end = IRQ_KIRKWOOD_XOR_01,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor01_data = {
.shared = &kirkwood_xor0_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor01_channel = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
.resource = kirkwood_xor01_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor01_data,
},
};
static void __init kirkwood_xor0_init(void)
{
kirkwood_clk_ctrl |= CGC_XOR0;
platform_device_register(&kirkwood_xor0_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
platform_device_register(&kirkwood_xor00_channel);
dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
platform_device_register(&kirkwood_xor01_channel);
orion_xor0_init(&kirkwood_mbus_dram_info,
XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
}
/*****************************************************************************
* XOR1
****************************************************************************/
static struct resource kirkwood_xor1_shared_resources[] = {
{
.name = "xor 1 low",
.start = XOR1_PHYS_BASE,
.end = XOR1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 1 high",
.start = XOR1_HIGH_PHYS_BASE,
.end = XOR1_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_xor1_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &kirkwood_xor_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
.resource = kirkwood_xor1_shared_resources,
};
static struct resource kirkwood_xor10_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_10,
.end = IRQ_KIRKWOOD_XOR_10,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor10_data = {
.shared = &kirkwood_xor1_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor10_channel = {
.name = MV_XOR_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
.resource = kirkwood_xor10_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor10_data,
},
};
static struct resource kirkwood_xor11_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_11,
.end = IRQ_KIRKWOOD_XOR_11,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor11_data = {
.shared = &kirkwood_xor1_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor11_channel = {
.name = MV_XOR_NAME,
.id = 3,
.num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
.resource = kirkwood_xor11_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor11_data,
},
};
static void __init kirkwood_xor1_init(void)
{
kirkwood_clk_ctrl |= CGC_XOR1;
platform_device_register(&kirkwood_xor1_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
platform_device_register(&kirkwood_xor10_channel);
dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
platform_device_register(&kirkwood_xor11_channel);
orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct orion_wdt_platform_data kirkwood_wdt_data = {
.tclk = 0,
};
static struct platform_device kirkwood_wdt_device = {
.name = "orion_wdt",
.id = -1,
.dev = {
.platform_data = &kirkwood_wdt_data,
},
.num_resources = 0,
};
static void __init kirkwood_wdt_init(void)
{
kirkwood_wdt_data.tclk = kirkwood_tclk;
platform_device_register(&kirkwood_wdt_device);
orion_wdt_init(kirkwood_tclk);
}
......@@ -984,11 +452,6 @@ void __init kirkwood_init(void)
{
printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
kirkwood_id(), kirkwood_tclk);
kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
kirkwood_spi_plat_data.tclk = kirkwood_tclk;
kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
kirkwood_i2s_data.tclk = kirkwood_tclk;
/*
......
arch/arm/mach-kirkwood/include/mach/irqs.h
View file @ 1e87347c
......@@ -51,6 +51,7 @@
#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
#define IRQ_KIRKWOOD_GE00_ERR 46
#define IRQ_KIRKWOOD_GE01_ERR 47
#define IRQ_KIRKWOOD_RTC 53
/*
* KIRKWOOD General Purpose Pins
......
arch/arm/mach-kirkwood/mpp.c
View file @ 1e87347c
......@@ -14,6 +14,7 @@
#include <linux/io.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
#include <plat/mpp.h>
#include "common.h"
#include "mpp.h"
......@@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void)
return 0;
}
#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
#define MPP_NR_REGS (1 + MPP_MAX/8)
void __init kirkwood_mpp_conf(unsigned int *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
int i;
variant_mask = kirkwood_variant();
if (!variant_mask)
return;
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (!(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"kirkwood_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = 0;
if (*mpp_list & MPP_INPUT_MASK)
gpio_mode |= GPIO_INPUT_OK;
if (*mpp_list & MPP_OUTPUT_MASK)
gpio_mode |= GPIO_OUTPUT_OK;
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
}
printk(KERN_DEBUG " final MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
writel(mpp_ctrl[i], MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
orion_mpp_conf(mpp_list, kirkwood_variant(),
MPP_MAX, DEV_BUS_VIRT_BASE);
}
arch/arm/mach-kirkwood/mpp.h
View file @ 1e87347c
......@@ -22,14 +22,8 @@
/* available on F6281 */ ((!!(_F6281)) << 17) | \
/* available on F6282 */ ((!!(_F6282)) << 18))
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
/* num sel i o 6180 6190 6192 6281 6282 */
#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
......
arch/arm/mach-loki/common.c
View file @ 1e87347c
......@@ -13,7 +13,7 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/dma-mapping.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
......@@ -22,6 +22,7 @@
#include <mach/loki.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
/*****************************************************************************
......@@ -43,116 +44,28 @@ void __init loki_map_io(void)
/*****************************************************************************
* GE0
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
.t_clk = LOKI_TCLK,
.dram = &loki_mbus_dram_info,
};
static struct resource loki_ge0_shared_resources[] = {
{
.name = "ge0 base",
.start = GE0_PHYS_BASE + 0x2000,
.end = GE0_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device loki_ge0_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &loki_ge0_shared_data,
},
.num_resources = 1,
.resource = loki_ge0_shared_resources,
};
static struct resource loki_ge0_resources[] = {
{
.name = "ge0 irq",
.start = IRQ_LOKI_GBE_A_INT,
.end = IRQ_LOKI_GBE_A_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_ge0 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = loki_ge0_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &loki_ge0_shared;
loki_ge0.dev.platform_data = eth_data;
writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
platform_device_register(&loki_ge0_shared);
platform_device_register(&loki_ge0);
orion_ge00_init(eth_data, &loki_mbus_dram_info,
GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
0, LOKI_TCLK);
}
/*****************************************************************************
* GE1
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
.t_clk = LOKI_TCLK,
.dram = &loki_mbus_dram_info,
};
static struct resource loki_ge1_shared_resources[] = {
{
.name = "ge1 base",
.start = GE1_PHYS_BASE + 0x2000,
.end = GE1_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device loki_ge1_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &loki_ge1_shared_data,
},
.num_resources = 1,
.resource = loki_ge1_shared_resources,
};
static struct resource loki_ge1_resources[] = {
{
.name = "ge1 irq",
.start = IRQ_LOKI_GBE_B_INT,
.end = IRQ_LOKI_GBE_B_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_ge1 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = loki_ge1_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &loki_ge1_shared;
loki_ge1.dev.platform_data = eth_data;
writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
platform_device_register(&loki_ge1_shared);
platform_device_register(&loki_ge1);
orion_ge01_init(eth_data, &loki_mbus_dram_info,
GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
0, LOKI_TCLK);
}
......@@ -187,7 +100,7 @@ static struct platform_device loki_sas = {
.name = "mvsas",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(loki_sas_resources),
.resource = loki_sas_resources,
......@@ -203,88 +116,19 @@ void __init loki_sas_init(void)
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port loki_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_LOKI_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = LOKI_TCLK,
}, {
},
};
static struct resource loki_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LOKI_UART0,
.end = IRQ_LOKI_UART0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = loki_uart0_data,
},
.resource = loki_uart0_resources,
.num_resources = ARRAY_SIZE(loki_uart0_resources),
};
void __init loki_uart0_init(void)
{
platform_device_register(&loki_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_LOKI_UART0, LOKI_TCLK);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port loki_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_LOKI_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = LOKI_TCLK,
}, {
},
};
static struct resource loki_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LOKI_UART1,
.end = IRQ_LOKI_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = loki_uart1_data,
},
.resource = loki_uart1_resources,
.num_resources = ARRAY_SIZE(loki_uart1_resources),
};
void __init loki_uart1_init(void)
{
platform_device_register(&loki_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_LOKI_UART1, LOKI_TCLK);
}
......
arch/arm/mach-mv78xx0/common.c
View file @ 1e87347c
......@@ -13,8 +13,6 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/ethtool.h>
#include <asm/mach/map.h>
......@@ -22,11 +20,12 @@
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
static int get_tclk(void);
/*****************************************************************************
* Common bits
......@@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void)
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data mv78xx0_ehci_data = {
.dram = &mv78xx0_mbus_dram_info,
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = 0xffffffffUL;
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource mv78xx0_ehci0_resources[] = {
{
.start = USB0_PHYS_BASE,
.end = USB0_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_USB_0,
.end = IRQ_MV78XX0_USB_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mv78xx0_ehci_data,
},
.resource = mv78xx0_ehci0_resources,
.num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
};
void __init mv78xx0_ehci0_init(void)
{
platform_device_register(&mv78xx0_ehci0);
orion_ehci_init(&mv78xx0_mbus_dram_info,
USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource mv78xx0_ehci1_resources[] = {
{
.start = USB1_PHYS_BASE,
.end = USB1_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_USB_1,
.end = IRQ_MV78XX0_USB_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mv78xx0_ehci_data,
},
.resource = mv78xx0_ehci1_resources,
.num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
};
void __init mv78xx0_ehci1_init(void)
{
platform_device_register(&mv78xx0_ehci1);
orion_ehci_1_init(&mv78xx0_mbus_dram_info,
USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}
/*****************************************************************************
* EHCI2
****************************************************************************/
static struct resource mv78xx0_ehci2_resources[] = {
{
.start = USB2_PHYS_BASE,
.end = USB2_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_USB_2,
.end = IRQ_MV78XX0_USB_2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ehci2 = {
.name = "orion-ehci",
.id = 2,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mv78xx0_ehci_data,
},
.resource = mv78xx0_ehci2_resources,
.num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
};
void __init mv78xx0_ehci2_init(void)
{
platform_device_register(&mv78xx0_ehci2);
orion_ehci_2_init(&mv78xx0_mbus_dram_info,
USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
};
static struct resource mv78xx0_ge00_shared_resources[] = {
{
.name = "ge00 base",
.start = GE00_PHYS_BASE + 0x2000,
.end = GE00_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.name = "ge err irq",
.start = IRQ_MV78XX0_GE_ERR,
.end = IRQ_MV78XX0_GE_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &mv78xx0_ge00_shared_data,
},
.num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
.resource = mv78xx0_ge00_shared_resources,
};
static struct resource mv78xx0_ge00_resources[] = {
{
.name = "ge00 irq",
.start = IRQ_MV78XX0_GE00_SUM,
.end = IRQ_MV78XX0_GE00_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = mv78xx0_ge00_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &mv78xx0_ge00_shared;
mv78xx0_ge00.dev.platform_data = eth_data;
platform_device_register(&mv78xx0_ge00_shared);
platform_device_register(&mv78xx0_ge00);
orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
IRQ_MV78XX0_GE_ERR, get_tclk());
}
/*****************************************************************************
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
.shared_smi = &mv78xx0_ge00_shared,
};
static struct resource mv78xx0_ge01_shared_resources[] = {
{
.name = "ge01 base",
.start = GE01_PHYS_BASE + 0x2000,
.end = GE01_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv78xx0_ge01_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &mv78xx0_ge01_shared_data,
},
.num_resources = 1,
.resource = mv78xx0_ge01_shared_resources,
};
static struct resource mv78xx0_ge01_resources[] = {
{
.name = "ge01 irq",
.start = IRQ_MV78XX0_GE01_SUM,
.end = IRQ_MV78XX0_GE01_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge01 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = mv78xx0_ge01_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &mv78xx0_ge01_shared;
mv78xx0_ge01.dev.platform_data = eth_data;
platform_device_register(&mv78xx0_ge01_shared);
platform_device_register(&mv78xx0_ge01);
orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
NO_IRQ, get_tclk());
}
/*****************************************************************************
* GE10
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
.shared_smi = &mv78xx0_ge00_shared,
};
static struct resource mv78xx0_ge10_shared_resources[] = {
{
.name = "ge10 base",
.start = GE10_PHYS_BASE + 0x2000,
.end = GE10_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv78xx0_ge10_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 2,
.dev = {
.platform_data = &mv78xx0_ge10_shared_data,
},
.num_resources = 1,
.resource = mv78xx0_ge10_shared_resources,
};
static struct resource mv78xx0_ge10_resources[] = {
{
.name = "ge10 irq",
.start = IRQ_MV78XX0_GE10_SUM,
.end = IRQ_MV78XX0_GE10_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge10 = {
.name = MV643XX_ETH_NAME,
.id = 2,
.num_resources = 1,
.resource = mv78xx0_ge10_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
{
u32 dev, rev;
eth_data->shared = &mv78xx0_ge10_shared;
mv78xx0_ge10.dev.platform_data = eth_data;
/*
* On the Z0, ge10 and ge11 are internally connected back
* to back, and not brought out.
......@@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
eth_data->duplex = DUPLEX_FULL;
}
platform_device_register(&mv78xx0_ge10_shared);
platform_device_register(&mv78xx0_ge10);
orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
NO_IRQ, get_tclk());
}
/*****************************************************************************
* GE11
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
.shared_smi = &mv78xx0_ge00_shared,
};
static struct resource mv78xx0_ge11_shared_resources[] = {
{
.name = "ge11 base",
.start = GE11_PHYS_BASE + 0x2000,
.end = GE11_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv78xx0_ge11_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 3,
.dev = {
.platform_data = &mv78xx0_ge11_shared_data,
},
.num_resources = 1,
.resource = mv78xx0_ge11_shared_resources,
};
static struct resource mv78xx0_ge11_resources[] = {
{
.name = "ge11 irq",
.start = IRQ_MV78XX0_GE11_SUM,
.end = IRQ_MV78XX0_GE11_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge11 = {
.name = MV643XX_ETH_NAME,
.id = 3,
.num_resources = 1,
.resource = mv78xx0_ge11_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
{
u32 dev, rev;
eth_data->shared = &mv78xx0_ge11_shared;
mv78xx0_ge11.dev.platform_data = eth_data;
/*
* On the Z0, ge10 and ge11 are internally connected back
* to back, and not brought out.
......@@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
eth_data->duplex = DUPLEX_FULL;
}
platform_device_register(&mv78xx0_ge11_shared);
platform_device_register(&mv78xx0_ge11);
orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
NO_IRQ, get_tclk());
}
/*****************************************************************************
* I2C bus 0
****************************************************************************/
static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource mv78xx0_i2c_0_resources[] = {
{
.start = I2C_0_PHYS_BASE,
.end = I2C_0_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_I2C_0,
.end = IRQ_MV78XX0_I2C_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_i2c_0 = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
.resource = mv78xx0_i2c_0_resources,
.dev = {
.platform_data = &mv78xx0_i2c_0_pdata,
},
};
/*****************************************************************************
* I2C bus 1
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource mv78xx0_i2c_1_resources[] = {
{
.start = I2C_1_PHYS_BASE,
.end = I2C_1_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_I2C_1,
.end = IRQ_MV78XX0_I2C_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_i2c_1 = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
.resource = mv78xx0_i2c_1_resources,
.dev = {
.platform_data = &mv78xx0_i2c_1_pdata,
},
};
void __init mv78xx0_i2c_init(void)
{
platform_device_register(&mv78xx0_i2c_0);
platform_device_register(&mv78xx0_i2c_1);
orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource mv78xx0_sata_resources[] = {
{
.name = "sata base",
.start = SATA_PHYS_BASE,
.end = SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_MV78XX0_SATA,
.end = IRQ_MV78XX0_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
.resource = mv78xx0_sata_resources,
};
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
sata_data->dram = &mv78xx0_mbus_dram_info;
mv78xx0_sata.dev.platform_data = sata_data;
platform_device_register(&mv78xx0_sata);
orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_0,
.end = IRQ_MV78XX0_UART_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = mv78xx0_uart0_data,
},
.resource = mv78xx0_uart0_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
};
void __init mv78xx0_uart0_init(void)
{
platform_device_register(&mv78xx0_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_MV78XX0_UART_0, get_tclk());
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_1,
.end = IRQ_MV78XX0_UART_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = mv78xx0_uart1_data,
},
.resource = mv78xx0_uart1_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
};
void __init mv78xx0_uart1_init(void)
{
platform_device_register(&mv78xx0_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_MV78XX0_UART_1, get_tclk());
}
/*****************************************************************************
* UART2
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart2_data[] = {
{
.mapbase = UART2_PHYS_BASE,
.membase = (char *)UART2_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_2,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart2_resources[] = {
{
.start = UART2_PHYS_BASE,
.end = UART2_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_2,
.end = IRQ_MV78XX0_UART_2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart2 = {
.name = "serial8250",
.id = 2,
.dev = {
.platform_data = mv78xx0_uart2_data,
},
.resource = mv78xx0_uart2_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
};
void __init mv78xx0_uart2_init(void)
{
platform_device_register(&mv78xx0_uart2);
orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
IRQ_MV78XX0_UART_2, get_tclk());
}
/*****************************************************************************
* UART3
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart3_data[] = {
{
.mapbase = UART3_PHYS_BASE,
.membase = (char *)UART3_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_3,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart3_resources[] = {
{
.start = UART3_PHYS_BASE,
.end = UART3_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_3,
.end = IRQ_MV78XX0_UART_3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart3 = {
.name = "serial8250",
.id = 3,
.dev = {
.platform_data = mv78xx0_uart3_data,
},
.resource = mv78xx0_uart3_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
};
void __init mv78xx0_uart3_init(void)
{
platform_device_register(&mv78xx0_uart3);
orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
IRQ_MV78XX0_UART_3, get_tclk());
}
/*****************************************************************************
* Time handling
****************************************************************************/
......@@ -895,13 +400,4 @@ void __init mv78xx0_init(void)
#ifdef CONFIG_CACHE_FEROCEON_L2
feroceon_l2_init(is_l2_writethrough());
#endif
mv78xx0_ge00_shared_data.t_clk = tclk;
mv78xx0_ge01_shared_data.t_clk = tclk;
mv78xx0_ge10_shared_data.t_clk = tclk;
mv78xx0_ge11_shared_data.t_clk = tclk;
mv78xx0_uart0_data[0].uartclk = tclk;
mv78xx0_uart1_data[0].uartclk = tclk;
mv78xx0_uart2_data[0].uartclk = tclk;
mv78xx0_uart3_data[0].uartclk = tclk;
}
arch/arm/mach-mv78xx0/mpp.c
View file @ 1e87347c
......@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <plat/mpp.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
#include "common.h"
......@@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void)
return 0;
}
#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
#define MPP_NR_REGS (1 + MPP_MAX/8)
void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
int i;
variant_mask = mv78xx0_variant();
if (!variant_mask)
return;
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (!(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"mv78xx0_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = 0;
if (*mpp_list & MPP_INPUT_MASK)
gpio_mode |= GPIO_INPUT_OK;
if (*mpp_list & MPP_OUTPUT_MASK)
gpio_mode |= GPIO_OUTPUT_OK;
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
}
printk(KERN_DEBUG " final MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
writel(mpp_ctrl[i], MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
orion_mpp_conf(mpp_list, mv78xx0_variant(),
MPP_MAX, DEV_BUS_VIRT_BASE);
}
arch/arm/mach-mv78xx0/mpp.h
View file @ 1e87347c
......@@ -19,14 +19,8 @@
/* may be output signal */ ((!!(_out)) << 13) | \
/* available on A0 */ ((!!(_78100_A0)) << 14))
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
/* num sel i o 78100_A0 */
#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0)
#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0)
#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
......
arch/arm/mach-orion5x/common.c
View file @ 1e87347c
......@@ -13,12 +13,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/spi/orion_spi.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/setup.h>
......@@ -29,11 +28,9 @@
#include <mach/bridge-regs.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/orion_wdt.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
/*****************************************************************************
......@@ -69,531 +66,125 @@ void __init orion5x_map_io(void)
}
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data orion5x_ehci_data = {
.dram = &orion5x_mbus_dram_info,
.phy_version = EHCI_PHY_ORION,
};
static u64 ehci_dmamask = 0xffffffffUL;
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource orion5x_ehci0_resources[] = {
{
.start = ORION5X_USB0_PHYS_BASE,
.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ORION5X_USB0_CTRL,
.end = IRQ_ORION5X_USB0_CTRL,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &orion5x_ehci_data,
},
.resource = orion5x_ehci0_resources,
.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
};
void __init orion5x_ehci0_init(void)
{
platform_device_register(&orion5x_ehci0);
orion_ehci_init(&orion5x_mbus_dram_info,
ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource orion5x_ehci1_resources[] = {
{
.start = ORION5X_USB1_PHYS_BASE,
.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ORION5X_USB1_CTRL,
.end = IRQ_ORION5X_USB1_CTRL,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &orion5x_ehci_data,
},
.resource = orion5x_ehci1_resources,
.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
};
void __init orion5x_ehci1_init(void)
{
platform_device_register(&orion5x_ehci1);
orion_ehci_1_init(&orion5x_mbus_dram_info,
ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
}
/*****************************************************************************
* GigE
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
.dram = &orion5x_mbus_dram_info,
};
static struct resource orion5x_eth_shared_resources[] = {
{
.start = ORION5X_ETH_PHYS_BASE + 0x2000,
.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ORION5X_ETH_ERR,
.end = IRQ_ORION5X_ETH_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_eth_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &orion5x_eth_shared_data,
},
.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
.resource = orion5x_eth_shared_resources,
};
static struct resource orion5x_eth_resources[] = {
{
.name = "eth irq",
.start = IRQ_ORION5X_ETH_SUM,
.end = IRQ_ORION5X_ETH_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_eth = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = orion5x_eth_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &orion5x_eth_shared;
orion5x_eth.dev.platform_data = eth_data;
platform_device_register(&orion5x_eth_shared);
platform_device_register(&orion5x_eth);
orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
IRQ_ORION5X_ETH_ERR, orion5x_tclk);
}
/*****************************************************************************
* Ethernet switch
****************************************************************************/
static struct resource orion5x_switch_resources[] = {
{
.start = 0,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_switch_device = {
.name = "dsa",
.id = 0,
.num_resources = 0,
.resource = orion5x_switch_resources,
};
void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
{
int i;
if (irq != NO_IRQ) {
orion5x_switch_resources[0].start = irq;
orion5x_switch_resources[0].end = irq;
orion5x_switch_device.num_resources = 1;
}
d->netdev = &orion5x_eth.dev;
for (i = 0; i < d->nr_chips; i++)
d->chip[i].mii_bus = &orion5x_eth_shared.dev;
orion5x_switch_device.dev.platform_data = d;
platform_device_register(&orion5x_switch_device);
orion_ge00_switch_init(d, irq);
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion5x_i2c_resources[] = {
{
.start = I2C_PHYS_BASE,
.end = I2C_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ORION5X_I2C,
.end = IRQ_ORION5X_I2C,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
.resource = orion5x_i2c_resources,
.dev = {
.platform_data = &orion5x_i2c_pdata,
},
};
void __init orion5x_i2c_init(void)
{
platform_device_register(&orion5x_i2c);
orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource orion5x_sata_resources[] = {
{
.name = "sata base",
.start = ORION5X_SATA_PHYS_BASE,
.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_ORION5X_SATA,
.end = IRQ_ORION5X_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(orion5x_sata_resources),
.resource = orion5x_sata_resources,
};
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
sata_data->dram = &orion5x_mbus_dram_info;
orion5x_sata.dev.platform_data = sata_data;
platform_device_register(&orion5x_sata);
orion_sata_init(sata_data, &orion5x_mbus_dram_info,
ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
}
/*****************************************************************************
* SPI
****************************************************************************/
static struct orion_spi_info orion5x_spi_plat_data = {
.tclk = 0,
.enable_clock_fix = 1,
};
static struct resource orion5x_spi_resources[] = {
{
.name = "spi base",
.start = SPI_PHYS_BASE,
.end = SPI_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion5x_spi = {
.name = "orion_spi",
.id = 0,
.dev = {
.platform_data = &orion5x_spi_plat_data,
},
.num_resources = ARRAY_SIZE(orion5x_spi_resources),
.resource = orion5x_spi_resources,
};
void __init orion5x_spi_init()
{
platform_device_register(&orion5x_spi);
orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port orion5x_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_ORION5X_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource orion5x_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ORION5X_UART0,
.end = IRQ_ORION5X_UART0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_uart0 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = orion5x_uart0_data,
},
.resource = orion5x_uart0_resources,
.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
};
void __init orion5x_uart0_init(void)
{
platform_device_register(&orion5x_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_ORION5X_UART0, orion5x_tclk);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port orion5x_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_ORION5X_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource orion5x_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ORION5X_UART1,
.end = IRQ_ORION5X_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_uart1 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = orion5x_uart1_data,
},
.resource = orion5x_uart1_resources,
.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
};
void __init orion5x_uart1_init(void)
{
platform_device_register(&orion5x_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_ORION5X_UART1, orion5x_tclk);
}
/*****************************************************************************
* XOR engine
****************************************************************************/
struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
.dram = &orion5x_mbus_dram_info,
};
static struct resource orion5x_xor_shared_resources[] = {
{
.name = "xor low",
.start = ORION5X_XOR_PHYS_BASE,
.end = ORION5X_XOR_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor high",
.start = ORION5X_XOR_PHYS_BASE + 0x200,
.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion5x_xor_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &orion5x_xor_shared_data,
},
.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
.resource = orion5x_xor_shared_resources,
};
static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
static struct resource orion5x_xor0_resources[] = {
[0] = {
.start = IRQ_ORION5X_XOR0,
.end = IRQ_ORION5X_XOR0,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data orion5x_xor0_data = {
.shared = &orion5x_xor_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device orion5x_xor0_channel = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
.resource = orion5x_xor0_resources,
.dev = {
.dma_mask = &orion5x_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &orion5x_xor0_data,
},
};
static struct resource orion5x_xor1_resources[] = {
[0] = {
.start = IRQ_ORION5X_XOR1,
.end = IRQ_ORION5X_XOR1,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data orion5x_xor1_data = {
.shared = &orion5x_xor_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device orion5x_xor1_channel = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
.resource = orion5x_xor1_resources,
.dev = {
.dma_mask = &orion5x_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &orion5x_xor1_data,
},
};
void __init orion5x_xor_init(void)
{
platform_device_register(&orion5x_xor_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
platform_device_register(&orion5x_xor0_channel);
dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
platform_device_register(&orion5x_xor1_channel);
orion_xor0_init(&orion5x_mbus_dram_info,
ORION5X_XOR_PHYS_BASE,
ORION5X_XOR_PHYS_BASE + 0x200,
IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
}
static struct resource orion5x_crypto_res[] = {
{
.name = "regs",
.start = ORION5X_CRYPTO_PHYS_BASE,
.end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
}, {
.name = "sram",
.start = ORION5X_SRAM_PHYS_BASE,
.end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "crypto interrupt",
.start = IRQ_ORION5X_CESA,
.end = IRQ_ORION5X_CESA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion5x_crypto_device = {
.name = "mv_crypto",
.id = -1,
.num_resources = ARRAY_SIZE(orion5x_crypto_res),
.resource = orion5x_crypto_res,
};
static int __init orion5x_crypto_init(void)
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
static void __init orion5x_crypto_init(void)
{
int ret;
ret = orion5x_setup_sram_win();
if (ret)
return ret;
return;
return platform_device_register(&orion5x_crypto_device);
orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
SZ_8K, IRQ_ORION5X_CESA);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct orion_wdt_platform_data orion5x_wdt_data = {
.tclk = 0,
};
static struct platform_device orion5x_wdt_device = {
.name = "orion_wdt",
.id = -1,
.dev = {
.platform_data = &orion5x_wdt_data,
},
.num_resources = 0,
};
void __init orion5x_wdt_init(void)
{
orion5x_wdt_data.tclk = orion5x_tclk;
platform_device_register(&orion5x_wdt_device);
orion_wdt_init(orion5x_tclk);
}
......@@ -685,11 +276,6 @@ void __init orion5x_init(void)
orion5x_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
orion5x_eth_shared_data.t_clk = orion5x_tclk;
orion5x_spi_plat_data.tclk = orion5x_tclk;
orion5x_uart0_data[0].uartclk = orion5x_tclk;
orion5x_uart1_data[0].uartclk = orion5x_tclk;
/*
* Setup Orion address map
*/
......
arch/arm/mach-orion5x/d2net-setup.c
View file @ 1e87347c
......@@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = {
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Board ID (bit 0) */
{ 1, MPP_GPIO }, /* Board ID (bit 1) */
{ 2, MPP_GPIO }, /* Board ID (bit 2) */
{ 3, MPP_GPIO }, /* SATA 0 power */
{ 4, MPP_UNUSED },
{ 5, MPP_GPIO }, /* Fan fail detection */
{ 6, MPP_GPIO }, /* Red front LED */
{ 7, MPP_UNUSED },
{ 8, MPP_GPIO }, /* Rear power switch (on|auto) */
{ 9, MPP_GPIO }, /* Rear power switch (auto|off) */
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_GPIO }, /* SATA 1 power */
{ 13, MPP_UNUSED },
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
{ 16, MPP_GPIO }, /* Blue front LED blink control */
{ 17, MPP_UNUSED },
{ 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */
{ 19, MPP_UNUSED },
{ -1 }
static unsigned int d2net_mpp_modes[] __initdata = {
MPP0_GPIO, /* Board ID (bit 0) */
MPP1_GPIO, /* Board ID (bit 1) */
MPP2_GPIO, /* Board ID (bit 2) */
MPP3_GPIO, /* SATA 0 power */
MPP4_UNUSED,
MPP5_GPIO, /* Fan fail detection */
MPP6_GPIO, /* Red front LED */
MPP7_UNUSED,
MPP8_GPIO, /* Rear power switch (on|auto) */
MPP9_GPIO, /* Rear power switch (auto|off) */
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_GPIO, /* SATA 1 power */
MPP13_UNUSED,
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_GPIO, /* Blue front LED blink control */
MPP17_UNUSED,
MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
MPP19_UNUSED,
0,
/* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
/* 23: Blue front LED off */
/* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
......
arch/arm/mach-orion5x/db88f5281-setup.c
View file @ 1e87347c
......@@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* USB Over Current */
{ 1, MPP_GPIO }, /* USB Vbat input */
{ 2, MPP_PCI_ARB }, /* PCI_REQn[2] */
{ 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */
{ 4, MPP_PCI_ARB }, /* PCI_REQn[3] */
{ 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */
{ 6, MPP_GPIO }, /* JP0, CON17.2 */
{ 7, MPP_GPIO }, /* JP1, CON17.1 */
{ 8, MPP_GPIO }, /* JP2, CON11.2 */
{ 9, MPP_GPIO }, /* JP3, CON11.3 */
{ 10, MPP_GPIO }, /* RTC int */
{ 11, MPP_GPIO }, /* Baud Rate Generator */
{ 12, MPP_GPIO }, /* PCI int 1 */
{ 13, MPP_GPIO }, /* PCI int 2 */
{ 14, MPP_NAND }, /* NAND_REn[2] */
{ 15, MPP_NAND }, /* NAND_WEn[2] */
{ 16, MPP_UART }, /* UART1_RX */
{ 17, MPP_UART }, /* UART1_TX */
{ 18, MPP_UART }, /* UART1_CTSn */
{ 19, MPP_UART }, /* UART1_RTSn */
{ -1 },
static unsigned int db88f5281_mpp_modes[] __initdata = {
MPP0_GPIO, /* USB Over Current */
MPP1_GPIO, /* USB Vbat input */
MPP2_PCI_ARB, /* PCI_REQn[2] */
MPP3_PCI_ARB, /* PCI_GNTn[2] */
MPP4_PCI_ARB, /* PCI_REQn[3] */
MPP5_PCI_ARB, /* PCI_GNTn[3] */
MPP6_GPIO, /* JP0, CON17.2 */
MPP7_GPIO, /* JP1, CON17.1 */
MPP8_GPIO, /* JP2, CON11.2 */
MPP9_GPIO, /* JP3, CON11.3 */
MPP10_GPIO, /* RTC int */
MPP11_GPIO, /* Baud Rate Generator */
MPP12_GPIO, /* PCI int 1 */
MPP13_GPIO, /* PCI int 2 */
MPP14_NAND, /* NAND_REn[2] */
MPP15_NAND, /* NAND_WEn[2] */
MPP16_UART, /* UART1_RX */
MPP17_UART, /* UART1_TX */
MPP18_UART, /* UART1_CTSn */
MPP19_UART, /* UART1_RTSn */
0,
};
static void __init db88f5281_init(void)
......
arch/arm/mach-orion5x/dns323-setup.c
View file @ 1e87347c
......@@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = {
/****************************************************************************
* General Setup
*/
static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
{ 0, MPP_PCIE_RST_OUTn },
{ 1, MPP_GPIO }, /* right amber LED (sata ch0) */
{ 2, MPP_GPIO }, /* left amber LED (sata ch1) */
{ 3, MPP_UNUSED },
{ 4, MPP_GPIO }, /* power button LED */
{ 5, MPP_GPIO }, /* power button LED */
{ 6, MPP_GPIO }, /* GMT G751-2f overtemp */
{ 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */
{ 8, MPP_GPIO }, /* triggers power off */
{ 9, MPP_GPIO }, /* power button switch */
{ 10, MPP_GPIO }, /* reset button switch */
{ 11, MPP_UNUSED },
{ 12, MPP_UNUSED },
{ 13, MPP_UNUSED },
{ 14, MPP_UNUSED },
{ 15, MPP_UNUSED },
{ 16, MPP_UNUSED },
{ 17, MPP_UNUSED },
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int dns323a_mpp_modes[] __initdata = {
MPP0_PCIE_RST_OUTn,
MPP1_GPIO, /* right amber LED (sata ch0) */
MPP2_GPIO, /* left amber LED (sata ch1) */
MPP3_UNUSED,
MPP4_GPIO, /* power button LED */
MPP5_GPIO, /* power button LED */
MPP6_GPIO, /* GMT G751-2f overtemp */
MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
MPP8_GPIO, /* triggers power off */
MPP9_GPIO, /* power button switch */
MPP10_GPIO, /* reset button switch */
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_UNUSED,
MPP15_UNUSED,
MPP16_UNUSED,
MPP17_UNUSED,
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED },
{ 1, MPP_GPIO }, /* right amber LED (sata ch0) */
{ 2, MPP_GPIO }, /* left amber LED (sata ch1) */
{ 3, MPP_GPIO }, /* system up flag */
{ 4, MPP_GPIO }, /* power button LED */
{ 5, MPP_GPIO }, /* power button LED */
{ 6, MPP_GPIO }, /* GMT G751-2f overtemp */
{ 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */
{ 8, MPP_GPIO }, /* triggers power off */
{ 9, MPP_GPIO }, /* power button switch */
{ 10, MPP_GPIO }, /* reset button switch */
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED },
{ 13, MPP_SATA_LED },
{ 14, MPP_SATA_LED },
{ 15, MPP_SATA_LED },
{ 16, MPP_UNUSED },
{ 17, MPP_UNUSED },
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int dns323b_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_GPIO, /* right amber LED (sata ch0) */
MPP2_GPIO, /* left amber LED (sata ch1) */
MPP3_GPIO, /* system up flag */
MPP4_GPIO, /* power button LED */
MPP5_GPIO, /* power button LED */
MPP6_GPIO, /* GMT G751-2f overtemp */
MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
MPP8_GPIO, /* triggers power off */
MPP9_GPIO, /* power button switch */
MPP10_GPIO, /* reset button switch */
MPP11_UNUSED,
MPP12_SATA_LED,
MPP13_SATA_LED,
MPP14_SATA_LED,
MPP15_SATA_LED,
MPP16_UNUSED,
MPP17_UNUSED,
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* ? input */
{ 1, MPP_GPIO }, /* input power switch (0 = pressed) */
{ 2, MPP_GPIO }, /* output power off */
{ 3, MPP_UNUSED }, /* ? output */
{ 4, MPP_UNUSED }, /* ? output */
{ 5, MPP_UNUSED }, /* ? output */
{ 6, MPP_UNUSED }, /* ? output */
{ 7, MPP_UNUSED }, /* ? output */
{ 8, MPP_GPIO }, /* i/o right amber LED */
{ 9, MPP_GPIO }, /* i/o left amber LED */
{ 10, MPP_GPIO }, /* input */
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED },
{ 13, MPP_SATA_LED },
{ 14, MPP_SATA_LED },
{ 15, MPP_SATA_LED },
{ 16, MPP_UNUSED },
{ 17, MPP_GPIO }, /* power button LED */
{ 18, MPP_GPIO }, /* fan speed bit 0 */
{ 19, MPP_GPIO }, /* fan speed bit 1 */
{ -1 },
static unsigned int dns323c_mpp_modes[] __initdata = {
MPP0_GPIO, /* ? input */
MPP1_GPIO, /* input power switch (0 = pressed) */
MPP2_GPIO, /* output power off */
MPP3_UNUSED, /* ? output */
MPP4_UNUSED, /* ? output */
MPP5_UNUSED, /* ? output */
MPP6_UNUSED, /* ? output */
MPP7_UNUSED, /* ? output */
MPP8_GPIO, /* i/o right amber LED */
MPP9_GPIO, /* i/o left amber LED */
MPP10_GPIO, /* input */
MPP11_UNUSED,
MPP12_SATA_LED,
MPP13_SATA_LED,
MPP14_SATA_LED,
MPP15_SATA_LED,
MPP16_UNUSED,
MPP17_GPIO, /* power button LED */
MPP18_GPIO, /* fan speed bit 0 */
MPP19_GPIO, /* fan speed bit 1 */
0,
};
/* Rev C1 Fan speed notes:
......
arch/arm/mach-orion5x/edmini_v2-setup.c
View file @ 1e87347c
......@@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = {
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED },
{ 1, MPP_UNUSED },
{ 2, MPP_UNUSED },
{ 3, MPP_GPIO }, /* RTC interrupt */
{ 4, MPP_UNUSED },
{ 5, MPP_UNUSED },
{ 6, MPP_UNUSED },
{ 7, MPP_UNUSED },
{ 8, MPP_UNUSED },
{ 9, MPP_UNUSED },
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED }, /* SATA 0 presence */
{ 13, MPP_SATA_LED }, /* SATA 1 presence */
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
static unsigned int edminiv2_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_UNUSED,
MPP2_UNUSED,
MPP3_GPIO, /* RTC interrupt */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_UNUSED,
MPP7_UNUSED,
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
/* 16: Power LED control (0 = On, 1 = Off) */
{ 16, MPP_GPIO },
MPP16_GPIO,
/* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
{ 17, MPP_GPIO },
MPP17_GPIO,
/* 18: Power button status (0 = Released, 1 = Pressed) */
{ 18, MPP_GPIO },
{ 19, MPP_UNUSED },
{ -1 }
MPP18_GPIO,
MPP19_UNUSED,
0,
};
static void __init edmini_v2_init(void)
......
arch/arm/mach-orion5x/kurobox_pro-setup.c
View file @ 1e87347c
......@@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void)
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED },
{ 1, MPP_UNUSED },
{ 2, MPP_GPIO }, /* GPIO Micon */
{ 3, MPP_GPIO }, /* GPIO Rtc */
{ 4, MPP_UNUSED },
{ 5, MPP_UNUSED },
{ 6, MPP_NAND }, /* NAND Flash REn */
{ 7, MPP_NAND }, /* NAND Flash WEn */
{ 8, MPP_UNUSED },
{ 9, MPP_UNUSED },
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED }, /* SATA 0 presence */
{ 13, MPP_SATA_LED }, /* SATA 1 presence */
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
{ 16, MPP_UART }, /* UART1 RXD */
{ 17, MPP_UART }, /* UART1 TXD */
{ 18, MPP_UART }, /* UART1 CTSn */
{ 19, MPP_UART }, /* UART1 RTSn */
{ -1 },
static unsigned int kurobox_pro_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_UNUSED,
MPP2_GPIO, /* GPIO Micon */
MPP3_GPIO, /* GPIO Rtc */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_NAND, /* NAND Flash REn */
MPP7_NAND, /* NAND Flash WEn */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_UART, /* UART1 CTSn */
MPP19_UART, /* UART1 RTSn */
0,
};
static void __init kurobox_pro_init(void)
......
arch/arm/mach-orion5x/ls-chl-setup.c
View file @ 1e87347c
......@@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = {
* GPIO Data
****************************************************************************/
static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* LED POWER */
{ 1, MPP_GPIO }, /* HDD POWER */
{ 2, MPP_GPIO }, /* LED ALARM */
{ 3, MPP_GPIO }, /* LED INFO */
{ 4, MPP_UNUSED },
{ 5, MPP_UNUSED },
{ 6, MPP_GPIO }, /* FAN LOCK */
{ 7, MPP_GPIO }, /* SW INIT */
{ 8, MPP_GPIO }, /* SW POWER */
{ 9, MPP_GPIO }, /* USB POWER */
{ 10, MPP_GPIO }, /* SW AUTO POWER */
{ 11, MPP_UNUSED },
{ 12, MPP_UNUSED },
{ 13, MPP_UNUSED },
{ 14, MPP_GPIO }, /* FAN HIGH */
{ 15, MPP_GPIO }, /* SW FUNC */
{ 16, MPP_GPIO }, /* FAN LOW */
{ 17, MPP_GPIO }, /* LED FUNC */
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int lschl_mpp_modes[] __initdata = {
MPP0_GPIO, /* LED POWER */
MPP1_GPIO, /* HDD POWER */
MPP2_GPIO, /* LED ALARM */
MPP3_GPIO, /* LED INFO */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_GPIO, /* FAN LOCK */
MPP7_GPIO, /* SW INIT */
MPP8_GPIO, /* SW POWER */
MPP9_GPIO, /* USB POWER */
MPP10_GPIO, /* SW AUTO POWER */
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_GPIO, /* FAN HIGH */
MPP15_GPIO, /* SW FUNC */
MPP16_GPIO, /* FAN LOW */
MPP17_GPIO, /* LED FUNC */
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init lschl_init(void)
......
arch/arm/mach-orion5x/ls_hgl-setup.c
View file @ 1e87347c
......@@ -200,28 +200,28 @@ static void ls_hgl_power_off(void)
#define LS_HGL_GPIO_HDD_POWER 1
static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* LED_PWR */
{ 1, MPP_GPIO }, /* HDD_PWR */
{ 2, MPP_GPIO }, /* LED_ALARM */
{ 3, MPP_GPIO }, /* LED_INFO */
{ 4, MPP_UNUSED },
{ 5, MPP_UNUSED },
{ 6, MPP_GPIO }, /* FAN_LCK */
{ 7, MPP_GPIO }, /* INIT */
{ 8, MPP_GPIO }, /* POWER */
{ 9, MPP_GPIO }, /* USB_PWR */
{ 10, MPP_GPIO }, /* AUTO_POWER */
{ 11, MPP_UNUSED }, /* LED_ETH (dummy) */
{ 12, MPP_UNUSED },
{ 13, MPP_UNUSED },
{ 14, MPP_UNUSED },
{ 15, MPP_GPIO }, /* FUNC */
{ 16, MPP_UNUSED },
{ 17, MPP_GPIO }, /* LED_FUNC */
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int ls_hgl_mpp_modes[] __initdata = {
MPP0_GPIO, /* LED_PWR */
MPP1_GPIO, /* HDD_PWR */
MPP2_GPIO, /* LED_ALARM */
MPP3_GPIO, /* LED_INFO */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_GPIO, /* FAN_LCK */
MPP7_GPIO, /* INIT */
MPP8_GPIO, /* POWER */
MPP9_GPIO, /* USB_PWR */
MPP10_GPIO, /* AUTO_POWER */
MPP11_UNUSED, /* LED_ETH (dummy) */
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_UNUSED,
MPP15_GPIO, /* FUNC */
MPP16_UNUSED,
MPP17_GPIO, /* LED_FUNC */
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init ls_hgl_init(void)
......
arch/arm/mach-orion5x/lsmini-setup.c
View file @ 1e87347c
......@@ -201,28 +201,28 @@ static void lsmini_power_off(void)
#define LSMINI_GPIO_HDD_POWER0 1
#define LSMINI_GPIO_HDD_POWER1 19
static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */
{ 1, MPP_GPIO }, /* HDD_PWR */
{ 2, MPP_GPIO }, /* LED_ALARM */
{ 3, MPP_GPIO }, /* LED_INFO */
{ 4, MPP_UNUSED },
{ 5, MPP_UNUSED },
{ 6, MPP_UNUSED },
{ 7, MPP_UNUSED },
{ 8, MPP_UNUSED },
{ 9, MPP_GPIO }, /* LED_FUNC */
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED }, /* LED_ETH (dummy) */
{ 12, MPP_UNUSED },
{ 13, MPP_UNUSED },
{ 14, MPP_GPIO }, /* LED_PWR */
{ 15, MPP_GPIO }, /* FUNC */
{ 16, MPP_GPIO }, /* USB_PWR */
{ 17, MPP_GPIO }, /* AUTO_POWER */
{ 18, MPP_GPIO }, /* POWER */
{ 19, MPP_GPIO }, /* HDD_PWR1 */
{ -1 },
static unsigned int lsmini_mpp_modes[] __initdata = {
MPP0_UNUSED, /* LED_RESERVE1 (unused) */
MPP1_GPIO, /* HDD_PWR */
MPP2_GPIO, /* LED_ALARM */
MPP3_GPIO, /* LED_INFO */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_UNUSED,
MPP7_UNUSED,
MPP8_UNUSED,
MPP9_GPIO, /* LED_FUNC */
MPP10_UNUSED,
MPP11_UNUSED, /* LED_ETH (dummy) */
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_GPIO, /* LED_PWR */
MPP15_GPIO, /* FUNC */
MPP16_GPIO, /* USB_PWR */
MPP17_GPIO, /* AUTO_POWER */
MPP18_GPIO, /* POWER */
MPP19_GPIO, /* HDD_PWR1 */
0,
};
static void __init lsmini_init(void)
......
arch/arm/mach-orion5x/mpp.c
View file @ 1e87347c
......@@ -12,154 +12,34 @@
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
#include "common.h"
#include <plat/mpp.h>
#include "mpp.h"
#include "common.h"
static int is_5181l(void)
{
u32 dev;
u32 rev;
orion5x_pcie_id(&dev, &rev);
return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
}
static int is_5182(void)
static unsigned int __init orion5x_variant(void)
{
u32 dev;
u32 rev;
orion5x_pcie_id(&dev, &rev);
return !!(dev == MV88F5182_DEV_ID);
}
if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
return MPP_F5181_MASK;
static int is_5281(void)
{
u32 dev;
u32 rev;
if (dev == MV88F5182_DEV_ID)
return MPP_F5182_MASK;
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5281_DEV_ID)
return MPP_F5281_MASK;
return !!(dev == MV88F5281_DEV_ID);
printk(KERN_ERR "MPP setup: unknown orion5x variant "
"(dev %#x rev %#x)\n", dev, rev);
return 0;
}
static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
void __init orion5x_mpp_conf(unsigned int *mpp_list)
{
switch (type) {
case MPP_UNUSED:
case MPP_GPIO:
if (mpp == 0)
return 3;
if (mpp >= 1 && mpp <= 15)
return 0;
if (mpp >= 16 && mpp <= 19) {
if (is_5182())
return 5;
if (type == MPP_UNUSED)
return 0;
}
return -1;
case MPP_PCIE_RST_OUTn:
if (mpp == 0)
return 0;
return -1;
case MPP_PCI_ARB:
if (mpp >= 0 && mpp <= 7)
return 2;
return -1;
case MPP_PCI_PMEn:
if (mpp == 2)
return 3;
return -1;
case MPP_GIGE:
if (mpp >= 8 && mpp <= 19)
return 1;
return -1;
case MPP_NAND:
if (is_5182() || is_5281()) {
if (mpp >= 4 && mpp <= 7)
return 4;
if (mpp >= 12 && mpp <= 17)
return 4;
}
return -1;
case MPP_PCI_CLK:
if (is_5181l() && mpp >= 6 && mpp <= 7)
return 5;
return -1;
case MPP_SATA_LED:
if (is_5182()) {
if (mpp >= 4 && mpp <= 7)
return 5;
if (mpp >= 12 && mpp <= 15)
return 5;
}
return -1;
case MPP_UART:
if (mpp >= 16 && mpp <= 19)
return 0;
return -1;
}
printk(KERN_INFO "unknown MPP type %d\n", type);
return -1;
}
void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
{
u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
for ( ; mode->mpp >= 0; mode++) {
u32 *reg;
int num_type;
int shift;
if (mode->mpp >= 0 && mode->mpp <= 7)
reg = &mpp_0_7_ctrl;
else if (mode->mpp >= 8 && mode->mpp <= 15)
reg = &mpp_8_15_ctrl;
else if (mode->mpp >= 16 && mode->mpp <= 19)
reg = &mpp_16_19_ctrl;
else {
printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
"(%d)\n", mode->mpp);
continue;
}
num_type = determine_type_encoding(mode->mpp, mode->type);
if (num_type < 0) {
printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
"combination (%d, %d)\n", mode->mpp,
mode->type);
continue;
}
shift = (mode->mpp & 7) << 2;
*reg &= ~(0xf << shift);
*reg |= (num_type & 0xf) << shift;
if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
orion_gpio_set_unused(mode->mpp);
orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
}
writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
orion_mpp_conf(mpp_list, orion5x_variant(),
MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
}
arch/arm/mach-orion5x/mpp.h
View file @ 1e87347c
#ifndef __ARCH_ORION5X_MPP_H
#define __ARCH_ORION5X_MPP_H
enum orion5x_mpp_type {
/*
* This MPP is unused.
*/
MPP_UNUSED,
/*
* This MPP pin is used as a generic GPIO pin. Valid for
* MPPs 0-15 and device bus data pins 16-31. On 5182, also
* valid for MPPs 16-19.
*/
MPP_GPIO,
/*
* This MPP is used as PCIe_RST_OUTn pin. Valid for
* MPP 0 only.
*/
MPP_PCIE_RST_OUTn,
/*
* This MPP is used as PCI arbiter pin (REQn/GNTn).
* Valid for MPPs 0-7 only.
*/
MPP_PCI_ARB,
/*
* This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
*/
MPP_PCI_PMEn,
/*
* This MPP is used as GigE half-duplex (COL, CRS) or GMII
* (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
* MPPs 8-19 only.
*/
MPP_GIGE,
/*
* This MPP is used as NAND REn/WEn pin. Valid for MPPs
* 4-7 and 12-17 only, and only on the 5181l/5182/5281.
*/
MPP_NAND,
/*
* This MPP is used as a PCI clock output pin. Valid for
* MPPs 6-7 only, and only on the 5181l.
*/
MPP_PCI_CLK,
/*
* This MPP is used as a SATA presence/activity LED.
* Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
*/
MPP_SATA_LED,
/*
* This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
* Valid for MPPs 16-19 only.
*/
MPP_UART,
};
struct orion5x_mpp_mode {
int mpp;
enum orion5x_mpp_type type;
};
void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
/* MPP number */ ((_num) & 0xff) | \
/* MPP select value */ (((_sel) & 0xf) << 8) | \
/* may be input signal */ ((!!(_in)) << 12) | \
/* may be output signal */ ((!!(_out)) << 13) | \
/* available on F5181l */ ((!!(_F5181l)) << 14) | \
/* available on F5182 */ ((!!(_F5182)) << 15) | \
/* available on F5281 */ ((!!(_F5281)) << 16))
/* num sel i o 5181 5182 5281 */
#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1)
#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1)
#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1)
#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1)
#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1)
#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1)
#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1)
#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1)
#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0)
#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1)
#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1)
#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1)
#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0)
#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1)
#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1)
#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1)
#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0)
#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0)
#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1)
#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1)
#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1)
#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0)
#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0)
#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1)
#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1)
#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1)
#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1)
#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1)
#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1)
#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1)
#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1)
#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1)
#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0)
#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1)
#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1)
#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1)
#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0)
#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1)
#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1)
#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1)
#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0)
#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1)
#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1)
#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1)
#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0)
#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1)
#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0)
#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1)
#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1)
#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1)
#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0)
#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1)
#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1)
#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1)
#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1)
#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0)
#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1)
#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1)
#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1)
#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0)
#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1)
#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1)
#define MPP_MAX 19
void orion5x_mpp_conf(unsigned int *mpp_list);
#endif
arch/arm/mach-orion5x/mss2-setup.c
View file @ 1e87347c
......@@ -193,28 +193,28 @@ static void mss2_power_off(void)
/****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Power LED */
{ 1, MPP_GPIO }, /* Error LED */
{ 2, MPP_UNUSED },
{ 3, MPP_GPIO }, /* RTC interrupt */
{ 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/
{ 5, MPP_GPIO }, /* HD0 5V control */
{ 6, MPP_GPIO }, /* HD0 12V control */
{ 7, MPP_GPIO }, /* HD1 5V control */
{ 8, MPP_GPIO }, /* HD1 12V control */
{ 9, MPP_UNUSED },
{ 10, MPP_GPIO }, /* Fan control */
{ 11, MPP_GPIO }, /* Power button */
{ 12, MPP_GPIO }, /* Reset button */
{ 13, MPP_UNUSED },
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
{ 16, MPP_UNUSED },
{ 17, MPP_UNUSED },
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int mss2_mpp_modes[] __initdata = {
MPP0_GPIO, /* Power LED */
MPP1_GPIO, /* Error LED */
MPP2_UNUSED,
MPP3_GPIO, /* RTC interrupt */
MPP4_GPIO, /* HDD ind. (Single/Dual)*/
MPP5_GPIO, /* HD0 5V control */
MPP6_GPIO, /* HD0 12V control */
MPP7_GPIO, /* HD1 5V control */
MPP8_GPIO, /* HD1 12V control */
MPP9_UNUSED,
MPP10_GPIO, /* Fan control */
MPP11_GPIO, /* Power button */
MPP12_GPIO, /* Reset button */
MPP13_UNUSED,
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UNUSED,
MPP17_UNUSED,
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init mss2_init(void)
......
arch/arm/mach-orion5x/mv2120-setup.c
View file @ 1e87347c
......@@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = {
/****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Sys status LED */
{ 1, MPP_GPIO }, /* Sys error LED */
{ 2, MPP_GPIO }, /* OverTemp interrupt */
{ 3, MPP_GPIO }, /* RTC interrupt */
{ 4, MPP_GPIO }, /* V_LED 5V */
{ 5, MPP_GPIO }, /* V_LED 3.3V */
{ 6, MPP_UNUSED },
{ 7, MPP_UNUSED },
{ 8, MPP_GPIO }, /* SATA 0 fail LED */
{ 9, MPP_GPIO }, /* SATA 1 fail LED */
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED }, /* SATA 0 presence */
{ 13, MPP_SATA_LED }, /* SATA 1 presence */
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
{ 16, MPP_UNUSED },
{ 17, MPP_GPIO }, /* Reset button */
{ 18, MPP_GPIO }, /* Power button */
{ 19, MPP_GPIO }, /* Power off */
{ -1 },
static unsigned int mv2120_mpp_modes[] __initdata = {
MPP0_GPIO, /* Sys status LED */
MPP1_GPIO, /* Sys error LED */
MPP2_GPIO, /* OverTemp interrupt */
MPP3_GPIO, /* RTC interrupt */
MPP4_GPIO, /* V_LED 5V */
MPP5_GPIO, /* V_LED 3.3V */
MPP6_UNUSED,
MPP7_UNUSED,
MPP8_GPIO, /* SATA 0 fail LED */
MPP9_GPIO, /* SATA 1 fail LED */
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UNUSED,
MPP17_GPIO, /* Reset button */
MPP18_GPIO, /* Power button */
MPP19_GPIO, /* Power off */
0,
};
static struct i2c_board_info __initdata mv2120_i2c_rtc = {
......
arch/arm/mach-orion5x/net2big-setup.c
View file @ 1e87347c
......@@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = {
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Raid mode (bit 0) */
{ 1, MPP_GPIO }, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
{ 2, MPP_GPIO }, /* Raid mode (bit 1) */
{ 3, MPP_GPIO }, /* Board ID (bit 0) */
{ 4, MPP_GPIO }, /* Fan activity (0 = Off, 1 = On) */
{ 5, MPP_GPIO }, /* Fan fail detection */
{ 6, MPP_GPIO }, /* Red front LED (0 = Off, 1 = On) */
{ 7, MPP_GPIO }, /* Disable initial blinking on front LED */
{ 8, MPP_GPIO }, /* Rear power switch (on|auto) */
{ 9, MPP_GPIO }, /* Rear power switch (auto|off) */
{ 10, MPP_GPIO }, /* SATA 1 red LED (0 = Off, 1 = On) */
{ 11, MPP_GPIO }, /* SATA 0 red LED (0 = Off, 1 = On) */
{ 12, MPP_GPIO }, /* Board ID (bit 1) */
{ 13, MPP_GPIO }, /* SATA 1 blue LED blink control */
{ 14, MPP_SATA_LED },
{ 15, MPP_SATA_LED },
{ 16, MPP_GPIO }, /* Blue front LED control */
{ 17, MPP_GPIO }, /* SATA 0 blue LED blink control */
{ 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */
{ 19, MPP_GPIO }, /* SATA{0,1} power On/Off request */
{ -1 }
static unsigned int net2big_mpp_modes[] __initdata = {
MPP0_GPIO, /* Raid mode (bit 0) */
MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
MPP2_GPIO, /* Raid mode (bit 1) */
MPP3_GPIO, /* Board ID (bit 0) */
MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
MPP5_GPIO, /* Fan fail detection */
MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
MPP7_GPIO, /* Disable initial blinking on front LED */
MPP8_GPIO, /* Rear power switch (on|auto) */
MPP9_GPIO, /* Rear power switch (auto|off) */
MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
MPP12_GPIO, /* Board ID (bit 1) */
MPP13_GPIO, /* SATA 1 blue LED blink control */
MPP14_SATA_LED,
MPP15_SATA_LED,
MPP16_GPIO, /* Blue front LED control */
MPP17_GPIO, /* SATA 0 blue LED blink control */
MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
MPP19_GPIO, /* SATA{0,1} power On/Off request */
0,
/* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
/* 23: SATA 0 power status */
/* 24: Board power off */
......
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
View file @ 1e87347c
......@@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */
{ 1, MPP_GPIO }, /* PCI_intA */
{ 2, MPP_GPIO }, /* Hard Reset / Factory Init*/
{ 3, MPP_GPIO }, /* FXS or DAA select */
{ 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */
{ 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */
{ 6, MPP_PCI_CLK }, /* CPU PCI refclk */
{ 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
{ 8, MPP_GPIO }, /* CardBus reset */
{ 9, MPP_GPIO }, /* GE_RXERR */
{ 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */
{ 11, MPP_GPIO }, /* Lifeline control */
{ 12, MPP_GIGE }, /* GE_TXD[4] */
{ 13, MPP_GIGE }, /* GE_TXD[5] */
{ 14, MPP_GIGE }, /* GE_TXD[6] */
{ 15, MPP_GIGE }, /* GE_TXD[7] */
{ 16, MPP_GIGE }, /* GE_RXD[4] */
{ 17, MPP_GIGE }, /* GE_RXD[5] */
{ 18, MPP_GIGE }, /* GE_RXD[6] */
{ 19, MPP_GIGE }, /* GE_RXD[7] */
{ -1 },
static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
MPP0_GPIO, /* LED1 CardBus LED (front panel) */
MPP1_GPIO, /* PCI_intA */
MPP2_GPIO, /* Hard Reset / Factory Init*/
MPP3_GPIO, /* FXS or DAA select */
MPP4_GPIO, /* LED6 - phone LED (front panel) */
MPP5_GPIO, /* LED5 - phone LED (front panel) */
MPP6_PCI_CLK, /* CPU PCI refclk */
MPP7_PCI_CLK, /* PCI/PCIe refclk */
MPP8_GPIO, /* CardBus reset */
MPP9_GPIO, /* GE_RXERR */
MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */
MPP11_GPIO, /* Lifeline control */
MPP12_GIGE, /* GE_TXD[4] */
MPP13_GIGE, /* GE_TXD[5] */
MPP14_GIGE, /* GE_TXD[6] */
MPP15_GIGE, /* GE_TXD[7] */
MPP16_GIGE, /* GE_RXD[4] */
MPP17_GIGE, /* GE_RXD[5] */
MPP18_GIGE, /* GE_RXD[6] */
MPP19_GIGE, /* GE_RXD[7] */
0,
};
static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
......
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
View file @ 1e87347c
......@@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = {
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* LED1 */
{ 1, MPP_GPIO }, /* LED5 */
{ 2, MPP_GPIO }, /* LED4 */
{ 3, MPP_GPIO }, /* LED3 */
{ 4, MPP_GPIO }, /* PCI_intA */
{ 5, MPP_GPIO }, /* RTC interrupt */
{ 6, MPP_PCI_CLK }, /* CPU PCI refclk */
{ 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
{ 8, MPP_GPIO }, /* 88e6131 interrupt */
{ 9, MPP_GPIO }, /* GE_RXERR */
{ 10, MPP_GPIO }, /* PCI_intB */
{ 11, MPP_GPIO }, /* LED2 */
{ 12, MPP_GIGE }, /* GE_TXD[4] */
{ 13, MPP_GIGE }, /* GE_TXD[5] */
{ 14, MPP_GIGE }, /* GE_TXD[6] */
{ 15, MPP_GIGE }, /* GE_TXD[7] */
{ 16, MPP_GIGE }, /* GE_RXD[4] */
{ 17, MPP_GIGE }, /* GE_RXD[5] */
{ 18, MPP_GIGE }, /* GE_RXD[6] */
{ 19, MPP_GIGE }, /* GE_RXD[7] */
{ -1 },
static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
MPP0_GPIO, /* LED1 */
MPP1_GPIO, /* LED5 */
MPP2_GPIO, /* LED4 */
MPP3_GPIO, /* LED3 */
MPP4_GPIO, /* PCI_intA */
MPP5_GPIO, /* RTC interrupt */
MPP6_PCI_CLK, /* CPU PCI refclk */
MPP7_PCI_CLK, /* PCI/PCIe refclk */
MPP8_GPIO, /* 88e6131 interrupt */
MPP9_GPIO, /* GE_RXERR */
MPP10_GPIO, /* PCI_intB */
MPP11_GPIO, /* LED2 */
MPP12_GIGE, /* GE_TXD[4] */
MPP13_GIGE, /* GE_TXD[5] */
MPP14_GIGE, /* GE_TXD[6] */
MPP15_GIGE, /* GE_TXD[7] */
MPP16_GIGE, /* GE_RXD[4] */
MPP17_GIGE, /* GE_RXD[5] */
MPP18_GIGE, /* GE_RXD[6] */
MPP19_GIGE, /* GE_RXD[7] */
0,
};
static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
......
arch/arm/mach-orion5x/rd88f5182-setup.c
View file @ 1e87347c
......@@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = {
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Debug Led */
{ 1, MPP_GPIO }, /* Reset Switch */
{ 2, MPP_UNUSED },
{ 3, MPP_GPIO }, /* RTC Int */
{ 4, MPP_GPIO },
{ 5, MPP_GPIO },
{ 6, MPP_GPIO }, /* PCI_intA */
{ 7, MPP_GPIO }, /* PCI_intB */
{ 8, MPP_UNUSED },
{ 9, MPP_UNUSED },
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED }, /* SATA 0 presence */
{ 13, MPP_SATA_LED }, /* SATA 1 presence */
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
{ 16, MPP_UNUSED },
{ 17, MPP_UNUSED },
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int rd88f5182_mpp_modes[] __initdata = {
MPP0_GPIO, /* Debug Led */
MPP1_GPIO, /* Reset Switch */
MPP2_UNUSED,
MPP3_GPIO, /* RTC Int */
MPP4_GPIO,
MPP5_GPIO,
MPP6_GPIO, /* PCI_intA */
MPP7_GPIO, /* PCI_intB */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UNUSED,
MPP17_UNUSED,
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init rd88f5182_init(void)
......
arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
View file @ 1e87347c
......@@ -27,7 +27,6 @@
#include <asm/mach/pci.h>
#include <mach/orion5x.h>
#include "common.h"
#include "mpp.h"
static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
.phy_addr = -1,
......
arch/arm/mach-orion5x/terastation_pro2-setup.c
View file @ 1e87347c
......@@ -295,28 +295,28 @@ static void tsp2_power_off(void)
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = {
{ 0, MPP_PCIE_RST_OUTn },
{ 1, MPP_UNUSED },
{ 2, MPP_UNUSED },
{ 3, MPP_UNUSED },
{ 4, MPP_NAND }, /* BOOT NAND Flash REn */
{ 5, MPP_NAND }, /* BOOT NAND Flash WEn */
{ 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */
{ 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */
{ 8, MPP_GPIO }, /* MICON int */
{ 9, MPP_GPIO }, /* RTC int */
{ 10, MPP_UNUSED },
{ 11, MPP_GPIO }, /* PCI Int A */
{ 12, MPP_UNUSED },
{ 13, MPP_GPIO }, /* UPS on UART0 enable */
{ 14, MPP_GPIO }, /* UPS low battery detection */
{ 15, MPP_UNUSED },
{ 16, MPP_UART }, /* UART1 RXD */
{ 17, MPP_UART }, /* UART1 TXD */
{ 18, MPP_UART }, /* UART1 CTSn */
{ 19, MPP_UART }, /* UART1 RTSn */
{ -1 },
static unsigned int tsp2_mpp_modes[] __initdata = {
MPP0_PCIE_RST_OUTn,
MPP1_UNUSED,
MPP2_UNUSED,
MPP3_UNUSED,
MPP4_NAND, /* BOOT NAND Flash REn */
MPP5_NAND, /* BOOT NAND Flash WEn */
MPP6_NAND, /* BOOT NAND Flash HREn[0] */
MPP7_NAND, /* BOOT NAND Flash WEn[0] */
MPP8_GPIO, /* MICON int */
MPP9_GPIO, /* RTC int */
MPP10_UNUSED,
MPP11_GPIO, /* PCI Int A */
MPP12_UNUSED,
MPP13_GPIO, /* UPS on UART0 enable */
MPP14_GPIO, /* UPS low battery detection */
MPP15_UNUSED,
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_UART, /* UART1 CTSn */
MPP19_UART, /* UART1 RTSn */
0,
};
static void __init tsp2_init(void)
......
arch/arm/mach-orion5x/ts209-setup.c
View file @ 1e87347c
......@@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = {
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED },
{ 1, MPP_GPIO }, /* USB copy button */
{ 2, MPP_GPIO }, /* Load defaults button */
{ 3, MPP_GPIO }, /* GPIO RTC */
{ 4, MPP_UNUSED },
{ 5, MPP_UNUSED },
{ 6, MPP_GPIO }, /* PCI Int A */
{ 7, MPP_GPIO }, /* PCI Int B */
{ 8, MPP_UNUSED },
{ 9, MPP_UNUSED },
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_SATA_LED }, /* SATA 0 presence */
{ 13, MPP_SATA_LED }, /* SATA 1 presence */
{ 14, MPP_SATA_LED }, /* SATA 0 active */
{ 15, MPP_SATA_LED }, /* SATA 1 active */
{ 16, MPP_UART }, /* UART1 RXD */
{ 17, MPP_UART }, /* UART1 TXD */
{ 18, MPP_GPIO }, /* SW_RST */
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int ts209_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_GPIO, /* USB copy button */
MPP2_GPIO, /* Load defaults button */
MPP3_GPIO, /* GPIO RTC */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_GPIO, /* PCI Int A */
MPP7_GPIO, /* PCI Int B */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_GPIO, /* SW_RST */
MPP19_UNUSED,
0,
};
static void __init qnap_ts209_init(void)
......
arch/arm/mach-orion5x/ts409-setup.c
View file @ 1e87347c
......@@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = {
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED },
{ 1, MPP_UNUSED },
{ 2, MPP_UNUSED },
{ 3, MPP_UNUSED },
{ 4, MPP_GPIO }, /* HDD 1 status */
{ 5, MPP_GPIO }, /* HDD 2 status */
{ 6, MPP_GPIO }, /* HDD 3 status */
{ 7, MPP_GPIO }, /* HDD 4 status */
{ 8, MPP_UNUSED },
{ 9, MPP_UNUSED },
{ 10, MPP_GPIO }, /* RTC int */
{ 11, MPP_UNUSED },
{ 12, MPP_UNUSED },
{ 13, MPP_UNUSED },
{ 14, MPP_GPIO }, /* SW_RST */
{ 15, MPP_GPIO }, /* USB copy button */
{ 16, MPP_UART }, /* UART1 RXD */
{ 17, MPP_UART }, /* UART1 TXD */
{ 18, MPP_UNUSED },
{ 19, MPP_UNUSED },
{ -1 },
static unsigned int ts409_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_UNUSED,
MPP2_UNUSED,
MPP3_UNUSED,
MPP4_GPIO, /* HDD 1 status */
MPP5_GPIO, /* HDD 2 status */
MPP6_GPIO, /* HDD 3 status */
MPP7_GPIO, /* HDD 4 status */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_GPIO, /* RTC int */
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_GPIO, /* SW_RST */
MPP15_GPIO, /* USB copy button */
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init qnap_ts409_init(void)
......
arch/arm/mach-orion5x/ts78xx-setup.c
View file @ 1e87347c
......@@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr =
/*****************************************************************************
* General Setup
****************************************************************************/
static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
{ 0, MPP_UNUSED },
{ 1, MPP_GPIO }, /* JTAG Clock */
{ 2, MPP_GPIO }, /* JTAG Data In */
{ 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */
{ 4, MPP_GPIO }, /* JTAG Data Out */
{ 5, MPP_GPIO }, /* JTAG TMS */
{ 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
{ 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */
{ 8, MPP_UNUSED },
{ 9, MPP_UNUSED },
{ 10, MPP_UNUSED },
{ 11, MPP_UNUSED },
{ 12, MPP_UNUSED },
{ 13, MPP_UNUSED },
{ 14, MPP_UNUSED },
{ 15, MPP_UNUSED },
{ 16, MPP_UART },
{ 17, MPP_UART },
{ 18, MPP_UART },
{ 19, MPP_UART },
static unsigned int ts78xx_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_GPIO, /* JTAG Clock */
MPP2_GPIO, /* JTAG Data In */
MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
MPP4_GPIO, /* JTAG Data Out */
MPP5_GPIO, /* JTAG TMS */
MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_UNUSED,
MPP15_UNUSED,
MPP16_UART,
MPP17_UART,
MPP18_UART,
MPP19_UART,
/*
* MPP[20] PCI Clock Out 1
* MPP[21] PCI Clock Out 0
......@@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
* MPP[24] Unused
* MPP[25] Unused
*/
{ -1 },
0,
};
static void __init ts78xx_init(void)
......
arch/arm/mach-orion5x/wnr854t-setup.c
View file @ 1e87347c
......@@ -24,28 +24,28 @@
#include "common.h"
#include "mpp.h"
static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Power LED green (0=on) */
{ 1, MPP_GPIO }, /* Reset Button (0=off) */
{ 2, MPP_GPIO }, /* Power LED blink (0=off) */
{ 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */
{ 4, MPP_GPIO }, /* PCI int */
{ 5, MPP_GPIO }, /* ??? */
{ 6, MPP_GPIO }, /* ??? */
{ 7, MPP_GPIO }, /* ??? */
{ 8, MPP_UNUSED }, /* ??? */
{ 9, MPP_GIGE }, /* GE_RXERR */
{ 10, MPP_UNUSED }, /* ??? */
{ 11, MPP_UNUSED }, /* ??? */
{ 12, MPP_GIGE }, /* GE_TXD[4] */
{ 13, MPP_GIGE }, /* GE_TXD[5] */
{ 14, MPP_GIGE }, /* GE_TXD[6] */
{ 15, MPP_GIGE }, /* GE_TXD[7] */
{ 16, MPP_GIGE }, /* GE_RXD[4] */
{ 17, MPP_GIGE }, /* GE_RXD[5] */
{ 18, MPP_GIGE }, /* GE_RXD[6] */
{ 19, MPP_GIGE }, /* GE_RXD[7] */
{ -1 },
static unsigned int wnr854t_mpp_modes[] __initdata = {
MPP0_GPIO, /* Power LED green (0=on) */
MPP1_GPIO, /* Reset Button (0=off) */
MPP2_GPIO, /* Power LED blink (0=off) */
MPP3_GPIO, /* WAN Status LED amber (0=off) */
MPP4_GPIO, /* PCI int */
MPP5_GPIO, /* ??? */
MPP6_GPIO, /* ??? */
MPP7_GPIO, /* ??? */
MPP8_UNUSED, /* ??? */
MPP9_GIGE, /* GE_RXERR */
MPP10_UNUSED, /* ??? */
MPP11_UNUSED, /* ??? */
MPP12_GIGE, /* GE_TXD[4] */
MPP13_GIGE, /* GE_TXD[5] */
MPP14_GIGE, /* GE_TXD[6] */
MPP15_GIGE, /* GE_TXD[7] */
MPP16_GIGE, /* GE_RXD[4] */
MPP17_GIGE, /* GE_RXD[5] */
MPP18_GIGE, /* GE_RXD[6] */
MPP19_GIGE, /* GE_RXD[7] */
0,
};
/*
......
arch/arm/mach-orion5x/wrt350n-v2-setup.c
View file @ 1e87347c
......@@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = {
/*
* General setup
*/
static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
{ 0, MPP_GPIO }, /* Power LED green (0=on) */
{ 1, MPP_GPIO }, /* Security LED (0=on) */
{ 2, MPP_GPIO }, /* Internal Button (0=on) */
{ 3, MPP_GPIO }, /* Reset Button (0=on) */
{ 4, MPP_GPIO }, /* PCI int */
{ 5, MPP_GPIO }, /* Power LED orange (0=on) */
{ 6, MPP_GPIO }, /* USB LED (0=on) */
{ 7, MPP_GPIO }, /* Wireless LED (0=on) */
{ 8, MPP_UNUSED }, /* ??? */
{ 9, MPP_GIGE }, /* GE_RXERR */
{ 10, MPP_UNUSED }, /* ??? */
{ 11, MPP_UNUSED }, /* ??? */
{ 12, MPP_GIGE }, /* GE_TXD[4] */
{ 13, MPP_GIGE }, /* GE_TXD[5] */
{ 14, MPP_GIGE }, /* GE_TXD[6] */
{ 15, MPP_GIGE }, /* GE_TXD[7] */
{ 16, MPP_GIGE }, /* GE_RXD[4] */
{ 17, MPP_GIGE }, /* GE_RXD[5] */
{ 18, MPP_GIGE }, /* GE_RXD[6] */
{ 19, MPP_GIGE }, /* GE_RXD[7] */
{ -1 },
static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
MPP0_GPIO, /* Power LED green (0=on) */
MPP1_GPIO, /* Security LED (0=on) */
MPP2_GPIO, /* Internal Button (0=on) */
MPP3_GPIO, /* Reset Button (0=on) */
MPP4_GPIO, /* PCI int */
MPP5_GPIO, /* Power LED orange (0=on) */
MPP6_GPIO, /* USB LED (0=on) */
MPP7_GPIO, /* Wireless LED (0=on) */
MPP8_UNUSED, /* ??? */
MPP9_GIGE, /* GE_RXERR */
MPP10_UNUSED, /* ??? */
MPP11_UNUSED, /* ??? */
MPP12_GIGE, /* GE_TXD[4] */
MPP13_GIGE, /* GE_TXD[5] */
MPP14_GIGE, /* GE_TXD[6] */
MPP15_GIGE, /* GE_TXD[7] */
MPP16_GIGE, /* GE_RXD[4] */
MPP17_GIGE, /* GE_RXD[5] */
MPP18_GIGE, /* GE_RXD[6] */
MPP19_GIGE, /* GE_RXD[7] */
0,
};
/*
......
arch/arm/plat-orion/Makefile
View file @ 1e87347c
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := irq.o pcie.o time.o
obj-y := irq.o pcie.o time.o common.o mpp.o
obj-m :=
obj-n :=
obj- :=
......
arch/arm/plat-orion/common.c 0 → 100644
View file @ 1e87347c
/*
* arch/arm/plat-orion/common.c
*
* Marvell Orion SoC common setup code used by multiple mach-/common.c
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <net/dsa.h>
#include <linux/spi/orion_spi.h>
#include <plat/orion_wdt.h>
#include <plat/mv_xor.h>
#include <plat/ehci-orion.h>
/* Fill in the resources structure and link it into the platform
device structure. There is always a memory region, and nearly
always an interrupt.*/
static void fill_resources(struct platform_device *device,
struct resource *resources,
resource_size_t mapbase,
resource_size_t size,
unsigned int irq)
{
device->resource = resources;
device->num_resources = 1;
resources[0].flags = IORESOURCE_MEM;
resources[0].start = mapbase;
resources[0].end = mapbase + size;
if (irq != NO_IRQ) {
device->num_resources++;
resources[1].flags = IORESOURCE_IRQ;
resources[1].start = irq;
resources[1].end = irq;
}
}
/*****************************************************************************
* UART
****************************************************************************/
static void __init uart_complete(
struct platform_device *orion_uart,
struct plat_serial8250_port *data,
struct resource *resources,
unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk)
{
data->mapbase = mapbase;
data->membase = (void __iomem *)membase;
data->irq = irq;
data->uartclk = uartclk;
orion_uart->dev.platform_data = data;
fill_resources(orion_uart, resources, mapbase, 0xff, irq);
platform_device_register(orion_uart);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port orion_uart0_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart0_resources[2];
static struct platform_device orion_uart0 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
};
void __init orion_uart0_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk)
{
uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
membase, mapbase, irq, uartclk);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port orion_uart1_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart1_resources[2];
static struct platform_device orion_uart1 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
};
void __init orion_uart1_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk)
{
uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
membase, mapbase, irq, uartclk);
}
/*****************************************************************************
* UART2
****************************************************************************/
static struct plat_serial8250_port orion_uart2_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart2_resources[2];
static struct platform_device orion_uart2 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
};
void __init orion_uart2_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk)
{
uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
membase, mapbase, irq, uartclk);
}
/*****************************************************************************
* UART3
****************************************************************************/
static struct plat_serial8250_port orion_uart3_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart3_resources[2];
static struct platform_device orion_uart3 = {
.name = "serial8250",
.id = 3,
};
void __init orion_uart3_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk)
{
uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
membase, mapbase, irq, uartclk);
}
/*****************************************************************************
* SoC RTC
****************************************************************************/
static struct resource orion_rtc_resource[2];
void __init orion_rtc_init(unsigned long mapbase,
unsigned long irq)
{
orion_rtc_resource[0].start = mapbase;
orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
orion_rtc_resource[0].flags = IORESOURCE_MEM;
orion_rtc_resource[1].start = irq;
orion_rtc_resource[1].end = irq;
orion_rtc_resource[1].flags = IORESOURCE_IRQ;
platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
}
/*****************************************************************************
* GE
****************************************************************************/
static __init void ge_complete(
struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
struct mbus_dram_target_info *mbus_dram_info, int tclk,
struct resource *orion_ge_resource, unsigned long irq,
struct platform_device *orion_ge_shared,
struct mv643xx_eth_platform_data *eth_data,
struct platform_device *orion_ge)
{
orion_ge_shared_data->dram = mbus_dram_info;
orion_ge_shared_data->t_clk = tclk;
orion_ge_resource->start = irq;
orion_ge_resource->end = irq;
eth_data->shared = orion_ge_shared;
orion_ge->dev.platform_data = eth_data;
platform_device_register(orion_ge_shared);
platform_device_register(orion_ge);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
static struct resource orion_ge00_shared_resources[] = {
{
.name = "ge00 base",
}, {
.name = "ge00 err irq",
},
};
static struct platform_device orion_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &orion_ge00_shared_data,
},
};
static struct resource orion_ge00_resources[] = {
{
.name = "ge00 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = orion_ge00_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk)
{
fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
mapbase + 0x2000, SZ_16K - 1, irq_err);
ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
orion_ge00_resources, irq, &orion_ge00_shared,
eth_data, &orion_ge00);
}
/*****************************************************************************
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = {
.shared_smi = &orion_ge00_shared,
};
static struct resource orion_ge01_shared_resources[] = {
{
.name = "ge01 base",
}, {
.name = "ge01 err irq",
},
};
static struct platform_device orion_ge01_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &orion_ge01_shared_data,
},
};
static struct resource orion_ge01_resources[] = {
{
.name = "ge01 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge01 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = orion_ge01_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk)
{
fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
mapbase + 0x2000, SZ_16K - 1, irq_err);
ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
orion_ge01_resources, irq, &orion_ge01_shared,
eth_data, &orion_ge01);
}
/*****************************************************************************
* GE10
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = {
.shared_smi = &orion_ge00_shared,
};
static struct resource orion_ge10_shared_resources[] = {
{
.name = "ge10 base",
}, {
.name = "ge10 err irq",
},
};
static struct platform_device orion_ge10_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &orion_ge10_shared_data,
},
};
static struct resource orion_ge10_resources[] = {
{
.name = "ge10 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge10 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 2,
.resource = orion_ge10_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk)
{
fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
mapbase + 0x2000, SZ_16K - 1, irq_err);
ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
orion_ge10_resources, irq, &orion_ge10_shared,
eth_data, &orion_ge10);
}
/*****************************************************************************
* GE11
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = {
.shared_smi = &orion_ge00_shared,
};
static struct resource orion_ge11_shared_resources[] = {
{
.name = "ge11 base",
}, {
.name = "ge11 err irq",
},
};
static struct platform_device orion_ge11_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &orion_ge11_shared_data,
},
};
static struct resource orion_ge11_resources[] = {
{
.name = "ge11 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge11 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 2,
.resource = orion_ge11_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk)
{
fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
mapbase + 0x2000, SZ_16K - 1, irq_err);
ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
orion_ge11_resources, irq, &orion_ge11_shared,
eth_data, &orion_ge11);
}
/*****************************************************************************
* Ethernet switch
****************************************************************************/
static struct resource orion_switch_resources[] = {
{
.start = 0,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_switch_device = {
.name = "dsa",
.id = 0,
.num_resources = 0,
.resource = orion_switch_resources,
};
void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
{
int i;
if (irq != NO_IRQ) {
orion_switch_resources[0].start = irq;
orion_switch_resources[0].end = irq;
orion_switch_device.num_resources = 1;
}
d->netdev = &orion_ge00.dev;
for (i = 0; i < d->nr_chips; i++)
d->chip[i].mii_bus = &orion_ge00_shared.dev;
orion_switch_device.dev.platform_data = d;
platform_device_register(&orion_switch_device);
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion_i2c_resources[2];
static struct platform_device orion_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.dev = {
.platform_data = &orion_i2c_pdata,
},
};
static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion_i2c_1_resources[2];
static struct platform_device orion_i2c_1 = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 1,
.dev = {
.platform_data = &orion_i2c_1_pdata,
},
};
void __init orion_i2c_init(unsigned long mapbase,
unsigned long irq,
unsigned long freq_m)
{
orion_i2c_pdata.freq_m = freq_m;
fill_resources(&orion_i2c, orion_i2c_resources, mapbase,
SZ_32 - 1, irq);
platform_device_register(&orion_i2c);
}
void __init orion_i2c_1_init(unsigned long mapbase,
unsigned long irq,
unsigned long freq_m)
{
orion_i2c_1_pdata.freq_m = freq_m;
fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase,
SZ_32 - 1, irq);
platform_device_register(&orion_i2c_1);
}
/*****************************************************************************
* SPI
****************************************************************************/
static struct orion_spi_info orion_spi_plat_data;
static struct resource orion_spi_resources;
static struct platform_device orion_spi = {
.name = "orion_spi",
.id = 0,
.dev = {
.platform_data = &orion_spi_plat_data,
},
};
static struct orion_spi_info orion_spi_1_plat_data;
static struct resource orion_spi_1_resources;
static struct platform_device orion_spi_1 = {
.name = "orion_spi",
.id = 1,
.dev = {
.platform_data = &orion_spi_1_plat_data,
},
};
/* Note: The SPI silicon core does have interrupts. However the
* current Linux software driver does not use interrupts. */
void __init orion_spi_init(unsigned long mapbase,
unsigned long tclk)
{
orion_spi_plat_data.tclk = tclk;
fill_resources(&orion_spi, &orion_spi_resources,
mapbase, SZ_512 - 1, NO_IRQ);
platform_device_register(&orion_spi);
}
void __init orion_spi_1_init(unsigned long mapbase,
unsigned long tclk)
{
orion_spi_1_plat_data.tclk = tclk;
fill_resources(&orion_spi_1, &orion_spi_1_resources,
mapbase, SZ_512 - 1, NO_IRQ);
platform_device_register(&orion_spi_1);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct orion_wdt_platform_data orion_wdt_data;
static struct platform_device orion_wdt_device = {
.name = "orion_wdt",
.id = -1,
.dev = {
.platform_data = &orion_wdt_data,
},
.num_resources = 0,
};
void __init orion_wdt_init(unsigned long tclk)
{
orion_wdt_data.tclk = tclk;
platform_device_register(&orion_wdt_device);
}
/*****************************************************************************
* XOR
****************************************************************************/
static struct mv_xor_platform_shared_data orion_xor_shared_data;
static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
void __init orion_xor_init_channels(
struct mv_xor_platform_data *orion_xor0_data,
struct platform_device *orion_xor0_channel,
struct mv_xor_platform_data *orion_xor1_data,
struct platform_device *orion_xor1_channel)
{
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
platform_device_register(orion_xor0_channel);
dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
platform_device_register(orion_xor1_channel);
}
/*****************************************************************************
* XOR0
****************************************************************************/
static struct resource orion_xor0_shared_resources[] = {
{
.name = "xor 0 low",
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion_xor0_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &orion_xor_shared_data,
},
.num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
.resource = orion_xor0_shared_resources,
};
static struct resource orion_xor00_resources[] = {
[0] = {
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data orion_xor00_data = {
.shared = &orion_xor0_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device orion_xor00_channel = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(orion_xor00_resources),
.resource = orion_xor00_resources,
.dev = {
.dma_mask = &orion_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &orion_xor00_data,
},
};
static struct resource orion_xor01_resources[] = {
[0] = {
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data orion_xor01_data = {
.shared = &orion_xor0_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device orion_xor01_channel = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(orion_xor01_resources),
.resource = orion_xor01_resources,
.dev = {
.dma_mask = &orion_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &orion_xor01_data,
},
};
void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase_low,
unsigned long mapbase_high,
unsigned long irq_0,
unsigned long irq_1)
{
orion_xor_shared_data.dram = mbus_dram_info;
orion_xor0_shared_resources[0].start = mapbase_low;
orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
orion_xor0_shared_resources[1].start = mapbase_high;
orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
orion_xor00_resources[0].start = irq_0;
orion_xor00_resources[0].end = irq_0;
orion_xor01_resources[0].start = irq_1;
orion_xor01_resources[0].end = irq_1;
platform_device_register(&orion_xor0_shared);
orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
&orion_xor01_data, &orion_xor01_channel);
}
/*****************************************************************************
* XOR1
****************************************************************************/
static struct resource orion_xor1_shared_resources[] = {
{
.name = "xor 1 low",
.flags = IORESOURCE_MEM,
}, {
.name = "xor 1 high",
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion_xor1_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &orion_xor_shared_data,
},
.num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
.resource = orion_xor1_shared_resources,
};
static struct resource orion_xor10_resources[] = {
[0] = {
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data orion_xor10_data = {
.shared = &orion_xor1_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device orion_xor10_channel = {
.name = MV_XOR_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(orion_xor10_resources),
.resource = orion_xor10_resources,
.dev = {
.dma_mask = &orion_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &orion_xor10_data,
},
};
static struct resource orion_xor11_resources[] = {
[0] = {
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data orion_xor11_data = {
.shared = &orion_xor1_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device orion_xor11_channel = {
.name = MV_XOR_NAME,
.id = 3,
.num_resources = ARRAY_SIZE(orion_xor11_resources),
.resource = orion_xor11_resources,
.dev = {
.dma_mask = &orion_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &orion_xor11_data,
},
};
void __init orion_xor1_init(unsigned long mapbase_low,
unsigned long mapbase_high,
unsigned long irq_0,
unsigned long irq_1)
{
orion_xor1_shared_resources[0].start = mapbase_low;
orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
orion_xor1_shared_resources[1].start = mapbase_high;
orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
orion_xor10_resources[0].start = irq_0;
orion_xor10_resources[0].end = irq_0;
orion_xor11_resources[0].start = irq_1;
orion_xor11_resources[0].end = irq_1;
platform_device_register(&orion_xor1_shared);
orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
&orion_xor11_data, &orion_xor11_channel);
}
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data orion_ehci_data = {
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource orion_ehci_resources[2];
static struct platform_device orion_ehci = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_ehci_data,
},
};
void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq)
{
orion_ehci_data.dram = mbus_dram_info;
fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
irq);
platform_device_register(&orion_ehci);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource orion_ehci_1_resources[2];
static struct platform_device orion_ehci_1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_ehci_data,
},
};
void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq)
{
orion_ehci_data.dram = mbus_dram_info;
fill_resources(&orion_ehci_1, orion_ehci_1_resources,
mapbase, SZ_4K - 1, irq);
platform_device_register(&orion_ehci_1);
}
/*****************************************************************************
* EHCI2
****************************************************************************/
static struct resource orion_ehci_2_resources[2];
static struct platform_device orion_ehci_2 = {
.name = "orion-ehci",
.id = 2,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_ehci_data,
},
};
void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq)
{
orion_ehci_data.dram = mbus_dram_info;
fill_resources(&orion_ehci_2, orion_ehci_2_resources,
mapbase, SZ_4K - 1, irq);
platform_device_register(&orion_ehci_2);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource orion_sata_resources[2] = {
{
.name = "sata base",
}, {
.name = "sata irq",
},
};
static struct platform_device orion_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq)
{
sata_data->dram = mbus_dram_info;
orion_sata.dev.platform_data = sata_data;
fill_resources(&orion_sata, orion_sata_resources,
mapbase, 0x5000 - 1, irq);
platform_device_register(&orion_sata);
}
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
static struct resource orion_crypto_resources[] = {
{
.name = "regs",
}, {
.name = "crypto interrupt",
}, {
.name = "sram",
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion_crypto = {
.name = "mv_crypto",
.id = -1,
};
void __init orion_crypto_init(unsigned long mapbase,
unsigned long srambase,
unsigned long sram_size,
unsigned long irq)
{
fill_resources(&orion_crypto, orion_crypto_resources,
mapbase, 0xffff, irq);
orion_crypto.num_resources = 3;
orion_crypto_resources[2].start = srambase;
orion_crypto_resources[2].end = srambase + sram_size - 1;
platform_device_register(&orion_crypto);
}
arch/arm/plat-orion/gpio.c
View file @ 1e87347c
......@@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
* polarity LEVEL mask
*
****************************************************************************/
static void gpio_irq_ack(struct irq_data *d)
{
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
int type = irqd_get_trigger_type(d);
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
int pin = d->irq - ochip->secondary_irq_base;
writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
}
}
static void gpio_irq_mask(struct irq_data *d)
{
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
int type = irqd_get_trigger_type(d);
void __iomem *reg;
int pin;
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
reg = GPIO_EDGE_MASK(ochip);
else
reg = GPIO_LEVEL_MASK(ochip);
pin = d->irq - ochip->secondary_irq_base;
writel(readl(reg) & ~(1 << pin), reg);
}
static void gpio_irq_unmask(struct irq_data *d)
{
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
int type = irqd_get_trigger_type(d);
void __iomem *reg;
int pin;
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
reg = GPIO_EDGE_MASK(ochip);
else
reg = GPIO_LEVEL_MASK(ochip);
pin = d->irq - ochip->secondary_irq_base;
writel(readl(reg) | (1 << pin), reg);
}
static int gpio_irq_set_type(struct irq_data *d, u32 type)
{
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
struct orion_gpio_chip *ochip = gc->private;
int pin;
u32 u;
pin = d->irq - ochip->secondary_irq_base;
pin = d->irq - gc->irq_base;
u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
if (!u) {
......@@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
return -EINVAL;
}
/*
* Set edge/level type.
*/
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
__irq_set_handler_locked(d->irq, handle_edge_irq);
} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
__irq_set_handler_locked(d->irq, handle_level_irq);
} else {
printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
d->irq, type);
type &= IRQ_TYPE_SENSE_MASK;
if (type == IRQ_TYPE_NONE)
return -EINVAL;
}
/* Check if we need to change chip and handler */
if (!(ct->type & type))
if (irq_setup_alt_chip(d, type))
return -EINVAL;
/*
* Configure interrupt polarity.
......@@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
return 0;
}
struct irq_chip orion_gpio_irq_chip = {
.name = "orion_gpio_irq",
.irq_ack = gpio_irq_ack,
.irq_mask = gpio_irq_mask,
.irq_unmask = gpio_irq_unmask,
.irq_set_type = gpio_irq_set_type,
};
void __init orion_gpio_init(int gpio_base, int ngpio,
u32 base, int mask_offset, int secondary_irq_base)
{
struct orion_gpio_chip *ochip;
int i;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
return;
......@@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
writel(0, GPIO_EDGE_MASK(ochip));
writel(0, GPIO_LEVEL_MASK(ochip));
for (i = 0; i < ngpio; i++) {
unsigned int irq = secondary_irq_base + i;
irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
handle_level_irq);
irq_set_chip_data(irq, ochip);
irq_set_status_flags(irq, IRQ_LEVEL);
set_irq_flags(irq, IRQF_VALID);
}
gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
ochip->base, handle_level_irq);
gc->private = ochip;
ct = gc->chip_types;
ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_set_type = gpio_irq_set_type;
ct++;
ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
ct->chip.irq_ack = irq_gc_ack;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_set_type = gpio_irq_set_type;
ct->handler = handle_edge_irq;
irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
}
void orion_gpio_irq_handler(int pinoff)
......
arch/arm/plat-orion/include/plat/common.h 0 → 100644
View file @ 1e87347c
/*
* arch/arm/plat-orion/include/plat/common.h
*
* Marvell Orion SoC common setup code used by different mach-/common.c
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_COMMON_H
#include <linux/mv643xx_eth.h>
struct dsa_platform_data;
void __init orion_uart0_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk);
void __init orion_uart1_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk);
void __init orion_uart2_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk);
void __init orion_uart3_init(unsigned int membase,
resource_size_t mapbase,
unsigned int irq,
unsigned int uartclk);
void __init orion_rtc_init(unsigned long mapbase,
unsigned long irq);
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk);
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk);
void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk);
void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
int tclk);
void __init orion_ge00_switch_init(struct dsa_platform_data *d,
int irq);
void __init orion_i2c_init(unsigned long mapbase,
unsigned long irq,
unsigned long freq_m);
void __init orion_i2c_1_init(unsigned long mapbase,
unsigned long irq,
unsigned long freq_m);
void __init orion_spi_init(unsigned long mapbase,
unsigned long tclk);
void __init orion_spi_1_init(unsigned long mapbase,
unsigned long tclk);
void __init orion_wdt_init(unsigned long tclk);
void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase_low,
unsigned long mapbase_high,
unsigned long irq_0,
unsigned long irq_1);
void __init orion_xor1_init(unsigned long mapbase_low,
unsigned long mapbase_high,
unsigned long irq_0,
unsigned long irq_1);
void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq);
void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq);
void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq);
void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
struct mbus_dram_target_info *mbus_dram_info,
unsigned long mapbase,
unsigned long irq);
void __init orion_crypto_init(unsigned long mapbase,
unsigned long srambase,
unsigned long sram_size,
unsigned long irq);
#endif
arch/arm/plat-orion/include/plat/gpio.h
View file @ 1e87347c
......@@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
/*
* GPIO interrupt handling.
*/
extern struct irq_chip orion_gpio_irq_chip;
void orion_gpio_irq_handler(int irqoff);
......
arch/arm/plat-orion/include/plat/mpp.h 0 → 100644
View file @ 1e87347c
/*
* arch/arm/plat-orion/include/plat/mpp.h
*
* Marvell Orion SoC MPP handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_MPP_H
#define __PLAT_MPP_H
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
/* This is the generic MPP macro, without any variant information.
Each machine architecture is expected to extend this with further
bit fields indicating which MPP configurations are valid for a
specific variant. */
#define GENERIC_MPP(_num, _sel, _in, _out) ( \
/* MPP number */ ((_num) & 0xff) | \
/* MPP select value */ (((_sel) & 0xf) << 8) | \
/* may be input signal */ ((!!(_in)) << 12) | \
/* may be output signal */ ((!!(_out)) << 13))
#define MPP_INPUT_MASK GENERIC_MPP(0, 0x0, 1, 0)
#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1)
void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
unsigned int mpp_max, unsigned int dev_bus);
#endif
arch/arm/plat-orion/irq.c
View file @ 1e87347c
......@@ -14,52 +14,21 @@
#include <linux/io.h>
#include <plat/irq.h>
static void orion_irq_mask(struct irq_data *d)
{
void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
u32 mask;
mask = readl(maskaddr);
mask &= ~(1 << (d->irq & 31));
writel(mask, maskaddr);
}
static void orion_irq_unmask(struct irq_data *d)
{
void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
u32 mask;
mask = readl(maskaddr);
mask |= 1 << (d->irq & 31);
writel(mask, maskaddr);
}
static struct irq_chip orion_irq_chip = {
.name = "orion_irq",
.irq_mask = orion_irq_mask,
.irq_mask_ack = orion_irq_mask,
.irq_unmask = orion_irq_unmask,
};
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
{
unsigned int i;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
/*
* Mask all interrupts initially.
*/
writel(0, maskaddr);
/*
* Register IRQ sources.
*/
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
irq_set_chip_and_handler(irq, &orion_irq_chip,
handle_level_irq);
irq_set_chip_data(irq, maskaddr);
irq_set_status_flags(irq, IRQ_LEVEL);
set_irq_flags(irq, IRQF_VALID);
}
gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
handle_level_irq);
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
}
arch/arm/plat-orion/mpp.c 0 → 100644
View file @ 1e87347c
/*
* arch/arm/plat-orion/mpp.c
*
* MPP functions for Marvell orion SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <plat/mpp.h>
/* Address of the ith MPP control register */
static __init unsigned long mpp_ctrl_addr(unsigned int i,
unsigned long dev_bus)
{
return dev_bus + (i) * 4;
}
void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
unsigned int mpp_max, unsigned int dev_bus)
{
unsigned int mpp_nr_regs = (1 + mpp_max/8);
u32 mpp_ctrl[mpp_nr_regs];
int i;
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < mpp_nr_regs; i++) {
mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > mpp_max) {
printk(KERN_ERR "orion_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (variant_mask & !(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"orion_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = 0;
if (*mpp_list & MPP_INPUT_MASK)
gpio_mode |= GPIO_INPUT_OK;
if (*mpp_list & MPP_OUTPUT_MASK)
gpio_mode |= GPIO_OUTPUT_OK;
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
}
printk(KERN_DEBUG " final MPP regs:");
for (i = 0; i < mpp_nr_regs; i++) {
writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
}
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