Commit 2b51a9b9 authored by Naresh Gottumukkala's avatar Naresh Gottumukkala Committed by Roland Dreier

RDMA/ocrdma: FRMA code cleanup

1) Fixed setting FR_MR bit for FRWR stag allocation
2) Access rights are passsed during FRWR stage and not during STAT allocation stage
3) FRWR WQE structure cleanup
4) Add QP level signaled bit.
Signed-off-by: default avatarNaresh Gottumukkala <bgottumukkala@emulex.com>
Signed-off-by: default avatarRoland Dreier <roland@purestorage.com>
parent f11220ee
...@@ -289,6 +289,7 @@ struct ocrdma_qp { ...@@ -289,6 +289,7 @@ struct ocrdma_qp {
u32 qkey; u32 qkey;
bool dpp_enabled; bool dpp_enabled;
u8 *ird_q_va; u8 *ird_q_va;
bool signaled;
u16 db_cache; u16 db_cache;
}; };
......
...@@ -1500,6 +1500,7 @@ static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr, ...@@ -1500,6 +1500,7 @@ static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
return -ENOMEM; return -ENOMEM;
cmd->num_pbl_pdid = cmd->num_pbl_pdid =
pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT); pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
cmd->fr_mr = hwmr->fr_mr;
cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr << cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
OCRDMA_REG_NSMR_REMOTE_WR_SHIFT); OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
...@@ -2049,6 +2050,7 @@ static int ocrdma_set_av_params(struct ocrdma_qp *qp, ...@@ -2049,6 +2050,7 @@ static int ocrdma_set_av_params(struct ocrdma_qp *qp,
(ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT); (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
cmd->params.rnt_rc_sl_fl |= cmd->params.rnt_rc_sl_fl |=
(ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK); (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
cmd->params.hop_lmt_rq_psn |= cmd->params.hop_lmt_rq_psn |=
(ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT); (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID; cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
......
...@@ -143,8 +143,11 @@ enum { ...@@ -143,8 +143,11 @@ enum {
# 2: 16K Bytes # 2: 16K Bytes
# 3: 32K Bytes # 3: 32K Bytes
# 4: 64K Bytes # 4: 64K Bytes
# 5: 128K Bytes
# 6: 256K Bytes
# 7: 512K Bytes
*/ */
#define OCRDMA_MAX_Q_PAGE_SIZE_CNT (5) #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
#define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES) #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
#define MAX_OCRDMA_QP_PAGES (8) #define MAX_OCRDMA_QP_PAGES (8)
...@@ -1274,7 +1277,7 @@ struct ocrdma_reg_nsmr { ...@@ -1274,7 +1277,7 @@ struct ocrdma_reg_nsmr {
struct ocrdma_mqe_hdr hdr; struct ocrdma_mqe_hdr hdr;
struct ocrdma_mbx_hdr cmd; struct ocrdma_mbx_hdr cmd;
u32 lrkey_key_index; u32 fr_mr;
u32 num_pbl_pdid; u32 num_pbl_pdid;
u32 flags_hpage_pbe_sz; u32 flags_hpage_pbe_sz;
u32 totlen_low; u32 totlen_low;
...@@ -1611,12 +1614,6 @@ struct ocrdma_ewqe_ud_hdr { ...@@ -1611,12 +1614,6 @@ struct ocrdma_ewqe_ud_hdr {
u32 rsvd; u32 rsvd;
}; };
#define OCRDMA_MAX_FR_PBES 11
struct ocrdma_fr_pbe {
u32 pa_hi;
u32 pa_lo;
};
/* extended wqe followed by hdr_wqe for Fast Memory register */ /* extended wqe followed by hdr_wqe for Fast Memory register */
struct ocrdma_ewqe_fr { struct ocrdma_ewqe_fr {
u32 va_hi; u32 va_hi;
...@@ -1625,7 +1622,8 @@ struct ocrdma_ewqe_fr { ...@@ -1625,7 +1622,8 @@ struct ocrdma_ewqe_fr {
u32 fbo_lo; u32 fbo_lo;
u32 size_sge; u32 size_sge;
u32 num_sges; u32 num_sges;
struct ocrdma_fr_pbe pbe[0]; u32 rsvd;
u32 rsvd2;
}; };
struct ocrdma_eth_basic { struct ocrdma_eth_basic {
......
...@@ -82,7 +82,8 @@ int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr) ...@@ -82,7 +82,8 @@ int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr)
IB_DEVICE_RC_RNR_NAK_GEN | IB_DEVICE_RC_RNR_NAK_GEN |
IB_DEVICE_SHUTDOWN_PORT | IB_DEVICE_SHUTDOWN_PORT |
IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_SYS_IMAGE_GUID |
IB_DEVICE_LOCAL_DMA_LKEY; IB_DEVICE_LOCAL_DMA_LKEY |
IB_DEVICE_MEM_MGT_EXTENSIONS;
attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_srq_sge); attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_srq_sge);
attr->max_sge_rd = dev->attr.max_rdma_sge; attr->max_sge_rd = dev->attr.max_rdma_sge;
attr->max_cq = dev->attr.max_cq; attr->max_cq = dev->attr.max_cq;
...@@ -1015,6 +1016,7 @@ static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp, ...@@ -1015,6 +1016,7 @@ static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
qp->sq.max_sges = attrs->cap.max_send_sge; qp->sq.max_sges = attrs->cap.max_send_sge;
qp->rq.max_sges = attrs->cap.max_recv_sge; qp->rq.max_sges = attrs->cap.max_recv_sge;
qp->state = OCRDMA_QPS_RST; qp->state = OCRDMA_QPS_RST;
qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
} }
...@@ -1864,7 +1866,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, ...@@ -1864,7 +1866,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
} }
hdr = ocrdma_hwq_head(&qp->sq); hdr = ocrdma_hwq_head(&qp->sq);
hdr->cw = 0; hdr->cw = 0;
if (wr->send_flags & IB_SEND_SIGNALED) if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT); hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
if (wr->send_flags & IB_SEND_FENCE) if (wr->send_flags & IB_SEND_FENCE)
hdr->cw |= hdr->cw |=
...@@ -1918,7 +1920,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, ...@@ -1918,7 +1920,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
*bad_wr = wr; *bad_wr = wr;
break; break;
} }
if (wr->send_flags & IB_SEND_SIGNALED) if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1; qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
else else
qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0; qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
......
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