Commit 2b7eab5f authored by Jeff Garzik's avatar Jeff Garzik

[netdrvr tg3] disable 5701 h/w bug workaround during core clock reset

parent 07cc7911
...@@ -3073,6 +3073,7 @@ static int tg3_abort_hw(struct tg3 *tp) ...@@ -3073,6 +3073,7 @@ static int tg3_abort_hw(struct tg3 *tp)
static void tg3_chip_reset(struct tg3 *tp) static void tg3_chip_reset(struct tg3 *tp)
{ {
u32 val; u32 val;
u32 flags_save;
/* Force NVRAM to settle. /* Force NVRAM to settle.
* This deals with a chip bug which can result in EEPROM * This deals with a chip bug which can result in EEPROM
...@@ -3089,8 +3090,21 @@ static void tg3_chip_reset(struct tg3 *tp) ...@@ -3089,8 +3090,21 @@ static void tg3_chip_reset(struct tg3 *tp)
} }
} }
/*
* We must avoid the readl() that normally takes place.
* It locks machines, causes machine checks, and other
* fun things. So, temporarily disable the 5701
* hardware workaround, while we do the reset.
*/
flags_save = tp->tg3_flags;
tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
/* do the reset */
tw32(GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET); tw32(GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET);
/* restore 5701 hardware bug workaround flag */
tp->tg3_flags = flags_save;
/* Flush PCI posted writes. The normal MMIO registers /* Flush PCI posted writes. The normal MMIO registers
* are inaccessible at this time so this is the only * are inaccessible at this time so this is the only
* way to make this reliably. I tried to use indirect * way to make this reliably. I tried to use indirect
......
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