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Commit 30b84288 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
 "This adds support for the spear13xx platform, which has first been
  under review a long time ago and finally been completed after generic
  spear work has gone into the clock, dt and pinctrl branches.

  Also a number of updates for the samsung socs are part of this branch."

Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c9 ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.

So the conflict diff looks like hell, but it's actually a fairly simple
change.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
  ARM: exynos: fix building with CONFIG_OF disabled
  ARM: EXYNOS: Add AUXDATA for i2c controllers
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: EXYNOS: Add device tree support for interrupt combiner
  ARM: EXYNOS: Add irq_domain support for interrupt combiner
  ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
  ARM: EXYNOS: update irqs for EXYNOS5250 SoC
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
  ARM: EXYNOS: add GPC4 bank instance
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Add watchdog timer clock instance
  pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
  SPEAr: Update MAINTAINERS and Documentation
  SPEAr13xx: Add defconfig
  SPEAr13xx: Add compilation support
  SPEAr13xx: Add dts and dtsi files
  pinctrl: Add SPEAr13xx pinctrl drivers
  pinctrl: SPEAr: Create macro for declaring GPIO PINS
  SPEAr13xx: Add common clock framework support
  ...
parents 84a442b9 820f3dd7
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Documentation/arm/SPEAr/overview.txt
View file @ 30b84288
......@@ -8,9 +8,8 @@ Introduction
weblink : http://www.st.com/spear
The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
series is in progress.
supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,
SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.
Hierarchy in SPEAr is as follows:
......@@ -26,33 +25,36 @@ Introduction
- SPEAr600 (SOC)
- SPEAr600 Evaluation Board
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
- SPEAr1310 (SOC)
- SPEAr1310 Evaluation Board
- SPEAr1340 (SOC)
- SPEAr1340 Evaluation Board
Configuration
-------------
A generic configuration is provided for each machine, and can be used as the
default by
make spear600_defconfig
make spear300_defconfig
make spear310_defconfig
make spear320_defconfig
make spear13xx_defconfig
make spear3xx_defconfig
make spear6xx_defconfig
Layout
------
The common files for multiple machine families (SPEAr3XX, SPEAr6XX and
SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear
The common files for multiple machine families (SPEAr3xx, SPEAr6xx and
SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear
with headers in plat/.
Each machine series have a directory with name arch/arm/mach-spear followed by
series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
mach-spear* doesn't contains board specific files as they fully support
Flattened Device Tree.
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is
mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and
spear600.c. mach-spear* doesn't contains board specific files as they fully
support Flattened Device Tree.
Document Author
......
Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt 0 → 100644
View file @ 30b84288
* Samsung Exynos Interrupt Combiner Controller
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt request
for the group. The interrupt request from each group are connected to a parent
interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Upto eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt
is usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register
can accommodate upto 4 interrupt combiners (with each combiner supporting
upto 8 interrupt sources).
Required properties:
- compatible: should be "samsung,exynos4210-combiner".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <2>. The meaning of the cells are
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
- reg: Base address and size of interrupt combiner registers.
- interrupts: The list of interrupts generated by the combiners which are then
connected to a parent interrupt controller. The format of the interrupt
specifier depends in the interrupt parent controller.
Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
- interrupt-parent: pHandle of the parent interrupt controller, if not
inherited from the parent node.
Example:
The following is a an example from the Exynos4210 SoC dtsi file.
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
Documentation/devicetree/bindings/arm/spear.txt
View file @ 30b84288
......@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
---------------------------------------
Boards with the ST SPEAr600 SoC shall have the following properties:
Required root node property:
compatible = "st,spear600";
Boards with the ST SPEAr300 SoC shall have the following properties:
Required root node property:
compatible = "st,spear300";
Boards with the ST SPEAr310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear310";
Boards with the ST SPEAr320 SoC shall have the following properties:
Required root node property:
compatible = "st,spear320";
Boards with the ST SPEAr1310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear1310";
compatible = "st,spear320";
Boards with the ST SPEAr1340 SoC shall have the following properties:
Required root node property:
compatible = "st,spear1340";
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
View file @ 30b84288
......@@ -4,6 +4,8 @@ Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
: "st,spear1310-pinmux"
: "st,spear1340-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
- Its values for SPEAr300:
......@@ -89,6 +91,37 @@ For SPEAr320 machines:
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
For SPEAr1310 machines:
"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
For SPEAr1340 machines:
"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
"miphy_dbg_grp", "pcie_grp", "sata_grp"
Valid values for function names are:
For All SPEAr3xx machines:
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
......@@ -106,3 +139,17 @@ For SPEAr320 machines:
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
"mii0_1", "i2c1", "i2c2"
For SPEAr1310 machines:
"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
For SPEAr1340 machines:
"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
MAINTAINERS
View file @ 30b84288
......@@ -6350,14 +6350,25 @@ F: include/linux/compiler.h
SPEAR PLATFORM SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/
SPEAR13XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/mach-spear13xx/
SPEAR3XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
......@@ -6366,6 +6377,8 @@ F: arch/arm/mach-spear3xx/
SPEAR6XX MACHINE SUPPORT
M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
M: Viresh Kumar <viresh.kumar@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
......
arch/arm/Makefile
View file @ 30b84288
......@@ -186,6 +186,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_VT8500) := vt8500
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
......
arch/arm/boot/dts/exynos5250-smdk5250.dts
View file @ 30b84288
......@@ -23,4 +23,52 @@ memory {
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
};
i2c@12C60000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
reg = <0x50>;
};
};
i2c@12C70000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
eeprom@51 {
compatible = "samsung,s524ad0xd1";
reg = <0x51>;
};
};
i2c@12C80000 {
status = "disabled";
};
i2c@12C90000 {
status = "disabled";
};
i2c@12CA0000 {
status = "disabled";
};
i2c@12CB0000 {
status = "disabled";
};
i2c@12CC0000 {
status = "disabled";
};
i2c@12CD0000 {
status = "disabled";
};
};
arch/arm/boot/dts/exynos5250.dtsi
View file @ 30b84288
......@@ -23,11 +23,11 @@ / {
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
gic:interrupt-controller@10490000 {
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
watchdog {
......@@ -42,30 +42,6 @@ rtc {
interrupts = <0 43 0>, <0 44 0>;
};
sdhci@12200000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12200000 0x100>;
interrupts = <0 75 0>;
};
sdhci@12210000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12210000 0x100>;
interrupts = <0 76 0>;
};
sdhci@12220000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12220000 0x100>;
interrupts = <0 77 0>;
};
sdhci@12230000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12230000 0x100>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
......@@ -94,48 +70,64 @@ i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
};
amba {
......@@ -157,13 +149,13 @@ pdma1: pdma@121B0000 {
interrupts = <0 35 0>;
};
mdma0: pdma@10800000 {
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
};
mdma1: pdma@11C10000 {
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
......@@ -242,6 +234,12 @@ gpc3: gpio-controller@11400140 {
#gpio-cells = <4>;
};
gpc4: gpio-controller@114002E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114002E0 0x20>;
#gpio-cells = <4>;
};
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
......@@ -388,19 +386,19 @@ gpv1: gpio-controller@10D10020 {
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10040 0x20>;
reg = <0x10D10060 0x20>;
#gpio-cells = <4>;
};
gpv3: gpio-controller@10D10060 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10060 0x20>;
reg = <0x10D10080 0x20>;
#gpio-cells = <4>;
};
gpv4: gpio-controller@10D10080 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10080 0x20>;
reg = <0x10D100C0 0x20>;
#gpio-cells = <4>;
};
......
arch/arm/boot/dts/spear1310-evb.dts 0 → 100644
View file @ 30b84288
/*
* DTS file for SPEAr1310 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear1310.dtsi"
/ {
model = "ST SPEAr1310 Evaluation Board";
compatible = "st,spear1310-evb", "st,spear1310";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@e0700000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
i2c0-pmx {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2s1 {
st,pins = "i2s1_grp";
st,function = "i2s1";
};
gpio {
st,pins = "arm_gpio_grp";
st,function = "arm_gpio";
};
eth {
st,pins = "gmii_grp";
st,function = "gmii";
};
ssp0 {
st,pins = "ssp0_grp";
st,function = "ssp0";
};
kbd {
st,pins = "keyboard_6x6_grp";
st,function = "keyboard";
};
sdhci {
st,pins = "sdhci_grp";
st,function = "sdhci";
};
smi-pmx {
st,pins = "smi_2_chips_grp";
st,function = "smi";
};
uart0 {
st,pins = "uart0_grp";
st,function = "uart0";
};
rs485 {
st,pins = "rs485_0_1_tdm_0_1_grp";
st,function = "rs485_0_1_tdm_0_1";
};
i2c1_2 {
st,pins = "i2c_1_2_grp";
st,function = "i2c_1_2";
};
pci {
st,pins = "pcie0_grp","pcie1_grp",
"pcie2_grp";
st,function = "pci";
};
smii {
st,pins = "smii_0_1_2_grp";
st,function = "smii_0_1_2";
};
nand {
st,pins = "nand_8bit_grp",
"nand_16bit_grp";
st,function = "nand";
};
};
};
ahci@b1000000 {
status = "okay";
};
cf@b2800000 {
status = "okay";
};
dma@ea800000 {
status = "okay";
};
dma@eb000000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
};
gmac0: eth@e2000000 {
status = "okay";
};
sdhci@b3000000 {
status = "okay";
};
smi: flash@ea000000 {
status = "okay";
clock-rate=<50000000>;
flash@e6000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe6000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@e0100000 {
status = "okay";
};
ehci@e4800000 {
status = "okay";
};
ehci@e5800000 {
status = "okay";
};
ohci@e4000000 {
status = "okay";
};
ohci@e5000000 {
status = "okay";
};
apb {
adc@e0080000 {
status = "okay";
};
gpio0: gpio@e0600000 {
status = "okay";
};
gpio1: gpio@e0680000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
};
i2c1: i2c@5cd00000 {
status = "okay";
};
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@e0580000 {
status = "okay";
};
serial@e0000000 {
status = "okay";
};
wdt@ec800620 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear1310.dtsi 0 → 100644
View file @ 30b84288
/*
* DTS file for all SPEAr1310 SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1310";
ahb {
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
status = "disabled";
};
ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
status = "disabled";
};
ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
status = "disabled";
};
gmac1: eth@5c400000 {
compatible = "st,spear600-gmac";
reg = <0x5c400000 0x8000>;
interrupts = <0 95 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac2: eth@5c500000 {
compatible = "st,spear600-gmac";
reg = <0x5c500000 0x8000>;
interrupts = <0 96 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac3: eth@5c600000 {
compatible = "st,spear600-gmac";
reg = <0x5c600000 0x8000>;
interrupts = <0 97 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac4: eth@5c700000 {
compatible = "st,spear600-gmac";
reg = <0x5c700000 0x8000>;
interrupts = <0 98 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
apb {
i2c1: i2c@5cd00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5cd00000 0x1000>;
interrupts = <0 87 0x4>;
status = "disabled";
};
i2c2: i2c@5ce00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5ce00000 0x1000>;
interrupts = <0 88 0x4>;
status = "disabled";
};
i2c3: i2c@5cf00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5cf00000 0x1000>;
interrupts = <0 89 0x4>;
status = "disabled";
};
i2c4: i2c@5d000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d000000 0x1000>;
interrupts = <0 90 0x4>;
status = "disabled";
};
i2c5: i2c@5d100000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d100000 0x1000>;
interrupts = <0 91 0x4>;
status = "disabled";
};
i2c6: i2c@5d200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d200000 0x1000>;
interrupts = <0 92 0x4>;
status = "disabled";
};
i2c7: i2c@5d300000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d300000 0x1000>;
interrupts = <0 93 0x4>;
status = "disabled";
};
serial@5c800000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c800000 0x1000>;
interrupts = <0 82 0x4>;
status = "disabled";
};
serial@5c900000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c900000 0x1000>;
interrupts = <0 83 0x4>;
status = "disabled";
};
serial@5ca00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5ca00000 0x1000>;
interrupts = <0 84 0x4>;
status = "disabled";
};
serial@5cb00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5cb00000 0x1000>;
interrupts = <0 85 0x4>;
status = "disabled";
};
serial@5cc00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5cc00000 0x1000>;
interrupts = <0 86 0x4>;
status = "disabled";
};
thermal@e07008c4 {
st,thermal-flags = <0x7000>;
};
};
};
};
arch/arm/boot/dts/spear1340-evb.dts 0 → 100644
View file @ 30b84288
/*
* DTS file for SPEAr1340 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear1340.dtsi"
/ {
model = "ST SPEAr1340 Evaluation Board";
compatible = "st,spear1340-evb", "st,spear1340";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@e0700000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
pads_as_gpio {
st,pins = "pads_as_gpio_grp";
st,function = "pads_as_gpio";
};
fsmc {
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
kbd {
st,pins = "keyboard_row_col_grp",
"keyboard_col5_grp";
st,function = "keyboard";
};
uart0 {
st,pins = "uart0_grp", "uart0_enh_grp";
st,function = "uart0";
};
i2c0-pmx {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2c1-pmx {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
spdif-in {
st,pins = "spdif_in_grp";
st,function = "spdif_in";
};
spdif-out {
st,pins = "spdif_out_grp";
st,function = "spdif_out";
};
ssp0 {
st,pins = "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs3_grp";
st,function = "ssp0";
};
pwm {
st,pins = "pwm2_grp", "pwm3_grp";
st,function = "pwm";
};
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
};
i2s {
st,pins = "i2s_in_grp", "i2s_out_grp";
st,function = "i2s";
};
gmac {
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
};
cec0 {
st,pins = "cec0_grp";
st,function = "cec0";
};
cec1 {
st,pins = "cec1_grp";
st,function = "cec1";
};
sdhci {
st,pins = "sdhci_grp";
st,function = "sdhci";
};
clcd {
st,pins = "clcd_grp";
st,function = "clcd";
};
sata {
st,pins = "sata_grp";
st,function = "sata";
};
};
};
dma@ea800000 {
status = "okay";
};
dma@eb000000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
};
gmac0: eth@e2000000 {
status = "okay";
};
sdhci@b3000000 {
status = "okay";
};
smi: flash@ea000000 {
status = "okay";
clock-rate=<50000000>;
flash@e6000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe6000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@e0100000 {
status = "okay";
};
ehci@e4800000 {
status = "okay";
};
ehci@e5800000 {
status = "okay";
};
ohci@e4000000 {
status = "okay";
};
ohci@e5000000 {
status = "okay";
};
apb {
adc@e0080000 {
status = "okay";
};
gpio0: gpio@e0600000 {
status = "okay";
};
gpio1: gpio@e0680000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
};
i2c1: i2c@b4000000 {
status = "okay";
};
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@e0580000 {
status = "okay";
};
serial@e0000000 {
status = "okay";
};
serial@b4100000 {
status = "okay";
};
wdt@ec800620 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear1340.dtsi 0 → 100644
View file @ 30b84288
/*
* DTS file for all SPEAr1340 SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1340";
ahb {
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
status = "disabled";
};
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
apb {
i2c1: i2c@b4000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xb4000000 0x1000>;
interrupts = <0 104 0x4>;
status = "disabled";
};
serial@b4100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb4100000 0x1000>;
interrupts = <0 105 0x4>;
status = "disabled";
};
thermal@e07008c4 {
st,thermal-flags = <0x2a00>;
};
};
};
};
arch/arm/boot/dts/spear13xx.dtsi 0 → 100644
View file @ 30b84288
/*
* DTS file for all SPEAr13xx SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
};
gic: interrupt-controller@ec801000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = < 0xec801000 0x1000 >,
< 0xec800100 0x0100 >;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 8 0x04
0 9 0x04>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xed000000 0x1000>;
cache-unified;
cache-level = <2>;
};
memory {
name = "memory";
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "console=ttyAMA0,115200";
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xe0000000 0xe0000000 0x10000000>;
sdhci@b3000000 {
compatible = "st,sdhci-spear";
reg = <0xb3000000 0x100>;
interrupts = <0 28 0x4>;
status = "disabled";
};
cf@b2800000 {
compatible = "arasan,cf-spear1340";
reg = <0xb2800000 0x100>;
interrupts = <0 29 0x4>;
status = "disabled";
};
dma@ea800000 {
compatible = "snps,dma-spear1340";
reg = <0xea800000 0x1000>;
interrupts = <0 19 0x4>;
status = "disabled";
};
dma@eb000000 {
compatible = "snps,dma-spear1340";
reg = <0xeb000000 0x1000>;
interrupts = <0 59 0x4>;
status = "disabled";
};
fsmc: flash@b0000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000000 0x1000 /* FSMC Register */
0xb0800000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
interrupts = <0 20 0x4
0 21 0x4
0 22 0x4
0 23 0x4>;
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
gmac0: eth@e2000000 {
compatible = "st,spear600-gmac";
reg = <0xe2000000 0x8000>;
interrupts = <0 23 0x4
0 24 0x4>;
interrupt-names = "macirq", "eth_wake_irq";
status = "disabled";
};
smi: flash@ea000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xea000000 0x1000>;
interrupts = <0 30 0x4>;
status = "disabled";
};
spi0: spi@e0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xe0100000 0x1000>;
interrupts = <0 31 0x4>;
status = "disabled";
};
ehci@e4800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe4800000 0x1000>;
interrupts = <0 64 0x4>;
status = "disabled";
};
ehci@e5800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe5800000 0x1000>;
interrupts = <0 66 0x4>;
status = "disabled";
};
ohci@e4000000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe4000000 0x1000>;
interrupts = <0 65 0x4>;
status = "disabled";
};
ohci@e5000000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe5000000 0x1000>;
interrupts = <0 67 0x4>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xe0000000 0xe0000000 0x10000000>;
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
interrupts = <0 24 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio1: gpio@e0680000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0680000 0x1000>;
interrupts = <0 25 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
kbd@e0300000 {
compatible = "st,spear300-kbd";
reg = <0xe0300000 0x1000>;
status = "disabled";
};
i2c0: i2c@e0280000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xe0280000 0x1000>;
interrupts = <0 41 0x4>;
status = "disabled";
};
rtc@e0580000 {
compatible = "st,spear-rtc";
reg = <0xe0580000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
};
serial@e0000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
};
adc@e0080000 {
compatible = "st,spear600-adc";
reg = <0xe0080000 0x1000>;
interrupts = <0 44 0x4>;
status = "disabled";
};
timer@e0380000 {
compatible = "st,spear-timer";
reg = <0xe0380000 0x400>;
interrupts = <0 37 0x4>;
};
timer@ec800600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xec800600 0x20>;
interrupts = <1 13 0x301>;
};
wdt@ec800620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0xec800620 0x20>;
status = "disabled";
};
thermal@e07008c4 {
compatible = "st,thermal-spear1340";
reg = <0xe07008c4 0x4>;
};
};
};
};
arch/arm/configs/spear13xx_defconfig 0 → 100644
View file @ 30b84288
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_PATA_ARASAN_CF=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_SPEAR=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
CONFIG_I2C=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_MPCORE_WATCHDOG=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_DMATEST=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_INFO=y
arch/arm/mach-exynos/Kconfig
View file @ 30b84288
......@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
select SAMSUNG_DMADEV
help
Enable EXYNOS5250 SoC support
......@@ -70,7 +71,7 @@ config EXYNOS4_MCT
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS4_DEV_DMA
config EXYNOS_DEV_DMA
bool
help
Compile in amba device definitions for DMA controller
......@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
config EXYNOS_DEV_DRM
bool
help
Compile in platform device definitions for core DRM device
config EXYNOS4_SETUP_FIMD0
bool
help
......@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
help
Common setup code for USB PHY controller
config EXYNOS4_SETUP_SPI
config EXYNOS_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations.
......@@ -224,7 +230,7 @@ config MACH_ARMLEX4210
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_AHCI
select EXYNOS4_DEV_DMA
select EXYNOS_DEV_DMA
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
......@@ -362,7 +368,7 @@ config MACH_SMDK4212
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
select EXYNOS_DEV_SYSMMU
select EXYNOS4_DEV_DMA
select EXYNOS_DEV_DMA
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C7
......
arch/arm/mach-exynos/Makefile
View file @ 30b84288
......@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
obj-y += dev-uart.o
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
......@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o
obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
arch/arm/mach-exynos/Makefile.boot
View file @ 30b84288
zreladdr-y += 0x40008000
params_phys-y := 0x40000100
dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
arch/arm/mach-exynos/clock-exynos4212.c
View file @ 30b84288
......@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 3),
}
};
......
arch/arm/mach-exynos/clock-exynos5.c
View file @ 30b84288
......@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
};
static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
.clk = {
.name = "mout_bpll_fout",
},
.sources = &clk_src_bpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
};
static struct clk *exynos5_clk_src_bpll_list[] = {
[0] = &clk_fin_bpll,
[1] = &exynos5_clk_mout_bpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_bpll = {
.sources = exynos5_clk_src_bpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
};
static struct clksrc_clk exynos5_clk_mout_bpll = {
.clk = {
.name = "mout_bpll",
},
.sources = &clk_src_bpll,
.sources = &exynos5_clk_src_bpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
};
......@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
};
static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
.clk = {
.name = "mout_mpll_fout",
},
.sources = &clk_src_mpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
};
static struct clk *exynos5_clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos5_clk_mout_mpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_mpll = {
.sources = exynos5_clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
};
struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &clk_src_mpll,
.sources = &exynos5_clk_src_mpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
};
......@@ -473,6 +509,11 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "watchdog",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.0",
......@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
&exynos5_clk_sclk_apll,
&exynos5_clk_mout_bpll,
&exynos5_clk_mout_bpll_fout,
&exynos5_clk_mout_bpll_user,
&exynos5_clk_mout_cpll,
&exynos5_clk_mout_epll,
&exynos5_clk_mout_mpll,
&exynos5_clk_mout_mpll_fout,
&exynos5_clk_mout_mpll_user,
&exynos5_clk_vpllsrc,
&exynos5_clk_sclk_vpll,
......@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
&exynos5_clk_sclk_hdmi27m,
&exynos5_clk_sclk_hdmiphy,
&clk_fout_bpll,
&clk_fout_bpll_div2,
&clk_fout_cpll,
&clk_fout_mpll_div2,
&exynos5_clk_armclk,
};
......@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_fout_apll.ops = &exynos5_fout_apll_ops;
clk_fout_bpll.rate = bpll;
clk_fout_bpll_div2.rate = bpll >> 1;
clk_fout_cpll.rate = cpll;
clk_fout_mpll.rate = mpll;
clk_fout_mpll_div2.rate = mpll >> 1;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;
......
arch/arm/mach-exynos/common.c
View file @ 30b84288
......@@ -19,6 +19,9 @@
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
......@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
.length = SZ_64K,
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
.length = SZ_64K,
.length = SZ_4K,
.type = MT_DEVICE,
},
};
......@@ -399,6 +402,7 @@ struct combiner_chip_data {
void __iomem *base;
};
static struct irq_domain *combiner_irq_domain;
static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
static inline void __iomem *combiner_base(struct irq_data *data)
......@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->irq % 32);
u32 mask = 1 << (data->hwirq % 32);
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
......@@ -474,49 +478,131 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
static void __init combiner_init_one(unsigned int combiner_nr,
void __iomem *base)
{
unsigned int i;
unsigned int max_nr;
if (soc_is_exynos5250())
max_nr = EXYNOS5_MAX_COMBINER_NR;
else
max_nr = EXYNOS4_MAX_COMBINER_NR;
if (combiner_nr >= max_nr)
BUG();
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_start;
combiner_data[combiner_nr].irq_offset = irq_find_mapping(
combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
}
#ifdef CONFIG_OF
static int combiner_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
if (d->of_node != controller)
return -EINVAL;
if (intsize < 2)
return -EINVAL;
*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
*out_type = 0;
return 0;
}
#else
static int combiner_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
return -EINVAL;
}
#endif
static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
irq_set_chip_data(irq, &combiner_data[hw >> 3]);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
/* Setup the Linux IRQ subsystem */
return 0;
}
static struct irq_domain_ops combiner_irq_domain_ops = {
.xlate = combiner_irq_domain_xlate,
.map = combiner_irq_domain_map,
};
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
{
int i, irq, irq_base;
unsigned int max_nr, nr_irq;
if (np) {
if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
pr_warning("%s: number of combiners not specified, "
"setting default as %d.\n",
__func__, EXYNOS4_MAX_COMBINER_NR);
max_nr = EXYNOS4_MAX_COMBINER_NR;
}
} else {
max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
EXYNOS4_MAX_COMBINER_NR;
}
nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
if (IS_ERR_VALUE(irq_base)) {
irq_base = COMBINER_IRQ(0, 0);
pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
}
combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
&combiner_irq_domain_ops, &combiner_data);
if (WARN_ON(!combiner_irq_domain)) {
pr_warning("%s: irq domain init failed\n", __func__);
return;
}
for (i = 0; i < max_nr; i++) {
combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
irq = IRQ_SPI(i);
#ifdef CONFIG_OF
if (np)
irq = irq_of_parse_and_map(np, i);
#endif
combiner_cascade_irq(i, irq);
}
}
#ifdef CONFIG_OF
int __init combiner_of_init(struct device_node *np, struct device_node *parent)
{
void __iomem *combiner_base;
combiner_base = of_iomap(np, 0);
if (!combiner_base) {
pr_err("%s: failed to map combiner registers\n", __func__);
return -ENXIO;
}
combiner_init(combiner_base, np);
return 0;
}
static const struct of_device_id exynos4_dt_irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{ .compatible = "samsung,exynos4210-combiner",
.data = combiner_of_init, },
{},
};
#endif
void __init exynos4_init_irq(void)
{
int irq;
unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
......@@ -528,12 +614,8 @@ void __init exynos4_init_irq(void)
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
if (!of_have_populated_dt())
combiner_init(S5P_VA_COMBINER_BASE, NULL);
/*
* The parameters of s5p_init_irq() are for VIC init.
......@@ -545,18 +627,9 @@ void __init exynos4_init_irq(void)
void __init exynos5_init_irq(void)
{
int irq;
#ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/*
* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
......@@ -565,30 +638,18 @@ void __init exynos5_init_irq(void)
s5p_init_irq(NULL, 0);
}
struct bus_type exynos4_subsys = {
.name = "exynos4-core",
.dev_name = "exynos4-core",
};
struct bus_type exynos5_subsys = {
.name = "exynos5-core",
.dev_name = "exynos5-core",
struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
static struct device exynos4_dev = {
.bus = &exynos4_subsys,
};
static struct device exynos5_dev = {
.bus = &exynos5_subsys,
.bus = &exynos_subsys,
};
static int __init exynos_core_init(void)
{
if (soc_is_exynos5250())
return subsys_system_register(&exynos5_subsys, NULL);
else
return subsys_system_register(&exynos4_subsys, NULL);
return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);
......@@ -675,10 +736,7 @@ static int __init exynos_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
if (soc_is_exynos5250())
return device_register(&exynos5_dev);
else
return device_register(&exynos4_dev);
return device_register(&exynos4_dev);
}
/* uart registration process */
......
arch/arm/mach-exynos/dev-drm.c 0 → 100644
View file @ 30b84288
/*
* linux/arch/arm/mach-exynos/dev-drm.c
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - core DRM device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <plat/devs.h>
static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
struct platform_device exynos_device_drm = {
.name = "exynos-drm",
.dev = {
.dma_mask = &exynos_drm_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
arch/arm/mach-exynos/dma.c
View file @ 30b84288
......@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
DMACH_MIPI_HSI5,
};
struct dma_pl330_platdata exynos4_pdma0_pdata;
static u8 exynos5250_pdma0_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM2_RX,
DMACH_PCM2_TX,
DMACH_SPI0_RX,
DMACH_SPI0_TX,
DMACH_SPI2_RX,
DMACH_SPI2_TX,
DMACH_I2S0S_TX,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
DMACH_I2S2_RX,
DMACH_I2S2_TX,
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART2_RX,
DMACH_UART2_TX,
DMACH_UART4_RX,
DMACH_UART4_TX,
DMACH_SLIMBUS0_RX,
DMACH_SLIMBUS0_TX,
DMACH_SLIMBUS2_RX,
DMACH_SLIMBUS2_TX,
DMACH_SLIMBUS4_RX,
DMACH_SLIMBUS4_TX,
DMACH_AC97_MICIN,
DMACH_AC97_PCMIN,
DMACH_AC97_PCMOUT,
DMACH_MIPI_HSI0,
DMACH_MIPI_HSI2,
DMACH_MIPI_HSI4,
DMACH_MIPI_HSI6,
};
static struct dma_pl330_platdata exynos_pdma0_pdata;
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
static u8 exynos4210_pdma1_peri[] = {
DMACH_PCM0_RX,
......@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
DMACH_MIPI_HSI7,
};
static struct dma_pl330_platdata exynos4_pdma1_pdata;
static u8 exynos5250_pdma1_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM1_RX,
DMACH_PCM1_TX,
DMACH_SPI1_RX,
DMACH_SPI1_TX,
DMACH_PWM,
DMACH_SPDIF,
DMACH_I2S0S_TX,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
DMACH_I2S1_RX,
DMACH_I2S1_TX,
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
DMACH_UART1_TX,
DMACH_UART3_RX,
DMACH_UART3_TX,
DMACH_SLIMBUS1_RX,
DMACH_SLIMBUS1_TX,
DMACH_SLIMBUS3_RX,
DMACH_SLIMBUS3_TX,
DMACH_SLIMBUS5_RX,
DMACH_SLIMBUS5_TX,
DMACH_SLIMBUS0AUX_RX,
DMACH_SLIMBUS0AUX_TX,
DMACH_DISP1,
DMACH_MIPI_HSI1,
DMACH_MIPI_HSI3,
DMACH_MIPI_HSI5,
DMACH_MIPI_HSI7,
};
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
static struct dma_pl330_platdata exynos_pdma1_pdata;
static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
static u8 mdma_peri[] = {
DMACH_MTOM_0,
......@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
DMACH_MTOM_7,
};
static struct dma_pl330_platdata exynos4_mdma1_pdata = {
static struct dma_pl330_platdata exynos_mdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
.peri_id = mdma_peri,
};
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
static int __init exynos4_dma_init(void)
static int __init exynos_dma_init(void)
{
if (of_have_populated_dt())
return 0;
if (soc_is_exynos4210()) {
exynos4_pdma0_pdata.nr_valid_peri =
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma0_peri);
exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
exynos4_pdma1_pdata.nr_valid_peri =
exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma1_peri);
exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos4_pdma0_pdata.nr_valid_peri =
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma0_peri);
exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
exynos4_pdma1_pdata.nr_valid_peri =
exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma1_peri);
exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
} else if (soc_is_exynos5250()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
}
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
amba_device_register(&exynos4_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
amba_device_register(&exynos_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
amba_device_register(&exynos4_pdma1_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
amba_device_register(&exynos_pdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
amba_device_register(&exynos4_mdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
amba_device_register(&exynos_mdma1_device, &iomem_resource);
return 0;
}
arch_initcall(exynos4_dma_init);
arch_initcall(exynos_dma_init);
arch/arm/mach-exynos/include/mach/gpio.h
View file @ 30b84288
......@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
#define EXYNOS5_GPIO_B2_NR (4)
#define EXYNOS5_GPIO_B3_NR (4)
#define EXYNOS5_GPIO_C0_NR (7)
#define EXYNOS5_GPIO_C1_NR (7)
#define EXYNOS5_GPIO_C1_NR (4)
#define EXYNOS5_GPIO_C2_NR (7)
#define EXYNOS5_GPIO_C3_NR (7)
#define EXYNOS5_GPIO_D0_NR (8)
#define EXYNOS5_GPIO_C4_NR (7)
#define EXYNOS5_GPIO_D0_NR (4)
#define EXYNOS5_GPIO_D1_NR (8)
#define EXYNOS5_GPIO_Y0_NR (6)
#define EXYNOS5_GPIO_Y1_NR (4)
......@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
......@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
......
arch/arm/mach-exynos/include/mach/irqs.h
View file @ 30b84288
......@@ -287,6 +287,7 @@
#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
......@@ -295,8 +296,8 @@
#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
#define EXYNOS5_IRQ_2D IRQ_SPI(91)
#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
......@@ -310,7 +311,7 @@
#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
......@@ -319,8 +320,9 @@
#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
......@@ -328,7 +330,6 @@
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
......@@ -339,6 +340,8 @@
#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
......@@ -362,8 +365,8 @@
#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
......@@ -375,11 +378,9 @@
#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
......@@ -395,17 +396,24 @@
#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
......@@ -436,7 +444,7 @@
#define EXYNOS5_MAX_COMBINER_NR 32
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
......
arch/arm/mach-exynos/include/mach/map.h
View file @ 30b84288
......@@ -34,6 +34,9 @@
#define EXYNOS4_PA_JPEG 0x11840000
/* x = 0...1 */
#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
#define EXYNOS4_PA_G2D 0x12800000
#define EXYNOS4_PA_I2S0 0x03830000
......@@ -78,8 +81,8 @@
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10480000
#define EXYNOS5_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10482000
#define EXYNOS5_PA_GIC_DIST 0x10481000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600
......
arch/arm/mach-exynos/include/mach/regs-clock.h
View file @ 30b84288
......@@ -322,6 +322,8 @@
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
......
arch/arm/mach-exynos/include/mach/regs-pmu.h
View file @ 30b84288
......@@ -180,7 +180,7 @@
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
/* Only for EXYNOS4212 */
/* Only for EXYNOS4x12 */
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
......@@ -221,4 +221,12 @@
#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
/* Only for EXYNOS4412 */
#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
#endif /* __ASM_ARCH_REGS_PMU_H */
arch/arm/mach-exynos/include/mach/spi-clocks.h
View file @ 30b84288
......@@ -11,6 +11,6 @@
#define __ASM_ARCH_SPI_CLKS_H __FILE__
/* Must source from SCLK_SPI */
#define EXYNOS4_SPI_SRCCLK_SCLK 0
#define EXYNOS_SPI_SRCCLK_SCLK 0
#endif /* __ASM_ARCH_SPI_CLKS_H */
arch/arm/mach-exynos/mach-exynos5-dt.c
View file @ 30b84288
......@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
"s3c2440-i2c.0", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
"s3c2440-i2c.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
......
arch/arm/mach-exynos/mct.c
View file @ 30b84288
......@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
int mct_lx_irq;
mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
......@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
evt->irq = EXYNOS4_IRQ_MCT_L0;
setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
evt->irq = mct_lx_irq;
setup_irq(mct_lx_irq, &mct_tick0_event_irq);
} else {
mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
evt->irq = EXYNOS4_IRQ_MCT_L1;
setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
evt->irq = mct_lx_irq;
setup_irq(mct_lx_irq, &mct_tick1_event_irq);
irq_set_affinity(mct_lx_irq, cpumask_of(1));
}
} else {
enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
......@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
if (soc_is_exynos4210())
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
mct_int_type = MCT_INT_PPI;
......
arch/arm/mach-exynos/pm.c
View file @ 30b84288
......@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
static struct subsys_interface exynos4_pm_interface = {
.name = "exynos4_pm",
.subsys = &exynos4_subsys,
.subsys = &exynos_subsys,
.add_dev = exynos4_pm_add,
};
......@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
if (soc_is_exynos4212()) {
if (soc_is_exynos4212() || soc_is_exynos4412()) {
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
S5P_USE_STANDBYWFE_ISP_ARM);
......
arch/arm/mach-exynos/pmu.c
View file @ 30b84288
......@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
{ PMU_TABLE_END,},
};
static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
......@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
{ PMU_TABLE_END,},
};
static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
{ S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
{ PMU_TABLE_END,},
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
......@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos4_pmu_config[i].val[mode],
exynos4_pmu_config[i].reg);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
__raw_writel(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
}
}
static int __init exynos4_pmu_init(void)
......@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
if (soc_is_exynos4210()) {
exynos4_pmu_config = exynos4210_pmu_config;
pr_info("EXYNOS4210 PMU Initialize\n");
} else if (soc_is_exynos4212()) {
exynos4_pmu_config = exynos4212_pmu_config;
pr_info("EXYNOS4212 PMU Initialize\n");
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos4_pmu_config = exynos4x12_pmu_config;
pr_info("EXYNOS4x12 PMU Initialize\n");
} else {
pr_info("EXYNOS4: PMU not supported\n");
}
......
arch/arm/mach-s3c24xx/Kconfig
View file @ 30b84288
......@@ -518,6 +518,11 @@ config S3C2443_DMA
help
Internal config node for S3C2443 DMA support
config S3C2443_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations
endif # CPU_S3C2443 || CPU_S3C2416
if CPU_S3C2443
......
arch/arm/mach-s3c24xx/Makefile
View file @ 30b84288
......@@ -97,5 +97,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
# device setup
obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o
obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o
obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o
arch/arm/mach-s3c24xx/clock-s3c2416.c
View file @ 30b84288
......@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
};
void __init s3c2416_init_clocks(int xtal)
......
arch/arm/mach-s3c24xx/clock-s3c2443.c
View file @ 30b84288
......@@ -179,6 +179,11 @@ static struct clk *clks[] __initdata = {
&clk_hsmmc,
};
static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
};
void __init s3c2443_init_clocks(int xtal)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
......@@ -210,6 +215,7 @@ void __init s3c2443_init_clocks(int xtal)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
s3c_pwmclk_init();
}
arch/arm/mach-s3c24xx/common-s3c2443.c
View file @ 30b84288
......@@ -423,11 +423,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "hsspi",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_HSSPI,
}, {
.name = "adc",
.parent = &clk_p,
......@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
.ctrlbit = S3C2443_HCLKCON_HSMMC,
};
static struct clk hsspi_clk = {
.name = "spi",
.devname = "s3c64xx-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_HSSPI,
};
/* EPLLCON compatible enough to get on/off information */
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
......@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
&clk_usb_bus,
&clk_armdiv,
&hsmmc1_clk,
&hsspi_clk,
};
static struct clksrc_clk *clksrcs[] __initdata = {
......@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
};
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
......
arch/arm/mach-s3c24xx/dma-s3c2443.c
View file @ 30b84288
......@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
.name = "sdi",
.channels = MAP(S3C2443_DMAREQSEL_SDI),
},
[DMACH_SPI0] = {
.name = "spi0",
[DMACH_SPI0_RX] = {
.name = "spi0-rx",
.channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
},
[DMACH_SPI0_TX] = {
.name = "spi0-tx",
.channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
},
[DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
.name = "spi1",
[DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
.name = "spi1-rx",
.channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
},
[DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
.name = "spi1-tx",
.channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
},
[DMACH_UART0] = {
......
arch/arm/mach-s3c24xx/include/mach/dma.h
View file @ 30b84288
......@@ -47,6 +47,10 @@ enum dma_ch {
DMACH_UART2_SRC2,
DMACH_UART3, /* s3c2443 has extra uart */
DMACH_UART3_SRC2,
DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
DMACH_MAX, /* the end entry */
};
......
arch/arm/mach-s3c24xx/include/mach/map.h
View file @ 30b84288
......@@ -98,6 +98,8 @@
/* SPI */
#define S3C2410_PA_SPI (0x59000000)
#define S3C2443_PA_SPI0 (0x52000000)
#define S3C2443_PA_SPI1 S3C2410_PA_SPI
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
......@@ -162,4 +164,7 @@
#define S3C_PA_WDT S3C2410_PA_WATCHDOG
#define S3C_PA_NAND S3C24XX_PA_NAND
#define S3C_PA_SPI0 S3C2443_PA_SPI0
#define S3C_PA_SPI1 S3C2443_PA_SPI1
#endif /* __ASM_ARCH_MAP_H */
arch/arm/mach-s3c24xx/setup-spi.c 0 → 100644
View file @ 30b84288
/*
* HS-SPI device setup for S3C2443/S3C2416
*
* Copyright (C) 2011 Samsung Electronics Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
#include <plat/s3c64xx-spi.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
.fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13,
.tx_st_done = 21,
.high_speed = 1,
};
int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
{
/* enable hsspi bit in misccr */
s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
#endif
arch/arm/mach-spear13xx/Kconfig 0 → 100644
View file @ 30b84288
#
# SPEAr13XX Machine configuration file
#
if ARCH_SPEAR13XX
menu "SPEAr13xx Implementations"
config MACH_SPEAR1310
bool "SPEAr1310 Machine support with Device Tree"
select PINCTRL_SPEAR1310
help
Supports ST SPEAr1310 machine configured via the device-tree
config MACH_SPEAR1340
bool "SPEAr1340 Machine support with Device Tree"
select PINCTRL_SPEAR1340
help
Supports ST SPEAr1340 machine configured via the device-tree
endmenu
endif #ARCH_SPEAR13XX
arch/arm/mach-spear13xx/Makefile 0 → 100644
View file @ 30b84288
#
# Makefile for SPEAr13XX machine series
#
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o
arch/arm/mach-spear13xx/Makefile.boot 0 → 100644
View file @ 30b84288
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
dtb-$(CONFIG_MACH_SPEAR1310) += spear1310-evb.dtb
dtb-$(CONFIG_MACH_SPEAR1340) += spear1340-evb.dtb
arch/arm/mach-spear13xx/headsmp.S 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13XX/headsmp.S
*
* Picked from realview
* Copyright (c) 2012 ST Microelectronics Limited
* Shiraz Hashim <shiraz.hashim@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__INIT
/*
* spear13xx specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(spear13xx_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
add r6, r6, r4
pen: ldr r7, [r6]
cmp r7, r0
bne pen
/* re-enable coherency */
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #(1 << 6) | (1 << 0)
mcr p15, 0, r0, c1, c0, 1
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
.align
1: .long .
.long pen_release
ENDPROC(spear13xx_secondary_startup)
arch/arm/mach-spear13xx/hotplug.c 0 → 100644
View file @ 30b84288
/*
* linux/arch/arm/mach-spear13xx/hotplug.c
*
* Copyright (C) 2012 ST Microelectronics Ltd.
* Deepak Sikri <deepak.sikri@st.com>
*
* based upon linux/arch/arm/mach-realview/hotplug.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
flush_cache_all();
asm volatile(
" mcr p15, 0, %1, c7, c5, 0\n"
" dsb\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x20\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C)
: "cc", "memory");
}
static inline void cpu_leave_lowpower(void)
{
unsigned int v;
asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
" orr %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
" mrc p15, 0, %0, c1, c0, 1\n"
" orr %0, %0, #0x20\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (CR_C)
: "cc");
}
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
for (;;) {
wfi();
if (pen_release == cpu) {
/*
* OK, proper wakeup, we're done
*/
break;
}
/*
* Getting here, means that we have come out of WFI without
* having been woken up - this shouldn't happen
*
* Just note it happening - when we're woken, we can report
* its occurrence.
*/
(*spurious)++;
}
}
int platform_cpu_kill(unsigned int cpu)
{
return 1;
}
/*
* platform-specific code to shutdown a CPU
*
* Called with IRQs disabled
*/
void __cpuinit platform_cpu_die(unsigned int cpu)
{
int spurious = 0;
/*
* we're ready for shutdown now, so do it
*/
cpu_enter_lowpower();
platform_do_lowpower(cpu, &spurious);
/*
* bring this CPU back into the world of cache
* coherency, and then restore interrupts
*/
cpu_leave_lowpower();
if (spurious)
pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
}
int platform_cpu_disable(unsigned int cpu)
{
/*
* we don't allow CPU 0 to be shutdown (it is still too special
* e.g. clock tick interrupts)
*/
return cpu == 0 ? -EPERM : 0;
}
arch/arm/mach-spear13xx/include/mach/debug-macro.S 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/debug-macro.S
*
* Debugging macro include header spear13xx machine family
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <plat/debug-macro.S>
arch/arm/mach-spear13xx/include/mach/dma.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/dma.h
*
* DMA information for SPEAr13xx machine family
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* request id of all the peripherals */
enum dma_master_info {
/* Accessible from only one master */
DMA_MASTER_MCIF = 0,
DMA_MASTER_FSMC = 1,
/* Accessible from both 0 & 1 */
DMA_MASTER_MEMORY = 0,
DMA_MASTER_ADC = 0,
DMA_MASTER_UART0 = 0,
DMA_MASTER_SSP0 = 0,
DMA_MASTER_I2C0 = 0,
#ifdef CONFIG_MACH_SPEAR1310
/* Accessible from only one master */
SPEAR1310_DMA_MASTER_JPEG = 1,
/* Accessible from both 0 & 1 */
SPEAR1310_DMA_MASTER_I2S = 0,
SPEAR1310_DMA_MASTER_UART1 = 0,
SPEAR1310_DMA_MASTER_UART2 = 0,
SPEAR1310_DMA_MASTER_UART3 = 0,
SPEAR1310_DMA_MASTER_UART4 = 0,
SPEAR1310_DMA_MASTER_UART5 = 0,
SPEAR1310_DMA_MASTER_I2C1 = 0,
SPEAR1310_DMA_MASTER_I2C2 = 0,
SPEAR1310_DMA_MASTER_I2C3 = 0,
SPEAR1310_DMA_MASTER_I2C4 = 0,
SPEAR1310_DMA_MASTER_I2C5 = 0,
SPEAR1310_DMA_MASTER_I2C6 = 0,
SPEAR1310_DMA_MASTER_I2C7 = 0,
SPEAR1310_DMA_MASTER_SSP1 = 0,
#endif
#ifdef CONFIG_MACH_SPEAR1340
/* Accessible from only one master */
SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
SPEAR1340_DMA_MASTER_I2S_REC = 1,
SPEAR1340_DMA_MASTER_I2C1 = 1,
SPEAR1340_DMA_MASTER_UART1 = 1,
/* following are accessible from both master 0 & 1 */
SPEAR1340_DMA_MASTER_SPDIF = 0,
SPEAR1340_DMA_MASTER_CAM = 1,
SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
SPEAR1340_DMA_MASTER_MALI = 0,
#endif
};
enum request_id {
DMA_REQ_ADC = 0,
DMA_REQ_SSP0_TX = 4,
DMA_REQ_SSP0_RX = 5,
DMA_REQ_UART0_TX = 6,
DMA_REQ_UART0_RX = 7,
DMA_REQ_I2C0_TX = 8,
DMA_REQ_I2C0_RX = 9,
#ifdef CONFIG_MACH_SPEAR1310
SPEAR1310_DMA_REQ_FROM_JPEG = 2,
SPEAR1310_DMA_REQ_TO_JPEG = 3,
SPEAR1310_DMA_REQ_I2S_TX = 10,
SPEAR1310_DMA_REQ_I2S_RX = 11,
SPEAR1310_DMA_REQ_I2C1_RX = 0,
SPEAR1310_DMA_REQ_I2C1_TX = 1,
SPEAR1310_DMA_REQ_I2C2_RX = 2,
SPEAR1310_DMA_REQ_I2C2_TX = 3,
SPEAR1310_DMA_REQ_I2C3_RX = 4,
SPEAR1310_DMA_REQ_I2C3_TX = 5,
SPEAR1310_DMA_REQ_I2C4_RX = 6,
SPEAR1310_DMA_REQ_I2C4_TX = 7,
SPEAR1310_DMA_REQ_I2C5_RX = 8,
SPEAR1310_DMA_REQ_I2C5_TX = 9,
SPEAR1310_DMA_REQ_I2C6_RX = 10,
SPEAR1310_DMA_REQ_I2C6_TX = 11,
SPEAR1310_DMA_REQ_UART1_RX = 12,
SPEAR1310_DMA_REQ_UART1_TX = 13,
SPEAR1310_DMA_REQ_UART2_RX = 14,
SPEAR1310_DMA_REQ_UART2_TX = 15,
SPEAR1310_DMA_REQ_UART5_RX = 16,
SPEAR1310_DMA_REQ_UART5_TX = 17,
SPEAR1310_DMA_REQ_SSP1_RX = 18,
SPEAR1310_DMA_REQ_SSP1_TX = 19,
SPEAR1310_DMA_REQ_I2C7_RX = 20,
SPEAR1310_DMA_REQ_I2C7_TX = 21,
SPEAR1310_DMA_REQ_UART3_RX = 28,
SPEAR1310_DMA_REQ_UART3_TX = 29,
SPEAR1310_DMA_REQ_UART4_RX = 30,
SPEAR1310_DMA_REQ_UART4_TX = 31,
#endif
#ifdef CONFIG_MACH_SPEAR1340
SPEAR1340_DMA_REQ_SPDIF_TX = 2,
SPEAR1340_DMA_REQ_SPDIF_RX = 3,
SPEAR1340_DMA_REQ_I2S_TX = 10,
SPEAR1340_DMA_REQ_I2S_RX = 11,
SPEAR1340_DMA_REQ_UART1_TX = 12,
SPEAR1340_DMA_REQ_UART1_RX = 13,
SPEAR1340_DMA_REQ_I2C1_TX = 14,
SPEAR1340_DMA_REQ_I2C1_RX = 15,
SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
SPEAR1340_DMA_REQ_CAM0_ODD = 1,
SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
SPEAR1340_DMA_REQ_CAM1_ODD = 3,
SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
SPEAR1340_DMA_REQ_CAM2_ODD = 5,
SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
SPEAR1340_DMA_REQ_CAM3_ODD = 7,
#endif
};
#endif /* __MACH_DMA_H */
arch/arm/mach-spear13xx/include/mach/generic.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/generic.h
*
* spear13xx machine family generic header file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_GENERIC_H
#define __MACH_GENERIC_H
#include <linux/dmaengine.h>
#include <asm/mach/time.h>
/* Add spear13xx structure declarations here */
extern struct sys_timer spear13xx_timer;
extern struct pl022_ssp_controller pl022_plat_data;
extern struct dw_dma_platform_data dmac_plat_data;
extern struct dw_dma_slave cf_dma_priv;
extern struct dw_dma_slave nand_read_dma_priv;
extern struct dw_dma_slave nand_write_dma_priv;
/* Add spear13xx family function declarations here */
void __init spear_setup_of_timer(void);
void __init spear13xx_map_io(void);
void __init spear13xx_dt_init_irq(void);
void __init spear13xx_l2x0_init(void);
bool dw_dma_filter(struct dma_chan *chan, void *slave);
void spear_restart(char, const char *);
void spear13xx_secondary_startup(void);
#ifdef CONFIG_MACH_SPEAR1310
void __init spear1310_clk_init(void);
#else
static inline void spear1310_clk_init(void) {}
#endif
#ifdef CONFIG_MACH_SPEAR1340
void __init spear1340_clk_init(void);
#else
static inline void spear1340_clk_init(void) {}
#endif
#endif /* __MACH_GENERIC_H */
arch/arm/mach-spear13xx/include/mach/gpio.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/gpio.h
*
* GPIO macros for SPEAr13xx machine family
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_GPIO_H
#define __MACH_GPIO_H
#include <plat/gpio.h>
#endif /* __MACH_GPIO_H */
arch/arm/mach-spear13xx/include/mach/irqs.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/irqs.h
*
* IRQ helper macros for spear13xx machine family
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_GIC_END 160
#define NR_IRQS IRQ_GIC_END
#endif /* __MACH_IRQS_H */
arch/arm/mach-spear13xx/include/mach/spear.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/spear.h
*
* spear13xx Machine family specific definition
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_SPEAR13XX_H
#define __MACH_SPEAR13XX_H
#include <asm/memory.h>
#define PERIP_GRP2_BASE UL(0xB3000000)
#define VA_PERIP_GRP2_BASE UL(0xFE000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
#define VA_SYSRAM0_BASE UL(0xFE800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
#define VA_PERIP_GRP1_BASE UL(0xFD000000)
#define UART_BASE UL(0xE0000000)
#define VA_UART_BASE UL(0xFD000000)
#define SSP_BASE UL(0xE0100000)
#define MISC_BASE UL(0xE0700000)
#define VA_MISC_BASE IOMEM(UL(0xFD700000))
#define A9SM_AND_MPMC_BASE UL(0xEC000000)
#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000)
/* A9SM peripheral offsets */
#define A9SM_PERIP_BASE UL(0xEC800000)
#define VA_A9SM_PERIP_BASE UL(0xFC800000)
#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
#define L2CC_BASE UL(0xED000000)
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
/* others */
#define DMAC0_BASE UL(0xEA800000)
#define DMAC1_BASE UL(0xEB000000)
#define MCIF_CF_BASE UL(0xB2800000)
/* Devices present in SPEAr1310 */
#ifdef CONFIG_MACH_SPEAR1310
#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
#define SPEAR1310_RAS_BASE UL(0xD8400000)
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
#endif /* CONFIG_MACH_SPEAR1310 */
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
#endif /* __MACH_SPEAR13XX_H */
arch/arm/mach-spear13xx/include/mach/timex.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear3xx/include/mach/timex.h
*
* SPEAr3XX machine family specific timex definitions
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_TIMEX_H
#define __MACH_TIMEX_H
#include <plat/timex.h>
#endif /* __MACH_TIMEX_H */
arch/arm/mach-spear13xx/include/mach/uncompress.h 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/include/mach/uncompress.h
*
* Serial port stubs for kernel decompress status messages
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_UNCOMPRESS_H
#define __MACH_UNCOMPRESS_H
#include <plat/uncompress.h>
#endif /* __MACH_UNCOMPRESS_H */
arch/arm/mach-spear13xx/platsmp.c 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/platsmp.c
*
* based upon linux/arch/arm/mach-realview/platsmp.c
*
* Copyright (C) 2012 ST Microelectronics Ltd.
* Shiraz Hashim <shiraz.hashim@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <asm/smp_scu.h>
#include <mach/spear.h>
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
extern void spear13xx_secondary_startup(void);
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
smp_wmb();
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
pen_release = cpu;
flush_cache_all();
outer_flush_all();
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (pen_release == -1)
break;
udelay(10);
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
void __init smp_init_cpus(void)
{
unsigned int i, ncores = scu_get_core_count(scu_base);
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
ncores, nr_cpu_ids);
ncores = nr_cpu_ids;
}
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
scu_enable(scu_base);
/*
* Write the address of secondary startup into the system-wide location
* (presently it is in SRAM). The BootMonitor waits until it receives a
* soft interrupt, and then the secondary CPU branches to this address.
*/
__raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
}
arch/arm/mach-spear13xx/spear1310.c 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/spear1310.c
*
* SPEAr1310 machine source file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define pr_fmt(fmt) "SPEAr1310: " fmt
#include <linux/amba/pl022.h>
#include <linux/of_platform.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/generic.h>
#include <mach/spear.h>
/* Base addresses */
#define SPEAR1310_SSP1_BASE UL(0x5D400000)
#define SPEAR1310_SATA0_BASE UL(0xB1000000)
#define SPEAR1310_SATA1_BASE UL(0xB1800000)
#define SPEAR1310_SATA2_BASE UL(0xB4000000)
/* ssp device registration */
static struct pl022_ssp_controller ssp1_plat_data = {
.bus_id = 0,
.enable_dma = 0,
.num_chipselect = 3,
};
/* Add SPEAr1310 auxdata to pass platform data */
static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
{}
};
static void __init spear1310_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
spear1310_auxdata_lookup, NULL);
}
static const char * const spear1310_dt_board_compat[] = {
"st,spear1310",
"st,spear1310-evb",
NULL,
};
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
* 0xD8000000 0xFA000000
*/
struct map_desc spear1310_io_desc[] __initdata = {
{
.virtual = VA_SPEAR1310_RAS_GRP1_BASE,
.pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
.length = SZ_16M,
.type = MT_DEVICE
},
};
static void __init spear1310_map_io(void)
{
iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
spear13xx_map_io();
}
DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
.map_io = spear1310_map_io,
.init_irq = spear13xx_dt_init_irq,
.handle_irq = gic_handle_irq,
.timer = &spear13xx_timer,
.init_machine = spear1310_dt_init,
.restart = spear_restart,
.dt_compat = spear1310_dt_board_compat,
MACHINE_END
arch/arm/mach-spear13xx/spear1340.c 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/spear1340.c
*
* SPEAr1340 machine source file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define pr_fmt(fmt) "SPEAr1340: " fmt
#include <linux/ahci_platform.h>
#include <linux/amba/serial.h>
#include <linux/delay.h>
#include <linux/dw_dmac.h>
#include <linux/of_platform.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <mach/dma.h>
#include <mach/generic.h>
#include <mach/spear.h>
/* Base addresses */
#define SPEAR1340_SATA_BASE UL(0xB1000000)
#define SPEAR1340_UART1_BASE UL(0xB4100000)
/* Power Management Registers */
#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
/* PCIE - SATA configuration registers */
#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
/* PCIE CFG MASks */
#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
#define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
#define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
#define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
#define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
#define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
#define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
#define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
#define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
#define SPEAR1340_PCIE_SATA_SEL_SATA (1)
#define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
SPEAR1340_PCIE_CFG_POWERUP_RESET | \
SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
SPEAR1340_SATA_CFG_PM_CLK_EN | \
SPEAR1340_SATA_CFG_POWERUP_RESET | \
SPEAR1340_SATA_CFG_RX_CLK_EN | \
SPEAR1340_SATA_CFG_TX_CLK_EN)
#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
#define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
#define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_CLK_REF_DIV2 | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
static struct dw_dma_slave uart1_dma_param[] = {
{
/* Tx */
.cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
.cfg_lo = 0,
.src_master = DMA_MASTER_MEMORY,
.dst_master = SPEAR1340_DMA_MASTER_UART1,
}, {
/* Rx */
.cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
.cfg_lo = 0,
.src_master = SPEAR1340_DMA_MASTER_UART1,
.dst_master = DMA_MASTER_MEMORY,
}
};
static struct amba_pl011_data uart1_data = {
.dma_filter = dw_dma_filter,
.dma_tx_param = &uart1_dma_param[0],
.dma_rx_param = &uart1_dma_param[1],
};
/* SATA device registration */
static int sata_miphy_init(struct device *dev, void __iomem *addr)
{
writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
SPEAR1340_PCIE_MIPHY_CFG);
/* Switch on sata power domain */
writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
msleep(20);
/* Disable PCIE SATA Controller reset */
writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
SPEAR1340_PERIP1_SW_RST);
msleep(20);
return 0;
}
void sata_miphy_exit(struct device *dev)
{
writel(0, SPEAR1340_PCIE_SATA_CFG);
writel(0, SPEAR1340_PCIE_MIPHY_CFG);
/* Enable PCIE SATA Controller reset */
writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
SPEAR1340_PERIP1_SW_RST);
msleep(20);
/* Switch off sata power domain */
writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
msleep(20);
}
int sata_suspend(struct device *dev)
{
if (dev->power.power_state.event == PM_EVENT_FREEZE)
return 0;
sata_miphy_exit(dev);
return 0;
}
int sata_resume(struct device *dev)
{
if (dev->power.power_state.event == PM_EVENT_THAW)
return 0;
return sata_miphy_init(dev, NULL);
}
static struct ahci_platform_data sata_pdata = {
.init = sata_miphy_init,
.exit = sata_miphy_exit,
.suspend = sata_suspend,
.resume = sata_resume,
};
/* Add SPEAr1340 auxdata to pass platform data */
static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
&sata_pdata),
OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
{}
};
static void __init spear1340_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
spear1340_auxdata_lookup, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
"st,spear1340",
"st,spear1340-evb",
NULL,
};
DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
.map_io = spear13xx_map_io,
.init_irq = spear13xx_dt_init_irq,
.handle_irq = gic_handle_irq,
.timer = &spear13xx_timer,
.init_machine = spear1340_dt_init,
.restart = spear_restart,
.dt_compat = spear1340_dt_board_compat,
MACHINE_END
arch/arm/mach-spear13xx/spear13xx.c 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/spear13xx.c
*
* SPEAr13XX machines common source file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define pr_fmt(fmt) "SPEAr13xx: " fmt
#include <linux/amba/pl022.h>
#include <linux/clk.h>
#include <linux/dw_dmac.h>
#include <linux/err.h>
#include <linux/of_irq.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
#include <asm/smp_twd.h>
#include <mach/dma.h>
#include <mach/generic.h>
#include <mach/spear.h>
/* common dw_dma filter routine to be used by peripherals */
bool dw_dma_filter(struct dma_chan *chan, void *slave)
{
struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
if (chan->device->dev == dws->dma_dev) {
chan->private = slave;
return true;
} else {
return false;
}
}
/* ssp device registration */
static struct dw_dma_slave ssp_dma_param[] = {
{
/* Tx */
.cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
.cfg_lo = 0,
.src_master = DMA_MASTER_MEMORY,
.dst_master = DMA_MASTER_SSP0,
}, {
/* Rx */
.cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
.cfg_lo = 0,
.src_master = DMA_MASTER_SSP0,
.dst_master = DMA_MASTER_MEMORY,
}
};
struct pl022_ssp_controller pl022_plat_data = {
.bus_id = 0,
.enable_dma = 1,
.dma_filter = dw_dma_filter,
.dma_rx_param = &ssp_dma_param[1],
.dma_tx_param = &ssp_dma_param[0],
.num_chipselect = 3,
};
/* CF device registration */
struct dw_dma_slave cf_dma_priv = {
.cfg_hi = 0,
.cfg_lo = 0,
.src_master = 0,
.dst_master = 0,
};
/* dmac device registeration */
struct dw_dma_platform_data dmac_plat_data = {
.nr_channels = 8,
.chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
.chan_priority = CHAN_PRIORITY_DESCENDING,
};
void __init spear13xx_l2x0_init(void)
{
/*
* 512KB (64KB/way), 8-way associativity, parity supported
*
* FIXME: 9th bit, of Auxillary Controller register must be set
* for some spear13xx devices for stable L2 operation.
*
* Enable Early BRESP, L2 prefetch for Instruction and Data,
* write alloc and 'Full line of zero' options
*
*/
writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
/*
* Program following latencies in order to make
* SPEAr1340 work at 600 MHz
*/
writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
}
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
* 0xB3000000 0xFE000000
* 0xE0000000 0xFD000000
* 0xEC000000 0xFC000000
* 0xED000000 0xFB000000
*/
struct map_desc spear13xx_io_desc[] __initdata = {
{
.virtual = VA_PERIP_GRP2_BASE,
.pfn = __phys_to_pfn(PERIP_GRP2_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = VA_PERIP_GRP1_BASE,
.pfn = __phys_to_pfn(PERIP_GRP1_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = VA_A9SM_AND_MPMC_BASE,
.pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}, {
.virtual = (unsigned long)VA_L2CC_BASE,
.pfn = __phys_to_pfn(L2CC_BASE),
.length = SZ_4K,
.type = MT_DEVICE
},
};
/* This will create static memory mapping for selected devices */
void __init spear13xx_map_io(void)
{
iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
}
static void __init spear13xx_clk_init(void)
{
if (of_machine_is_compatible("st,spear1310"))
spear1310_clk_init();
else if (of_machine_is_compatible("st,spear1340"))
spear1340_clk_init();
else
pr_err("%s: Unknown machine\n", __func__);
}
static void __init spear13xx_timer_init(void)
{
char pclk_name[] = "osc_24m_clk";
struct clk *gpt_clk, *pclk;
spear13xx_clk_init();
/* get the system timer clock */
gpt_clk = clk_get_sys("gpt0", NULL);
if (IS_ERR(gpt_clk)) {
pr_err("%s:couldn't get clk for gpt\n", __func__);
BUG();
}
/* get the suitable parent clock for timer*/
pclk = clk_get(NULL, pclk_name);
if (IS_ERR(pclk)) {
pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
pclk_name);
BUG();
}
clk_set_parent(gpt_clk, pclk);
clk_put(gpt_clk);
clk_put(pclk);
spear_setup_of_timer();
twd_local_timer_of_register();
}
struct sys_timer spear13xx_timer = {
.init = spear13xx_timer_init,
};
static const struct of_device_id gic_of_match[] __initconst = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
{ /* Sentinel */ }
};
void __init spear13xx_dt_init_irq(void)
{
of_irq_init(gic_of_match);
}
arch/arm/plat-samsung/Kconfig
View file @ 30b84288
......@@ -419,7 +419,7 @@ config S3C_DMA
config SAMSUNG_DMADEV
bool
select DMADEVICES
select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \
select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
CPU_S5P6450 || CPU_S5P6440)
select ARM_AMBA
help
......
arch/arm/plat-samsung/include/plat/cpu.h
View file @ 30b84288
......@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
extern struct bus_type s5p64x0_subsys;
extern struct bus_type s5pv210_subsys;
extern struct bus_type exynos4_subsys;
extern struct bus_type exynos_subsys;
extern void (*s5pc1xx_idle)(void);
......
arch/arm/plat-samsung/include/plat/devs.h
View file @ 30b84288
......@@ -134,6 +134,8 @@ extern struct platform_device exynos4_device_pcm2;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos_device_drm;
extern struct platform_device samsung_asoc_dma;
extern struct platform_device samsung_asoc_idma;
extern struct platform_device samsung_device_keypad;
......
arch/arm/plat-samsung/include/plat/dma-pl330.h
View file @ 30b84288
......@@ -90,6 +90,7 @@ enum dma_ch {
DMACH_MIPI_HSI5,
DMACH_MIPI_HSI6,
DMACH_MIPI_HSI7,
DMACH_DISP1,
DMACH_MTOM_0,
DMACH_MTOM_1,
DMACH_MTOM_2,
......
arch/arm/plat-samsung/include/plat/s5p-clock.h
View file @ 30b84288
......@@ -32,8 +32,10 @@ extern struct clk clk_48m;
extern struct clk s5p_clk_27m;
extern struct clk clk_fout_apll;
extern struct clk clk_fout_bpll;
extern struct clk clk_fout_bpll_div2;
extern struct clk clk_fout_cpll;
extern struct clk clk_fout_mpll;
extern struct clk clk_fout_mpll_div2;
extern struct clk clk_fout_epll;
extern struct clk clk_fout_dpll;
extern struct clk clk_fout_vpll;
......@@ -42,8 +44,10 @@ extern struct clk clk_vpll;
extern struct clksrc_sources clk_src_apll;
extern struct clksrc_sources clk_src_bpll;
extern struct clksrc_sources clk_src_bpll_fout;
extern struct clksrc_sources clk_src_cpll;
extern struct clksrc_sources clk_src_mpll;
extern struct clksrc_sources clk_src_mpll_fout;
extern struct clksrc_sources clk_src_epll;
extern struct clksrc_sources clk_src_dpll;
......
arch/arm/plat-samsung/s5p-clock.c
View file @ 30b84288
......@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = {
.id = -1,
};
struct clk clk_fout_bpll_div2 = {
.name = "fout_bpll_div2",
.id = -1,
};
/* CPLL clock output */
struct clk clk_fout_cpll = {
......@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = {
.id = -1,
};
struct clk clk_fout_mpll_div2 = {
.name = "fout_mpll_div2",
.id = -1,
};
/* EPLL clock output */
struct clk clk_fout_epll = {
.name = "fout_epll",
......@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
.nr_sources = ARRAY_SIZE(clk_src_bpll_list),
};
static struct clk *clk_src_bpll_fout_list[] = {
[0] = &clk_fout_bpll_div2,
[1] = &clk_fout_bpll,
};
struct clksrc_sources clk_src_bpll_fout = {
.sources = clk_src_bpll_fout_list,
.nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
};
/* Possible clock sources for CPLL Mux */
static struct clk *clk_src_cpll_list[] = {
[0] = &clk_fin_cpll,
......@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
static struct clk *clk_src_mpll_fout_list[] = {
[0] = &clk_fout_mpll_div2,
[1] = &clk_fout_mpll,
};
struct clksrc_sources clk_src_mpll_fout = {
.sources = clk_src_mpll_fout_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
};
/* Possible clock sources for EPLL Mux */
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
......
arch/arm/plat-spear/Kconfig
View file @ 30b84288
......@@ -8,6 +8,17 @@ choice
prompt "ST SPEAr Family"
default ARCH_SPEAR3XX
config ARCH_SPEAR13XX
bool "ST SPEAr13xx with Device Tree"
select ARM_GIC
select CPU_V7
select USE_OF
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
help
Supports for ARM's SPEAR13XX family
config ARCH_SPEAR3XX
bool "ST SPEAr3xx with Device Tree"
select ARM_VIC
......@@ -27,6 +38,7 @@ config ARCH_SPEAR6XX
endchoice
# Adding SPEAr machine specific configuration files
source "arch/arm/mach-spear13xx/Kconfig"
source "arch/arm/mach-spear3xx/Kconfig"
source "arch/arm/mach-spear6xx/Kconfig"
......
arch/arm/plat-spear/Makefile
View file @ 30b84288
......@@ -3,6 +3,7 @@
#
# Common support
obj-y := restart.o time.o pl080.o
obj-y := restart.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o
obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
arch/arm/plat-spear/restart.c
View file @ 30b84288
......@@ -16,6 +16,7 @@
#include <mach/spear.h>
#include <mach/generic.h>
#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204)
void spear_restart(char mode, const char *cmd)
{
if (mode == 's') {
......@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd)
soft_restart(0);
} else {
/* hardware reset, Use on-chip reset capability */
#ifdef CONFIG_ARCH_SPEAR13XX
writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
#else
sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
#endif
}
}
drivers/clk/spear/Makefile
View file @ 30b84288
......@@ -6,3 +6,5 @@ obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o
obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o
obj-$(CONFIG_MACH_SPEAR1310) += spear1310_clock.o
obj-$(CONFIG_MACH_SPEAR1340) += spear1340_clock.o
drivers/clk/spear/spear1310_clock.c 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/spear1310_clock.c
*
* SPEAr1310 machine clock framework source file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/spinlock_types.h>
#include <mach/spear.h>
#include "clk.h"
/* PLL related registers and bit values */
#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
/* PLL_CFG bit values */
#define SPEAR1310_CLCD_SYNT_CLK_MASK 1
#define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
#define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
#define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
#define SPEAR1310_RAS_SYNT_CLK_MASK 2
#define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
#define SPEAR1310_PLL_CLK_MASK 2
#define SPEAR1310_PLL3_CLK_SHIFT 24
#define SPEAR1310_PLL2_CLK_SHIFT 22
#define SPEAR1310_PLL1_CLK_SHIFT 20
#define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214)
#define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218)
#define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220)
#define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224)
#define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C)
#define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230)
#define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238)
#define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C)
#define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
/* PERIP_CLK_CFG bit values */
#define SPEAR1310_GPT_OSC24_VAL 0
#define SPEAR1310_GPT_APB_VAL 1
#define SPEAR1310_GPT_CLK_MASK 1
#define SPEAR1310_GPT3_CLK_SHIFT 11
#define SPEAR1310_GPT2_CLK_SHIFT 10
#define SPEAR1310_GPT1_CLK_SHIFT 9
#define SPEAR1310_GPT0_CLK_SHIFT 8
#define SPEAR1310_UART_CLK_PLL5_VAL 0
#define SPEAR1310_UART_CLK_OSC24_VAL 1
#define SPEAR1310_UART_CLK_SYNT_VAL 2
#define SPEAR1310_UART_CLK_MASK 2
#define SPEAR1310_UART_CLK_SHIFT 4
#define SPEAR1310_AUX_CLK_PLL5_VAL 0
#define SPEAR1310_AUX_CLK_SYNT_VAL 1
#define SPEAR1310_CLCD_CLK_MASK 2
#define SPEAR1310_CLCD_CLK_SHIFT 2
#define SPEAR1310_C3_CLK_MASK 1
#define SPEAR1310_C3_CLK_SHIFT 1
#define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
#define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
#define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
#define SPEAR1310_GMAC_PHY_CLK_MASK 1
#define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
#define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
#define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
#define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
/* I2S_CLK_CFG register mask */
#define SPEAR1310_I2S_SCLK_X_MASK 0x1F
#define SPEAR1310_I2S_SCLK_X_SHIFT 27
#define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
#define SPEAR1310_I2S_SCLK_Y_SHIFT 22
#define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
#define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
#define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
#define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
#define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
#define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
#define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
#define SPEAR1310_I2S_REF_SEL_MASK 1
#define SPEAR1310_I2S_REF_SHIFT 2
#define SPEAR1310_I2S_SRC_CLK_MASK 2
#define SPEAR1310_I2S_SRC_CLK_SHIFT 0
#define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
#define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254)
#define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258)
#define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C)
#define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260)
#define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264)
#define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268)
#define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270)
#define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280)
#define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288)
#define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290)
#define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298)
/* Check Fractional synthesizer reg masks */
#define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300)
/* PERIP1_CLK_ENB register masks */
#define SPEAR1310_RTC_CLK_ENB 31
#define SPEAR1310_ADC_CLK_ENB 30
#define SPEAR1310_C3_CLK_ENB 29
#define SPEAR1310_JPEG_CLK_ENB 28
#define SPEAR1310_CLCD_CLK_ENB 27
#define SPEAR1310_DMA_CLK_ENB 25
#define SPEAR1310_GPIO1_CLK_ENB 24
#define SPEAR1310_GPIO0_CLK_ENB 23
#define SPEAR1310_GPT1_CLK_ENB 22
#define SPEAR1310_GPT0_CLK_ENB 21
#define SPEAR1310_I2S0_CLK_ENB 20
#define SPEAR1310_I2S1_CLK_ENB 19
#define SPEAR1310_I2C0_CLK_ENB 18
#define SPEAR1310_SSP_CLK_ENB 17
#define SPEAR1310_UART_CLK_ENB 15
#define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
#define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
#define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
#define SPEAR1310_UOC_CLK_ENB 11
#define SPEAR1310_UHC1_CLK_ENB 10
#define SPEAR1310_UHC0_CLK_ENB 9
#define SPEAR1310_GMAC_CLK_ENB 8
#define SPEAR1310_CFXD_CLK_ENB 7
#define SPEAR1310_SDHCI_CLK_ENB 6
#define SPEAR1310_SMI_CLK_ENB 5
#define SPEAR1310_FSMC_CLK_ENB 4
#define SPEAR1310_SYSRAM0_CLK_ENB 3
#define SPEAR1310_SYSRAM1_CLK_ENB 2
#define SPEAR1310_SYSROM_CLK_ENB 1
#define SPEAR1310_BUS_CLK_ENB 0
#define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304)
/* PERIP2_CLK_ENB register masks */
#define SPEAR1310_THSENS_CLK_ENB 8
#define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
#define SPEAR1310_ACP_CLK_ENB 6
#define SPEAR1310_GPT3_CLK_ENB 5
#define SPEAR1310_GPT2_CLK_ENB 4
#define SPEAR1310_KBD_CLK_ENB 3
#define SPEAR1310_CPU_DBG_CLK_ENB 2
#define SPEAR1310_DDR_CORE_CLK_ENB 1
#define SPEAR1310_DDR_CTRL_CLK_ENB 0
#define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310)
/* RAS_CLK_ENB register masks */
#define SPEAR1310_SYNT3_CLK_ENB 17
#define SPEAR1310_SYNT2_CLK_ENB 16
#define SPEAR1310_SYNT1_CLK_ENB 15
#define SPEAR1310_SYNT0_CLK_ENB 14
#define SPEAR1310_PCLK3_CLK_ENB 13
#define SPEAR1310_PCLK2_CLK_ENB 12
#define SPEAR1310_PCLK1_CLK_ENB 11
#define SPEAR1310_PCLK0_CLK_ENB 10
#define SPEAR1310_PLL3_CLK_ENB 9
#define SPEAR1310_PLL2_CLK_ENB 8
#define SPEAR1310_C125M_PAD_CLK_ENB 7
#define SPEAR1310_C30M_CLK_ENB 6
#define SPEAR1310_C48M_CLK_ENB 5
#define SPEAR1310_OSC_25M_CLK_ENB 4
#define SPEAR1310_OSC_32K_CLK_ENB 3
#define SPEAR1310_OSC_24M_CLK_ENB 2
#define SPEAR1310_PCLK_CLK_ENB 1
#define SPEAR1310_ACLK_CLK_ENB 0
/* RAS Area Control Register */
#define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000)
#define SPEAR1310_SSP1_CLK_MASK 3
#define SPEAR1310_SSP1_CLK_SHIFT 26
#define SPEAR1310_TDM_CLK_MASK 1
#define SPEAR1310_TDM2_CLK_SHIFT 24
#define SPEAR1310_TDM1_CLK_SHIFT 23
#define SPEAR1310_I2C_CLK_MASK 1
#define SPEAR1310_I2C7_CLK_SHIFT 22
#define SPEAR1310_I2C6_CLK_SHIFT 21
#define SPEAR1310_I2C5_CLK_SHIFT 20
#define SPEAR1310_I2C4_CLK_SHIFT 19
#define SPEAR1310_I2C3_CLK_SHIFT 18
#define SPEAR1310_I2C2_CLK_SHIFT 17
#define SPEAR1310_I2C1_CLK_SHIFT 16
#define SPEAR1310_GPT64_CLK_MASK 1
#define SPEAR1310_GPT64_CLK_SHIFT 15
#define SPEAR1310_RAS_UART_CLK_MASK 1
#define SPEAR1310_UART5_CLK_SHIFT 14
#define SPEAR1310_UART4_CLK_SHIFT 13
#define SPEAR1310_UART3_CLK_SHIFT 12
#define SPEAR1310_UART2_CLK_SHIFT 11
#define SPEAR1310_UART1_CLK_SHIFT 10
#define SPEAR1310_PCI_CLK_MASK 1
#define SPEAR1310_PCI_CLK_SHIFT 0
#define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004)
#define SPEAR1310_PHY_CLK_MASK 0x3
#define SPEAR1310_RMII_PHY_CLK_SHIFT 0
#define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
#define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148)
#define SPEAR1310_CAN1_CLK_ENB 25
#define SPEAR1310_CAN0_CLK_ENB 24
#define SPEAR1310_GPT64_CLK_ENB 23
#define SPEAR1310_SSP1_CLK_ENB 22
#define SPEAR1310_I2C7_CLK_ENB 21
#define SPEAR1310_I2C6_CLK_ENB 20
#define SPEAR1310_I2C5_CLK_ENB 19
#define SPEAR1310_I2C4_CLK_ENB 18
#define SPEAR1310_I2C3_CLK_ENB 17
#define SPEAR1310_I2C2_CLK_ENB 16
#define SPEAR1310_I2C1_CLK_ENB 15
#define SPEAR1310_UART5_CLK_ENB 14
#define SPEAR1310_UART4_CLK_ENB 13
#define SPEAR1310_UART3_CLK_ENB 12
#define SPEAR1310_UART2_CLK_ENB 11
#define SPEAR1310_UART1_CLK_ENB 10
#define SPEAR1310_RS485_1_CLK_ENB 9
#define SPEAR1310_RS485_0_CLK_ENB 8
#define SPEAR1310_TDM2_CLK_ENB 7
#define SPEAR1310_TDM1_CLK_ENB 6
#define SPEAR1310_PCI_CLK_ENB 5
#define SPEAR1310_GMII_CLK_ENB 4
#define SPEAR1310_MII2_CLK_ENB 3
#define SPEAR1310_MII1_CLK_ENB 2
#define SPEAR1310_MII0_CLK_ENB 1
#define SPEAR1310_ESRAM_CLK_ENB 0
static DEFINE_SPINLOCK(_lock);
/* pll rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll_rtbl[] = {
/* PCLK 24MHz */
{.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
{.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
};
/* vco-pll4 rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll4_rtbl[] = {
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
};
/* aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl aux_rtbl[] = {
/* For VCO1div2 = 500 MHz */
{.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
{.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
{.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
{.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
{.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
{.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
};
/* gmac rate configuration table, in ascending order of rates */
static struct aux_rate_tbl gmac_rtbl[] = {
/* For gmac phy input clk */
{.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
{.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
{.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
{.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
};
/* clcd rate configuration table, in ascending order of rates */
static struct frac_rate_tbl clcd_rtbl[] = {
{.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
{.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
{.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
{.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
};
/* i2s prescaler1 masks */
static struct aux_clk_masks i2s_prs1_masks = {
.eq_sel_mask = AUX_EQ_SEL_MASK,
.eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
.eq1_mask = AUX_EQ1_SEL,
.eq2_mask = AUX_EQ2_SEL,
.xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
.xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
.yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
.yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
};
/* i2s sclk (bit clock) syynthesizers masks */
static struct aux_clk_masks i2s_sclk_masks = {
.eq_sel_mask = AUX_EQ_SEL_MASK,
.eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
.eq1_mask = AUX_EQ1_SEL,
.eq2_mask = AUX_EQ2_SEL,
.xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
.xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
.yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
.yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
.enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
};
/* i2s prs1 aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl i2s_prs1_rtbl[] = {
/* For parent clk = 49.152 MHz */
{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
};
/* i2s sclk aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl i2s_sclk_rtbl[] = {
/* For i2s_ref_clk = 12.288MHz */
{.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
{.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
};
/* adc rate configuration table, in ascending order of rates */
/* possible adc range is 2.5 MHz to 20 MHz. */
static struct aux_rate_tbl adc_rtbl[] = {
/* For ahb = 166.67 MHz */
{.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
{.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
{.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
};
/* General synth rate configuration table, in ascending order of rates */
static struct frac_rate_tbl gen_rtbl[] = {
/* For vco1div4 = 250 MHz */
{.div = 0x14000}, /* 25 MHz */
{.div = 0x0A000}, /* 50 MHz */
{.div = 0x05000}, /* 100 MHz */
{.div = 0x02000}, /* 250 MHz */
};
/* clock parents */
static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", };
static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
"osc_25m_clk", };
static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
"gmac_phy_synth_gate_clk", };
static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
"i2s_src_pad_clk", };
static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
"pll3_clk", };
static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
"pll2_clk", };
static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
"ras_pll2_clk", "ras_synth0_clk", };
static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
"ras_pll2_clk", "ras_synth0_clk", };
static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", };
static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", };
static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk",
"ras_plclk0_clk", };
static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", };
static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", };
void __init spear1310_clk_init(void)
{
struct clk *clk, *clk1;
clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
clk_register_clkdev(clk, "apb_pclk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
32000);
clk_register_clkdev(clk, "osc_32k_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
24000000);
clk_register_clkdev(clk, "osc_24m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
25000000);
clk_register_clkdev(clk, "osc_25m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
CLK_IS_ROOT, 125000000);
clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
CLK_IS_ROOT, 12288000);
clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
/* clock derived from 32 KHz osc clk */
clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "fc900000.rtc");
/* clock derived from 24 or 25 MHz osc clk */
/* vco-pll */
clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "vco1_mux_clk", NULL);
clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco1_clk", NULL);
clk_register_clkdev(clk1, "pll1_clk", NULL);
clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "vco2_mux_clk", NULL);
clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco2_clk", NULL);
clk_register_clkdev(clk1, "pll2_clk", NULL);
clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "vco3_mux_clk", NULL);
clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco3_clk", NULL);
clk_register_clkdev(clk1, "pll3_clk", NULL);
clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco4_clk", NULL);
clk_register_clkdev(clk1, "pll4_clk", NULL);
clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
48000000);
clk_register_clkdev(clk, "pll5_clk", NULL);
clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
25000000);
clk_register_clkdev(clk, "pll6_clk", NULL);
/* vco div n clocks */
clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
2);
clk_register_clkdev(clk, "vco1div2_clk", NULL);
clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
4);
clk_register_clkdev(clk, "vco1div4_clk", NULL);
clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
2);
clk_register_clkdev(clk, "vco2div2_clk", NULL);
clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
2);
clk_register_clkdev(clk, "vco3div2_clk", NULL);
/* peripherals */
clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
128);
clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_thermal");
/* clock derived from pll4 clk */
clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
1);
clk_register_clkdev(clk, "ddr_clk", NULL);
/* clock derived from pll1 clk */
clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
clk_register_clkdev(clk, "cpu_clk", NULL);
clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
2);
clk_register_clkdev(clk, NULL, "ec800620.wdt");
clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
6);
clk_register_clkdev(clk, "ahb_clk", NULL);
clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
12);
clk_register_clkdev(clk, "apb_clk", NULL);
/* gpt clocks */
clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt0");
clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt1");
clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt2");
clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt3");
/* others */
clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "uart_synth_clk", NULL);
clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "uart0_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0000000.serial");
clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b3000000.sdhci");
clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b2800000.cf");
clk_register_clkdev(clk, NULL, "arasan_xd");
clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "c3_synth_clk", NULL);
clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "c3_mux_clk", NULL);
clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "c3");
/* gmac */
clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
gmac_phy_input_parents,
ARRAY_SIZE(gmac_phy_input_parents), 0,
SPEAR1310_GMAC_CLK_CFG,
SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
"gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT,
NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
ARRAY_SIZE(gmac_phy_parents), 0,
SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, NULL, "stmmacphy.0");
/* clcd */
clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
ARRAY_SIZE(clcd_synth_parents), 0,
SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
ARRAY_SIZE(clcd_rtbl), &_lock);
clk_register_clkdev(clk, "clcd_synth_clk", NULL);
clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
ARRAY_SIZE(clcd_pixel_parents), 0,
SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "clcd_clk", NULL);
/* i2s */
clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "i2s_src_clk", NULL);
clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2s_ref_clk", NULL);
clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
"i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
&i2s_sclk_masks, i2s_sclk_rtbl,
ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
/* clock derived from ahb clk */
clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0280000.i2c");
clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "ea800000.dma");
clk_register_clkdev(clk, NULL, "eb000000.dma");
clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b2000000.jpeg");
clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e2000000.eth");
clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b0000000.flash");
clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "ea000000.flash");
clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "usbh.0_clk", NULL);
clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "usbh.1_clk", NULL);
clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "uoc");
clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "dw_pcie.0");
clk_register_clkdev(clk, NULL, "ahci.0");
clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "dw_pcie.1");
clk_register_clkdev(clk, NULL, "ahci.1");
clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "dw_pcie.2");
clk_register_clkdev(clk, NULL, "ahci.2");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "sysram0_clk", NULL);
clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "sysram1_clk", NULL);
clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "adc_synth_clk", NULL);
clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "adc_clk");
/* clock derived from apb clk */
clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0100000.spi");
clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0600000.gpio");
clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0680000.gpio");
clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0180000.i2s");
clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0200000.i2s");
clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0300000.kbd");
/* RAS clks */
clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth0_clk", NULL);
clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth1_clk", NULL);
clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth2_clk", NULL);
clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth3_clk", NULL);
clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_pll2_clk", NULL);
clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_pll3_clk", NULL);
clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_tx125_clk", NULL);
clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
30000000);
clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_30m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
48000000);
clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_48m_clk", NULL);
clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_ahb_clk", NULL);
clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "ras_apb_clk", NULL);
clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
50000000);
clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
50000000);
clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "c_can_platform.0");
clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "c_can_platform.1");
clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5c400000.eth");
clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5c500000.eth");
clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5c600000.eth");
clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5c700000.eth");
clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk",
smii_rgmii_phy_parents,
ARRAY_SIZE(smii_rgmii_phy_parents), 0,
SPEAR1310_RAS_CTRL_REG1,
SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
SPEAR1310_PHY_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, NULL, "stmmacphy.1");
clk_register_clkdev(clk, NULL, "stmmacphy.2");
clk_register_clkdev(clk, NULL, "stmmacphy.4");
clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
ARRAY_SIZE(rmii_phy_parents), 0,
SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
SPEAR1310_PHY_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, NULL, "stmmacphy.3");
clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "uart1_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5c800000.serial");
clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents,
ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "uart2_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5c900000.serial");
clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents,
ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "uart3_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5ca00000.serial");
clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents,
ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "uart4_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5cb00000.serial");
clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents,
ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "uart5_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5cc00000.serial");
clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c1_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5cd00000.i2c");
clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c2_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5ce00000.i2c");
clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c3_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5cf00000.i2c");
clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c4_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5d000000.i2c");
clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c5_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5d100000.i2c");
clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c6_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5d200000.i2c");
clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents,
ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2c7_mux_clk", NULL);
clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5d300000.i2c");
clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents,
ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "ssp1_mux_clk", NULL);
clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "5d400000.spi");
clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents,
ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "pci_mux_clk", NULL);
clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "pci");
clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents,
ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "tdm1_mux_clk", NULL);
clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents,
ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "tdm2_mux_clk", NULL);
clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
}
drivers/clk/spear/spear1340_clock.c 0 → 100644
View file @ 30b84288
/*
* arch/arm/mach-spear13xx/spear1340_clock.c
*
* SPEAr1340 machine clock framework source file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/spinlock_types.h>
#include <mach/spear.h>
#include "clk.h"
/* Clock Configuration Registers */
#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
#define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
#define SPEAR1340_HCLK_SRC_SEL_MASK 1
#define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
#define SPEAR1340_SCLK_SRC_SEL_MASK 3
/* PLL related registers and bit values */
#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
/* PLL_CFG bit values */
#define SPEAR1340_CLCD_SYNT_CLK_MASK 1
#define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
#define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
#define SPEAR1340_GEN_SYNT_CLK_MASK 2
#define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
#define SPEAR1340_PLL_CLK_MASK 2
#define SPEAR1340_PLL3_CLK_SHIFT 24
#define SPEAR1340_PLL2_CLK_SHIFT 22
#define SPEAR1340_PLL1_CLK_SHIFT 20
#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
/* PERIP_CLK_CFG bit values */
#define SPEAR1340_SPDIF_CLK_MASK 1
#define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
#define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
#define SPEAR1340_GPT3_CLK_SHIFT 13
#define SPEAR1340_GPT2_CLK_SHIFT 12
#define SPEAR1340_GPT_CLK_MASK 1
#define SPEAR1340_GPT1_CLK_SHIFT 9
#define SPEAR1340_GPT0_CLK_SHIFT 8
#define SPEAR1340_UART_CLK_MASK 2
#define SPEAR1340_UART1_CLK_SHIFT 6
#define SPEAR1340_UART0_CLK_SHIFT 4
#define SPEAR1340_CLCD_CLK_MASK 2
#define SPEAR1340_CLCD_CLK_SHIFT 2
#define SPEAR1340_C3_CLK_MASK 1
#define SPEAR1340_C3_CLK_SHIFT 1
#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
#define SPEAR1340_GMAC_PHY_CLK_MASK 1
#define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
#define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
#define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
/* I2S_CLK_CFG register mask */
#define SPEAR1340_I2S_SCLK_X_MASK 0x1F
#define SPEAR1340_I2S_SCLK_X_SHIFT 27
#define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
#define SPEAR1340_I2S_SCLK_Y_SHIFT 22
#define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
#define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
#define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
#define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
#define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
#define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
#define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
#define SPEAR1340_I2S_REF_SEL_MASK 1
#define SPEAR1340_I2S_REF_SHIFT 2
#define SPEAR1340_I2S_SRC_CLK_MASK 2
#define SPEAR1340_I2S_SRC_CLK_SHIFT 0
#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
#define SPEAR1340_RTC_CLK_ENB 31
#define SPEAR1340_ADC_CLK_ENB 30
#define SPEAR1340_C3_CLK_ENB 29
#define SPEAR1340_CLCD_CLK_ENB 27
#define SPEAR1340_DMA_CLK_ENB 25
#define SPEAR1340_GPIO1_CLK_ENB 24
#define SPEAR1340_GPIO0_CLK_ENB 23
#define SPEAR1340_GPT1_CLK_ENB 22
#define SPEAR1340_GPT0_CLK_ENB 21
#define SPEAR1340_I2S_PLAY_CLK_ENB 20
#define SPEAR1340_I2S_REC_CLK_ENB 19
#define SPEAR1340_I2C0_CLK_ENB 18
#define SPEAR1340_SSP_CLK_ENB 17
#define SPEAR1340_UART0_CLK_ENB 15
#define SPEAR1340_PCIE_SATA_CLK_ENB 12
#define SPEAR1340_UOC_CLK_ENB 11
#define SPEAR1340_UHC1_CLK_ENB 10
#define SPEAR1340_UHC0_CLK_ENB 9
#define SPEAR1340_GMAC_CLK_ENB 8
#define SPEAR1340_CFXD_CLK_ENB 7
#define SPEAR1340_SDHCI_CLK_ENB 6
#define SPEAR1340_SMI_CLK_ENB 5
#define SPEAR1340_FSMC_CLK_ENB 4
#define SPEAR1340_SYSRAM0_CLK_ENB 3
#define SPEAR1340_SYSRAM1_CLK_ENB 2
#define SPEAR1340_SYSROM_CLK_ENB 1
#define SPEAR1340_BUS_CLK_ENB 0
#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
#define SPEAR1340_THSENS_CLK_ENB 8
#define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
#define SPEAR1340_ACP_CLK_ENB 6
#define SPEAR1340_GPT3_CLK_ENB 5
#define SPEAR1340_GPT2_CLK_ENB 4
#define SPEAR1340_KBD_CLK_ENB 3
#define SPEAR1340_CPU_DBG_CLK_ENB 2
#define SPEAR1340_DDR_CORE_CLK_ENB 1
#define SPEAR1340_DDR_CTRL_CLK_ENB 0
#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
#define SPEAR1340_PLGPIO_CLK_ENB 18
#define SPEAR1340_VIDEO_DEC_CLK_ENB 16
#define SPEAR1340_VIDEO_ENC_CLK_ENB 15
#define SPEAR1340_SPDIF_OUT_CLK_ENB 13
#define SPEAR1340_SPDIF_IN_CLK_ENB 12
#define SPEAR1340_VIDEO_IN_CLK_ENB 11
#define SPEAR1340_CAM0_CLK_ENB 10
#define SPEAR1340_CAM1_CLK_ENB 9
#define SPEAR1340_CAM2_CLK_ENB 8
#define SPEAR1340_CAM3_CLK_ENB 7
#define SPEAR1340_MALI_CLK_ENB 6
#define SPEAR1340_CEC0_CLK_ENB 5
#define SPEAR1340_CEC1_CLK_ENB 4
#define SPEAR1340_PWM_CLK_ENB 3
#define SPEAR1340_I2C1_CLK_ENB 2
#define SPEAR1340_UART1_CLK_ENB 1
static DEFINE_SPINLOCK(_lock);
/* pll rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll_rtbl[] = {
/* PCLK 24MHz */
{.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
{.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
{.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
};
/* vco-pll4 rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll4_rtbl[] = {
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
};
/*
* All below entries generate 166 MHz for
* different values of vco1div2
*/
static struct frac_rate_tbl amba_synth_rtbl[] = {
{.div = 0x06062}, /* for vco1div2 = 500 MHz */
{.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
{.div = 0x04000}, /* for vco1div2 = 332 MHz */
{.div = 0x03031}, /* for vco1div2 = 250 MHz */
{.div = 0x0268D}, /* for vco1div2 = 200 MHz */
};
/*
* Synthesizer Clock derived from vcodiv2. This clock is one of the
* possible clocks to feed cpu directly.
* We can program this synthesizer to make cpu run on different clock
* frequencies.
* Following table provides configuration values to let cpu run on 200,
* 250, 332, 400 or 500 MHz considering different possibilites of input
* (vco1div2) clock.
*
* --------------------------------------------------------------------
* vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
* --------------------------------------------------------------------
* 400 200 100 0x04000
* 400 250 125 0x03333
* 400 332 166 0x0268D
* 400 400 200 0x02000
* --------------------------------------------------------------------
* 500 200 100 0x05000
* 500 250 125 0x04000
* 500 332 166 0x03031
* 500 400 200 0x02800
* 500 500 250 0x02000
* --------------------------------------------------------------------
* 664 200 100 0x06a38
* 664 250 125 0x054FD
* 664 332 166 0x04000
* 664 400 200 0x0351E
* 664 500 250 0x02A7E
* --------------------------------------------------------------------
* 800 200 100 0x08000
* 800 250 125 0x06666
* 800 332 166 0x04D18
* 800 400 200 0x04000
* 800 500 250 0x03333
* --------------------------------------------------------------------
* sys rate configuration table is in descending order of divisor.
*/
static struct frac_rate_tbl sys_synth_rtbl[] = {
{.div = 0x08000},
{.div = 0x06a38},
{.div = 0x06666},
{.div = 0x054FD},
{.div = 0x05000},
{.div = 0x04D18},
{.div = 0x04000},
{.div = 0x0351E},
{.div = 0x03333},
{.div = 0x03031},
{.div = 0x02A7E},
{.div = 0x02800},
{.div = 0x0268D},
{.div = 0x02000},
};
/* aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl aux_rtbl[] = {
/* For VCO1div2 = 500 MHz */
{.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
{.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
{.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
{.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
{.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
{.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
};
/* gmac rate configuration table, in ascending order of rates */
static struct aux_rate_tbl gmac_rtbl[] = {
/* For gmac phy input clk */
{.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
{.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
{.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
{.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
};
/* clcd rate configuration table, in ascending order of rates */
static struct frac_rate_tbl clcd_rtbl[] = {
{.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
{.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
{.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
{.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
{.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
};
/* i2s prescaler1 masks */
static struct aux_clk_masks i2s_prs1_masks = {
.eq_sel_mask = AUX_EQ_SEL_MASK,
.eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
.eq1_mask = AUX_EQ1_SEL,
.eq2_mask = AUX_EQ2_SEL,
.xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
.xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
.yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
.yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
};
/* i2s sclk (bit clock) syynthesizers masks */
static struct aux_clk_masks i2s_sclk_masks = {
.eq_sel_mask = AUX_EQ_SEL_MASK,
.eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
.eq1_mask = AUX_EQ1_SEL,
.eq2_mask = AUX_EQ2_SEL,
.xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
.xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
.yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
.yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
.enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
};
/* i2s prs1 aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl i2s_prs1_rtbl[] = {
/* For parent clk = 49.152 MHz */
{.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
{.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
{.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
{.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
/*
* with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
* with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
*/
{.xscale = 1, .yscale = 3, .eq = 0},
/* For parent clk = 49.152 MHz */
{.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
};
/* i2s sclk aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl i2s_sclk_rtbl[] = {
/* For sclk = ref_clk * x/2/y */
{.xscale = 1, .yscale = 4, .eq = 0},
{.xscale = 1, .yscale = 2, .eq = 0},
};
/* adc rate configuration table, in ascending order of rates */
/* possible adc range is 2.5 MHz to 20 MHz. */
static struct aux_rate_tbl adc_rtbl[] = {
/* For ahb = 166.67 MHz */
{.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
{.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
{.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
};
/* General synth rate configuration table, in ascending order of rates */
static struct frac_rate_tbl gen_rtbl[] = {
/* For vco1div4 = 250 MHz */
{.div = 0x1624E}, /* 22.5792 MHz */
{.div = 0x14585}, /* 24.576 MHz */
{.div = 0x14000}, /* 25 MHz */
{.div = 0x0B127}, /* 45.1584 MHz */
{.div = 0x0A000}, /* 50 MHz */
{.div = 0x061A8}, /* 81.92 MHz */
{.div = 0x05000}, /* 100 MHz */
{.div = 0x02800}, /* 200 MHz */
{.div = 0x02620}, /* 210 MHz */
{.div = 0x02460}, /* 220 MHz */
{.div = 0x022C0}, /* 230 MHz */
{.div = 0x02160}, /* 240 MHz */
{.div = 0x02000}, /* 250 MHz */
};
/* clock parents */
static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
"sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
"uart0_synth_gate_clk", };
static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
"uart1_synth_gate_clk", };
static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
"osc_25m_clk", };
static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
"gmac_phy_synth_gate_clk", };
static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
"i2s_src_pad_clk", };
static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk",
};
static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
"pll3_clk", };
static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
"pll2_clk", };
void __init spear1340_clk_init(void)
{
struct clk *clk, *clk1;
clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
clk_register_clkdev(clk, "apb_pclk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
32000);
clk_register_clkdev(clk, "osc_32k_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
24000000);
clk_register_clkdev(clk, "osc_24m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
25000000);
clk_register_clkdev(clk, "osc_25m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
CLK_IS_ROOT, 125000000);
clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
CLK_IS_ROOT, 12288000);
clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
/* clock derived from 32 KHz osc clk */
clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "fc900000.rtc");
/* clock derived from 24 or 25 MHz osc clk */
/* vco-pll */
clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "vco1_mux_clk", NULL);
clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco1_clk", NULL);
clk_register_clkdev(clk1, "pll1_clk", NULL);
clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "vco2_mux_clk", NULL);
clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco2_clk", NULL);
clk_register_clkdev(clk1, "pll2_clk", NULL);
clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "vco3_mux_clk", NULL);
clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco3_clk", NULL);
clk_register_clkdev(clk1, "pll3_clk", NULL);
clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco4_clk", NULL);
clk_register_clkdev(clk1, "pll4_clk", NULL);
clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
48000000);
clk_register_clkdev(clk, "pll5_clk", NULL);
clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
25000000);
clk_register_clkdev(clk, "pll6_clk", NULL);
/* vco div n clocks */
clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
2);
clk_register_clkdev(clk, "vco1div2_clk", NULL);
clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
4);
clk_register_clkdev(clk, "vco1div4_clk", NULL);
clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
2);
clk_register_clkdev(clk, "vco2div2_clk", NULL);
clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
2);
clk_register_clkdev(clk, "vco3div2_clk", NULL);
/* peripherals */
clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
128);
clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_thermal");
/* clock derived from pll4 clk */
clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
1);
clk_register_clkdev(clk, "ddr_clk", NULL);
/* clock derived from pll1 clk */
clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0,
SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
ARRAY_SIZE(sys_synth_rtbl), &_lock);
clk_register_clkdev(clk, "sys_synth_clk", NULL);
clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0,
SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
ARRAY_SIZE(amba_synth_rtbl), &_lock);
clk_register_clkdev(clk, "amba_synth_clk", NULL);
clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents,
ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
SPEAR1340_SCLK_SRC_SEL_SHIFT,
SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
clk_register_clkdev(clk, "sys_clk", NULL);
clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1,
2);
clk_register_clkdev(clk, "cpu_clk", NULL);
clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
3);
clk_register_clkdev(clk, "cpu_div3_clk", NULL);
clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
2);
clk_register_clkdev(clk, NULL, "ec800620.wdt");
clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
SPEAR1340_HCLK_SRC_SEL_SHIFT,
SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
clk_register_clkdev(clk, "ahb_clk", NULL);
clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
2);
clk_register_clkdev(clk, "apb_clk", NULL);
/* gpt clocks */
clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt0");
clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt1");
clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt2");
clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "gpt3");
/* others */
clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "uart0_synth_clk", NULL);
clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "uart0_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0000000.serial");
clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "uart1_synth_clk", NULL);
clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents,
ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "uart1_mux_clk", NULL);
clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b4100000.serial");
clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b3000000.sdhci");
clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b2800000.cf");
clk_register_clkdev(clk, NULL, "arasan_xd");
clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
"vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL,
aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "c3_synth_clk", NULL);
clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
&_lock);
clk_register_clkdev(clk, "c3_mux_clk", NULL);
clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "c3");
/* gmac */
clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
gmac_phy_input_parents,
ARRAY_SIZE(gmac_phy_input_parents), 0,
SPEAR1340_GMAC_CLK_CFG,
SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
"gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT,
NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
ARRAY_SIZE(gmac_phy_parents), 0,
SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, NULL, "stmmacphy.0");
/* clcd */
clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
ARRAY_SIZE(clcd_synth_parents), 0,
SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
ARRAY_SIZE(clcd_rtbl), &_lock);
clk_register_clkdev(clk, "clcd_synth_clk", NULL);
clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
ARRAY_SIZE(clcd_pixel_parents), 0,
SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "clcd_clk", NULL);
/* i2s */
clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
0, &_lock);
clk_register_clkdev(clk, "i2s_src_clk", NULL);
clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
&_lock);
clk_register_clkdev(clk, "i2s_ref_clk", NULL);
clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
"i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG,
&i2s_sclk_masks, i2s_sclk_rtbl,
ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
/* clock derived from ahb clk */
clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0280000.i2c");
clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b4000000.i2c");
clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "ea800000.dma");
clk_register_clkdev(clk, NULL, "eb000000.dma");
clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e2000000.eth");
clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b0000000.flash");
clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "ea000000.flash");
clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "usbh.0_clk", NULL);
clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "usbh.1_clk", NULL);
clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "uoc");
clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "dw_pcie");
clk_register_clkdev(clk, NULL, "ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "sysram0_clk", NULL);
clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, "sysram1_clk", NULL);
clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
clk_register_clkdev(clk, "adc_synth_clk", NULL);
clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "adc_clk");
/* clock derived from apb clk */
clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0100000.spi");
clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0600000.gpio");
clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0680000.gpio");
clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b2400000.i2s");
clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "b2000000.i2s");
clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e0300000.kbd");
/* RAS clks */
clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth0_clk", NULL);
clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth1_clk", NULL);
clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth2_clk", NULL);
clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
&_lock);
clk_register_clkdev(clk, "gen_synth3_clk", NULL);
clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "mali");
clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_cec.0");
clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_cec.1");
clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents,
ARRAY_SIZE(spdif_out_parents), 0,
SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "spdif_out_mux_clk", NULL);
clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "spdif-out");
clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents,
ARRAY_SIZE(spdif_in_parents), 0,
SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "spdif_in_mux_clk", NULL);
clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spdif-in");
clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "acp_clk");
clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "plgpio");
clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "video_dec");
clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "video_enc");
clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_vip");
clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_camif.0");
clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_camif.1");
clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_camif.2");
clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_camif.3");
clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "pwm");
}
drivers/gpio/gpio-samsung.c
View file @ 30b84288
......@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
.ngpio = EXYNOS5_GPIO_C3_NR,
.label = "GPC3",
},
}, {
.chip = {
.base = EXYNOS5_GPC4(0),
.ngpio = EXYNOS5_GPIO_C4_NR,
.label = "GPC4",
},
}, {
.chip = {
.base = EXYNOS5_GPD0(0),
......@@ -2826,8 +2832,11 @@ static __init void exynos5_gpiolib_init(void)
goto err_ioremap1;
}
/* need to set base address for gpc4 */
exonys5_gpios_1[11].base = gpio_base1 + 0x2E0;
/* need to set base address for gpx */
chip = &exynos5_gpios_1[20];
chip = &exynos5_gpios_1[21];
gpx_base = gpio_base1 + 0xC00;
for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
chip->base = gpx_base;
......
drivers/pinctrl/spear/Kconfig
View file @ 30b84288
......@@ -31,4 +31,14 @@ config PINCTRL_SPEAR320
depends on MACH_SPEAR320
select PINCTRL_SPEAR3XX
config PINCTRL_SPEAR1310
bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
depends on MACH_SPEAR1310
select PINCTRL_SPEAR
config PINCTRL_SPEAR1340
bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
depends on MACH_SPEAR1340
select PINCTRL_SPEAR
endif
drivers/pinctrl/spear/Makefile
View file @ 30b84288
......@@ -5,3 +5,5 @@ obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
obj-$(CONFIG_PINCTRL_SPEAR1310) += pinctrl-spear1310.o
obj-$(CONFIG_PINCTRL_SPEAR1340) += pinctrl-spear1340.o
drivers/pinctrl/spear/pinctrl-spear.h
View file @ 30b84288
......@@ -139,4 +139,255 @@ void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
int __devinit spear_pinctrl_probe(struct platform_device *pdev,
struct spear_pinctrl_machdata *machdata);
int __devexit spear_pinctrl_remove(struct platform_device *pdev);
#define SPEAR_PIN_0_TO_101 \
PINCTRL_PIN(0, "PLGPIO0"), \
PINCTRL_PIN(1, "PLGPIO1"), \
PINCTRL_PIN(2, "PLGPIO2"), \
PINCTRL_PIN(3, "PLGPIO3"), \
PINCTRL_PIN(4, "PLGPIO4"), \
PINCTRL_PIN(5, "PLGPIO5"), \
PINCTRL_PIN(6, "PLGPIO6"), \
PINCTRL_PIN(7, "PLGPIO7"), \
PINCTRL_PIN(8, "PLGPIO8"), \
PINCTRL_PIN(9, "PLGPIO9"), \
PINCTRL_PIN(10, "PLGPIO10"), \
PINCTRL_PIN(11, "PLGPIO11"), \
PINCTRL_PIN(12, "PLGPIO12"), \
PINCTRL_PIN(13, "PLGPIO13"), \
PINCTRL_PIN(14, "PLGPIO14"), \
PINCTRL_PIN(15, "PLGPIO15"), \
PINCTRL_PIN(16, "PLGPIO16"), \
PINCTRL_PIN(17, "PLGPIO17"), \
PINCTRL_PIN(18, "PLGPIO18"), \
PINCTRL_PIN(19, "PLGPIO19"), \
PINCTRL_PIN(20, "PLGPIO20"), \
PINCTRL_PIN(21, "PLGPIO21"), \
PINCTRL_PIN(22, "PLGPIO22"), \
PINCTRL_PIN(23, "PLGPIO23"), \
PINCTRL_PIN(24, "PLGPIO24"), \
PINCTRL_PIN(25, "PLGPIO25"), \
PINCTRL_PIN(26, "PLGPIO26"), \
PINCTRL_PIN(27, "PLGPIO27"), \
PINCTRL_PIN(28, "PLGPIO28"), \
PINCTRL_PIN(29, "PLGPIO29"), \
PINCTRL_PIN(30, "PLGPIO30"), \
PINCTRL_PIN(31, "PLGPIO31"), \
PINCTRL_PIN(32, "PLGPIO32"), \
PINCTRL_PIN(33, "PLGPIO33"), \
PINCTRL_PIN(34, "PLGPIO34"), \
PINCTRL_PIN(35, "PLGPIO35"), \
PINCTRL_PIN(36, "PLGPIO36"), \
PINCTRL_PIN(37, "PLGPIO37"), \
PINCTRL_PIN(38, "PLGPIO38"), \
PINCTRL_PIN(39, "PLGPIO39"), \
PINCTRL_PIN(40, "PLGPIO40"), \
PINCTRL_PIN(41, "PLGPIO41"), \
PINCTRL_PIN(42, "PLGPIO42"), \
PINCTRL_PIN(43, "PLGPIO43"), \
PINCTRL_PIN(44, "PLGPIO44"), \
PINCTRL_PIN(45, "PLGPIO45"), \
PINCTRL_PIN(46, "PLGPIO46"), \
PINCTRL_PIN(47, "PLGPIO47"), \
PINCTRL_PIN(48, "PLGPIO48"), \
PINCTRL_PIN(49, "PLGPIO49"), \
PINCTRL_PIN(50, "PLGPIO50"), \
PINCTRL_PIN(51, "PLGPIO51"), \
PINCTRL_PIN(52, "PLGPIO52"), \
PINCTRL_PIN(53, "PLGPIO53"), \
PINCTRL_PIN(54, "PLGPIO54"), \
PINCTRL_PIN(55, "PLGPIO55"), \
PINCTRL_PIN(56, "PLGPIO56"), \
PINCTRL_PIN(57, "PLGPIO57"), \
PINCTRL_PIN(58, "PLGPIO58"), \
PINCTRL_PIN(59, "PLGPIO59"), \
PINCTRL_PIN(60, "PLGPIO60"), \
PINCTRL_PIN(61, "PLGPIO61"), \
PINCTRL_PIN(62, "PLGPIO62"), \
PINCTRL_PIN(63, "PLGPIO63"), \
PINCTRL_PIN(64, "PLGPIO64"), \
PINCTRL_PIN(65, "PLGPIO65"), \
PINCTRL_PIN(66, "PLGPIO66"), \
PINCTRL_PIN(67, "PLGPIO67"), \
PINCTRL_PIN(68, "PLGPIO68"), \
PINCTRL_PIN(69, "PLGPIO69"), \
PINCTRL_PIN(70, "PLGPIO70"), \
PINCTRL_PIN(71, "PLGPIO71"), \
PINCTRL_PIN(72, "PLGPIO72"), \
PINCTRL_PIN(73, "PLGPIO73"), \
PINCTRL_PIN(74, "PLGPIO74"), \
PINCTRL_PIN(75, "PLGPIO75"), \
PINCTRL_PIN(76, "PLGPIO76"), \
PINCTRL_PIN(77, "PLGPIO77"), \
PINCTRL_PIN(78, "PLGPIO78"), \
PINCTRL_PIN(79, "PLGPIO79"), \
PINCTRL_PIN(80, "PLGPIO80"), \
PINCTRL_PIN(81, "PLGPIO81"), \
PINCTRL_PIN(82, "PLGPIO82"), \
PINCTRL_PIN(83, "PLGPIO83"), \
PINCTRL_PIN(84, "PLGPIO84"), \
PINCTRL_PIN(85, "PLGPIO85"), \
PINCTRL_PIN(86, "PLGPIO86"), \
PINCTRL_PIN(87, "PLGPIO87"), \
PINCTRL_PIN(88, "PLGPIO88"), \
PINCTRL_PIN(89, "PLGPIO89"), \
PINCTRL_PIN(90, "PLGPIO90"), \
PINCTRL_PIN(91, "PLGPIO91"), \
PINCTRL_PIN(92, "PLGPIO92"), \
PINCTRL_PIN(93, "PLGPIO93"), \
PINCTRL_PIN(94, "PLGPIO94"), \
PINCTRL_PIN(95, "PLGPIO95"), \
PINCTRL_PIN(96, "PLGPIO96"), \
PINCTRL_PIN(97, "PLGPIO97"), \
PINCTRL_PIN(98, "PLGPIO98"), \
PINCTRL_PIN(99, "PLGPIO99"), \
PINCTRL_PIN(100, "PLGPIO100"), \
PINCTRL_PIN(101, "PLGPIO101")
#define SPEAR_PIN_102_TO_245 \
PINCTRL_PIN(102, "PLGPIO102"), \
PINCTRL_PIN(103, "PLGPIO103"), \
PINCTRL_PIN(104, "PLGPIO104"), \
PINCTRL_PIN(105, "PLGPIO105"), \
PINCTRL_PIN(106, "PLGPIO106"), \
PINCTRL_PIN(107, "PLGPIO107"), \
PINCTRL_PIN(108, "PLGPIO108"), \
PINCTRL_PIN(109, "PLGPIO109"), \
PINCTRL_PIN(110, "PLGPIO110"), \
PINCTRL_PIN(111, "PLGPIO111"), \
PINCTRL_PIN(112, "PLGPIO112"), \
PINCTRL_PIN(113, "PLGPIO113"), \
PINCTRL_PIN(114, "PLGPIO114"), \
PINCTRL_PIN(115, "PLGPIO115"), \
PINCTRL_PIN(116, "PLGPIO116"), \
PINCTRL_PIN(117, "PLGPIO117"), \
PINCTRL_PIN(118, "PLGPIO118"), \
PINCTRL_PIN(119, "PLGPIO119"), \
PINCTRL_PIN(120, "PLGPIO120"), \
PINCTRL_PIN(121, "PLGPIO121"), \
PINCTRL_PIN(122, "PLGPIO122"), \
PINCTRL_PIN(123, "PLGPIO123"), \
PINCTRL_PIN(124, "PLGPIO124"), \
PINCTRL_PIN(125, "PLGPIO125"), \
PINCTRL_PIN(126, "PLGPIO126"), \
PINCTRL_PIN(127, "PLGPIO127"), \
PINCTRL_PIN(128, "PLGPIO128"), \
PINCTRL_PIN(129, "PLGPIO129"), \
PINCTRL_PIN(130, "PLGPIO130"), \
PINCTRL_PIN(131, "PLGPIO131"), \
PINCTRL_PIN(132, "PLGPIO132"), \
PINCTRL_PIN(133, "PLGPIO133"), \
PINCTRL_PIN(134, "PLGPIO134"), \
PINCTRL_PIN(135, "PLGPIO135"), \
PINCTRL_PIN(136, "PLGPIO136"), \
PINCTRL_PIN(137, "PLGPIO137"), \
PINCTRL_PIN(138, "PLGPIO138"), \
PINCTRL_PIN(139, "PLGPIO139"), \
PINCTRL_PIN(140, "PLGPIO140"), \
PINCTRL_PIN(141, "PLGPIO141"), \
PINCTRL_PIN(142, "PLGPIO142"), \
PINCTRL_PIN(143, "PLGPIO143"), \
PINCTRL_PIN(144, "PLGPIO144"), \
PINCTRL_PIN(145, "PLGPIO145"), \
PINCTRL_PIN(146, "PLGPIO146"), \
PINCTRL_PIN(147, "PLGPIO147"), \
PINCTRL_PIN(148, "PLGPIO148"), \
PINCTRL_PIN(149, "PLGPIO149"), \
PINCTRL_PIN(150, "PLGPIO150"), \
PINCTRL_PIN(151, "PLGPIO151"), \
PINCTRL_PIN(152, "PLGPIO152"), \
PINCTRL_PIN(153, "PLGPIO153"), \
PINCTRL_PIN(154, "PLGPIO154"), \
PINCTRL_PIN(155, "PLGPIO155"), \
PINCTRL_PIN(156, "PLGPIO156"), \
PINCTRL_PIN(157, "PLGPIO157"), \
PINCTRL_PIN(158, "PLGPIO158"), \
PINCTRL_PIN(159, "PLGPIO159"), \
PINCTRL_PIN(160, "PLGPIO160"), \
PINCTRL_PIN(161, "PLGPIO161"), \
PINCTRL_PIN(162, "PLGPIO162"), \
PINCTRL_PIN(163, "PLGPIO163"), \
PINCTRL_PIN(164, "PLGPIO164"), \
PINCTRL_PIN(165, "PLGPIO165"), \
PINCTRL_PIN(166, "PLGPIO166"), \
PINCTRL_PIN(167, "PLGPIO167"), \
PINCTRL_PIN(168, "PLGPIO168"), \
PINCTRL_PIN(169, "PLGPIO169"), \
PINCTRL_PIN(170, "PLGPIO170"), \
PINCTRL_PIN(171, "PLGPIO171"), \
PINCTRL_PIN(172, "PLGPIO172"), \
PINCTRL_PIN(173, "PLGPIO173"), \
PINCTRL_PIN(174, "PLGPIO174"), \
PINCTRL_PIN(175, "PLGPIO175"), \
PINCTRL_PIN(176, "PLGPIO176"), \
PINCTRL_PIN(177, "PLGPIO177"), \
PINCTRL_PIN(178, "PLGPIO178"), \
PINCTRL_PIN(179, "PLGPIO179"), \
PINCTRL_PIN(180, "PLGPIO180"), \
PINCTRL_PIN(181, "PLGPIO181"), \
PINCTRL_PIN(182, "PLGPIO182"), \
PINCTRL_PIN(183, "PLGPIO183"), \
PINCTRL_PIN(184, "PLGPIO184"), \
PINCTRL_PIN(185, "PLGPIO185"), \
PINCTRL_PIN(186, "PLGPIO186"), \
PINCTRL_PIN(187, "PLGPIO187"), \
PINCTRL_PIN(188, "PLGPIO188"), \
PINCTRL_PIN(189, "PLGPIO189"), \
PINCTRL_PIN(190, "PLGPIO190"), \
PINCTRL_PIN(191, "PLGPIO191"), \
PINCTRL_PIN(192, "PLGPIO192"), \
PINCTRL_PIN(193, "PLGPIO193"), \
PINCTRL_PIN(194, "PLGPIO194"), \
PINCTRL_PIN(195, "PLGPIO195"), \
PINCTRL_PIN(196, "PLGPIO196"), \
PINCTRL_PIN(197, "PLGPIO197"), \
PINCTRL_PIN(198, "PLGPIO198"), \
PINCTRL_PIN(199, "PLGPIO199"), \
PINCTRL_PIN(200, "PLGPIO200"), \
PINCTRL_PIN(201, "PLGPIO201"), \
PINCTRL_PIN(202, "PLGPIO202"), \
PINCTRL_PIN(203, "PLGPIO203"), \
PINCTRL_PIN(204, "PLGPIO204"), \
PINCTRL_PIN(205, "PLGPIO205"), \
PINCTRL_PIN(206, "PLGPIO206"), \
PINCTRL_PIN(207, "PLGPIO207"), \
PINCTRL_PIN(208, "PLGPIO208"), \
PINCTRL_PIN(209, "PLGPIO209"), \
PINCTRL_PIN(210, "PLGPIO210"), \
PINCTRL_PIN(211, "PLGPIO211"), \
PINCTRL_PIN(212, "PLGPIO212"), \
PINCTRL_PIN(213, "PLGPIO213"), \
PINCTRL_PIN(214, "PLGPIO214"), \
PINCTRL_PIN(215, "PLGPIO215"), \
PINCTRL_PIN(216, "PLGPIO216"), \
PINCTRL_PIN(217, "PLGPIO217"), \
PINCTRL_PIN(218, "PLGPIO218"), \
PINCTRL_PIN(219, "PLGPIO219"), \
PINCTRL_PIN(220, "PLGPIO220"), \
PINCTRL_PIN(221, "PLGPIO221"), \
PINCTRL_PIN(222, "PLGPIO222"), \
PINCTRL_PIN(223, "PLGPIO223"), \
PINCTRL_PIN(224, "PLGPIO224"), \
PINCTRL_PIN(225, "PLGPIO225"), \
PINCTRL_PIN(226, "PLGPIO226"), \
PINCTRL_PIN(227, "PLGPIO227"), \
PINCTRL_PIN(228, "PLGPIO228"), \
PINCTRL_PIN(229, "PLGPIO229"), \
PINCTRL_PIN(230, "PLGPIO230"), \
PINCTRL_PIN(231, "PLGPIO231"), \
PINCTRL_PIN(232, "PLGPIO232"), \
PINCTRL_PIN(233, "PLGPIO233"), \
PINCTRL_PIN(234, "PLGPIO234"), \
PINCTRL_PIN(235, "PLGPIO235"), \
PINCTRL_PIN(236, "PLGPIO236"), \
PINCTRL_PIN(237, "PLGPIO237"), \
PINCTRL_PIN(238, "PLGPIO238"), \
PINCTRL_PIN(239, "PLGPIO239"), \
PINCTRL_PIN(240, "PLGPIO240"), \
PINCTRL_PIN(241, "PLGPIO241"), \
PINCTRL_PIN(242, "PLGPIO242"), \
PINCTRL_PIN(243, "PLGPIO243"), \
PINCTRL_PIN(244, "PLGPIO244"), \
PINCTRL_PIN(245, "PLGPIO245")
#endif /* __PINMUX_SPEAR_H__ */
drivers/pinctrl/spear/pinctrl-spear1310.c 0 → 100644
View file @ 30b84288
/*
* Driver for the ST Microelectronics SPEAr1310 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear1310-pinmux"
/* pins */
static const struct pinctrl_pin_desc spear1310_pins[] = {
SPEAR_PIN_0_TO_101,
SPEAR_PIN_102_TO_245,
};
/* registers */
#define PERIP_CFG 0x32C
#define MCIF_SEL_SHIFT 3
#define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
#define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
#define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
#define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
#define PCIE_SATA_CFG 0x3A4
#define PCIE_SATA2_SEL_PCIE (0 << 31)
#define PCIE_SATA1_SEL_PCIE (0 << 30)
#define PCIE_SATA0_SEL_PCIE (0 << 29)
#define PCIE_SATA2_SEL_SATA (1 << 31)
#define PCIE_SATA1_SEL_SATA (1 << 30)
#define PCIE_SATA0_SEL_SATA (1 << 29)
#define SATA2_CFG_TX_CLK_EN (1 << 27)
#define SATA2_CFG_RX_CLK_EN (1 << 26)
#define SATA2_CFG_POWERUP_RESET (1 << 25)
#define SATA2_CFG_PM_CLK_EN (1 << 24)
#define SATA1_CFG_TX_CLK_EN (1 << 23)
#define SATA1_CFG_RX_CLK_EN (1 << 22)
#define SATA1_CFG_POWERUP_RESET (1 << 21)
#define SATA1_CFG_PM_CLK_EN (1 << 20)
#define SATA0_CFG_TX_CLK_EN (1 << 19)
#define SATA0_CFG_RX_CLK_EN (1 << 18)
#define SATA0_CFG_POWERUP_RESET (1 << 17)
#define SATA0_CFG_PM_CLK_EN (1 << 16)
#define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
#define PCIE2_CFG_POWERUP_RESET (1 << 10)
#define PCIE2_CFG_CORE_CLK_EN (1 << 9)
#define PCIE2_CFG_AUX_CLK_EN (1 << 8)
#define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
#define PCIE1_CFG_POWERUP_RESET (1 << 6)
#define PCIE1_CFG_CORE_CLK_EN (1 << 5)
#define PCIE1_CFG_AUX_CLK_EN (1 << 4)
#define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
#define PCIE0_CFG_POWERUP_RESET (1 << 2)
#define PCIE0_CFG_CORE_CLK_EN (1 << 1)
#define PCIE0_CFG_AUX_CLK_EN (1 << 0)
#define PAD_FUNCTION_EN_0 0x650
#define PMX_UART0_MASK (1 << 1)
#define PMX_I2C0_MASK (1 << 2)
#define PMX_I2S0_MASK (1 << 3)
#define PMX_SSP0_MASK (1 << 4)
#define PMX_CLCD1_MASK (1 << 5)
#define PMX_EGPIO00_MASK (1 << 6)
#define PMX_EGPIO01_MASK (1 << 7)
#define PMX_EGPIO02_MASK (1 << 8)
#define PMX_EGPIO03_MASK (1 << 9)
#define PMX_EGPIO04_MASK (1 << 10)
#define PMX_EGPIO05_MASK (1 << 11)
#define PMX_EGPIO06_MASK (1 << 12)
#define PMX_EGPIO07_MASK (1 << 13)
#define PMX_EGPIO08_MASK (1 << 14)
#define PMX_EGPIO09_MASK (1 << 15)
#define PMX_SMI_MASK (1 << 16)
#define PMX_NAND8_MASK (1 << 17)
#define PMX_GMIICLK_MASK (1 << 18)
#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
#define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
#define PMX_GMIID47_MASK (1 << 21)
#define PMX_MDC_MDIO_MASK (1 << 22)
#define PMX_MCI_DATA8_15_MASK (1 << 23)
#define PMX_NFAD23_MASK (1 << 24)
#define PMX_NFAD24_MASK (1 << 25)
#define PMX_NFAD25_MASK (1 << 26)
#define PMX_NFCE3_MASK (1 << 27)
#define PMX_NFWPRT3_MASK (1 << 28)
#define PMX_NFRSTPWDWN0_MASK (1 << 29)
#define PMX_NFRSTPWDWN1_MASK (1 << 30)
#define PMX_NFRSTPWDWN2_MASK (1 << 31)
#define PAD_FUNCTION_EN_1 0x654
#define PMX_NFRSTPWDWN3_MASK (1 << 0)
#define PMX_SMINCS2_MASK (1 << 1)
#define PMX_SMINCS3_MASK (1 << 2)
#define PMX_CLCD2_MASK (1 << 3)
#define PMX_KBD_ROWCOL68_MASK (1 << 4)
#define PMX_EGPIO10_MASK (1 << 5)
#define PMX_EGPIO11_MASK (1 << 6)
#define PMX_EGPIO12_MASK (1 << 7)
#define PMX_EGPIO13_MASK (1 << 8)
#define PMX_EGPIO14_MASK (1 << 9)
#define PMX_EGPIO15_MASK (1 << 10)
#define PMX_UART0_MODEM_MASK (1 << 11)
#define PMX_GPT0_TMR0_MASK (1 << 12)
#define PMX_GPT0_TMR1_MASK (1 << 13)
#define PMX_GPT1_TMR0_MASK (1 << 14)
#define PMX_GPT1_TMR1_MASK (1 << 15)
#define PMX_I2S1_MASK (1 << 16)
#define PMX_KBD_ROWCOL25_MASK (1 << 17)
#define PMX_NFIO8_15_MASK (1 << 18)
#define PMX_KBD_COL1_MASK (1 << 19)
#define PMX_NFCE1_MASK (1 << 20)
#define PMX_KBD_COL0_MASK (1 << 21)
#define PMX_NFCE2_MASK (1 << 22)
#define PMX_KBD_ROW1_MASK (1 << 23)
#define PMX_NFWPRT1_MASK (1 << 24)
#define PMX_KBD_ROW0_MASK (1 << 25)
#define PMX_NFWPRT2_MASK (1 << 26)
#define PMX_MCIDATA0_MASK (1 << 27)
#define PMX_MCIDATA1_MASK (1 << 28)
#define PMX_MCIDATA2_MASK (1 << 29)
#define PMX_MCIDATA3_MASK (1 << 30)
#define PMX_MCIDATA4_MASK (1 << 31)
#define PAD_FUNCTION_EN_2 0x658
#define PMX_MCIDATA5_MASK (1 << 0)
#define PMX_MCIDATA6_MASK (1 << 1)
#define PMX_MCIDATA7_MASK (1 << 2)
#define PMX_MCIDATA1SD_MASK (1 << 3)
#define PMX_MCIDATA2SD_MASK (1 << 4)
#define PMX_MCIDATA3SD_MASK (1 << 5)
#define PMX_MCIADDR0ALE_MASK (1 << 6)
#define PMX_MCIADDR1CLECLK_MASK (1 << 7)
#define PMX_MCIADDR2_MASK (1 << 8)
#define PMX_MCICECF_MASK (1 << 9)
#define PMX_MCICEXD_MASK (1 << 10)
#define PMX_MCICESDMMC_MASK (1 << 11)
#define PMX_MCICDCF1_MASK (1 << 12)
#define PMX_MCICDCF2_MASK (1 << 13)
#define PMX_MCICDXD_MASK (1 << 14)
#define PMX_MCICDSDMMC_MASK (1 << 15)
#define PMX_MCIDATADIR_MASK (1 << 16)
#define PMX_MCIDMARQWP_MASK (1 << 17)
#define PMX_MCIIORDRE_MASK (1 << 18)
#define PMX_MCIIOWRWE_MASK (1 << 19)
#define PMX_MCIRESETCF_MASK (1 << 20)
#define PMX_MCICS0CE_MASK (1 << 21)
#define PMX_MCICFINTR_MASK (1 << 22)
#define PMX_MCIIORDY_MASK (1 << 23)
#define PMX_MCICS1_MASK (1 << 24)
#define PMX_MCIDMAACK_MASK (1 << 25)
#define PMX_MCISDCMD_MASK (1 << 26)
#define PMX_MCILEDS_MASK (1 << 27)
#define PMX_TOUCH_XY_MASK (1 << 28)
#define PMX_SSP0_CS0_MASK (1 << 29)
#define PMX_SSP0_CS1_2_MASK (1 << 30)
/* combined macros */
#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
PMX_RXCLK_RDV_TXEN_D03_MASK | \
PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
PMX_EGPIO02_MASK | \
PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
PMX_EGPIO09_MASK)
#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
PMX_KBD_COL1_MASK)
#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
PMX_NFCE3_MASK)
#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
#define PMX_MCIFALL_1_MASK 0xF8000000
#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
PMX_NFCE2_MASK)
#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
PMX_SSP0_CS1_2_MASK)
#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
PMX_GMIID47_MASK)
#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
PMX_SSP0_CS1_2_MASK)
#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
PCIE##x##_CFG_AUX_CLK_EN | \
PCIE##x##_CFG_CORE_CLK_EN | \
PCIE##x##_CFG_POWERUP_RESET | \
PCIE##x##_CFG_DEVICE_PRESENT)
#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
SATA##x##_CFG_PM_CLK_EN | \
SATA##x##_CFG_POWERUP_RESET | \
SATA##x##_CFG_RX_CLK_EN | \
SATA##x##_CFG_TX_CLK_EN)
/* Pad multiplexing for i2c0 device */
static const unsigned i2c0_pins[] = { 102, 103 };
static struct spear_muxreg i2c0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2C0_MASK,
.val = PMX_I2C0_MASK,
},
};
static struct spear_modemux i2c0_modemux[] = {
{
.muxregs = i2c0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
},
};
static struct spear_pingroup i2c0_pingroup = {
.name = "i2c0_grp",
.pins = i2c0_pins,
.npins = ARRAY_SIZE(i2c0_pins),
.modemuxs = i2c0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
};
static const char *const i2c0_grps[] = { "i2c0_grp" };
static struct spear_function i2c0_function = {
.name = "i2c0",
.groups = i2c0_grps,
.ngroups = ARRAY_SIZE(i2c0_grps),
};
/* Pad multiplexing for ssp0 device */
static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
static struct spear_muxreg ssp0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SSP0_MASK,
.val = PMX_SSP0_MASK,
},
};
static struct spear_modemux ssp0_modemux[] = {
{
.muxregs = ssp0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
},
};
static struct spear_pingroup ssp0_pingroup = {
.name = "ssp0_grp",
.pins = ssp0_pins,
.npins = ARRAY_SIZE(ssp0_pins),
.modemuxs = ssp0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
};
/* Pad multiplexing for ssp0_cs0 device */
static const unsigned ssp0_cs0_pins[] = { 96 };
static struct spear_muxreg ssp0_cs0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_SSP0_CS0_MASK,
.val = PMX_SSP0_CS0_MASK,
},
};
static struct spear_modemux ssp0_cs0_modemux[] = {
{
.muxregs = ssp0_cs0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
},
};
static struct spear_pingroup ssp0_cs0_pingroup = {
.name = "ssp0_cs0_grp",
.pins = ssp0_cs0_pins,
.npins = ARRAY_SIZE(ssp0_cs0_pins),
.modemuxs = ssp0_cs0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
};
/* ssp0_cs1_2 device */
static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_SSP0_CS1_2_MASK,
.val = PMX_SSP0_CS1_2_MASK,
},
};
static struct spear_modemux ssp0_cs1_2_modemux[] = {
{
.muxregs = ssp0_cs1_2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
},
};
static struct spear_pingroup ssp0_cs1_2_pingroup = {
.name = "ssp0_cs1_2_grp",
.pins = ssp0_cs1_2_pins,
.npins = ARRAY_SIZE(ssp0_cs1_2_pins),
.modemuxs = ssp0_cs1_2_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
};
static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
"ssp0_cs1_2_grp" };
static struct spear_function ssp0_function = {
.name = "ssp0",
.groups = ssp0_grps,
.ngroups = ARRAY_SIZE(ssp0_grps),
};
/* Pad multiplexing for i2s0 device */
static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
static struct spear_muxreg i2s0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK,
.val = PMX_I2S0_MASK,
},
};
static struct spear_modemux i2s0_modemux[] = {
{
.muxregs = i2s0_muxreg,
.nmuxregs = ARRAY_SIZE(i2s0_muxreg),
},
};
static struct spear_pingroup i2s0_pingroup = {
.name = "i2s0_grp",
.pins = i2s0_pins,
.npins = ARRAY_SIZE(i2s0_pins),
.modemuxs = i2s0_modemux,
.nmodemuxs = ARRAY_SIZE(i2s0_modemux),
};
static const char *const i2s0_grps[] = { "i2s0_grp" };
static struct spear_function i2s0_function = {
.name = "i2s0",
.groups = i2s0_grps,
.ngroups = ARRAY_SIZE(i2s0_grps),
};
/* Pad multiplexing for i2s1 device */
static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
static struct spear_muxreg i2s1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_I2S1_MASK,
.val = PMX_I2S1_MASK,
},
};
static struct spear_modemux i2s1_modemux[] = {
{
.muxregs = i2s1_muxreg,
.nmuxregs = ARRAY_SIZE(i2s1_muxreg),
},
};
static struct spear_pingroup i2s1_pingroup = {
.name = "i2s1_grp",
.pins = i2s1_pins,
.npins = ARRAY_SIZE(i2s1_pins),
.modemuxs = i2s1_modemux,
.nmodemuxs = ARRAY_SIZE(i2s1_modemux),
};
static const char *const i2s1_grps[] = { "i2s1_grp" };
static struct spear_function i2s1_function = {
.name = "i2s1",
.groups = i2s1_grps,
.ngroups = ARRAY_SIZE(i2s1_grps),
};
/* Pad multiplexing for clcd device */
static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
135, 136, 137, 138, 139, 140, 141, 142 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
static struct spear_muxreg clcd_high_res_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_CLCD2_MASK,
.val = PMX_CLCD2_MASK,
},
};
static struct spear_modemux clcd_high_res_modemux[] = {
{
.muxregs = clcd_high_res_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
},
};
static struct spear_pingroup clcd_high_res_pingroup = {
.name = "clcd_high_res_grp",
.pins = clcd_high_res_pins,
.npins = ARRAY_SIZE(clcd_high_res_pins),
.modemuxs = clcd_high_res_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
146, 147, 148, 149, 150, 151, 152 };
static struct spear_muxreg arm_gpio_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_EGPIO_0_GRP_MASK,
.val = PMX_EGPIO_0_GRP_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_EGPIO_1_GRP_MASK,
.val = PMX_EGPIO_1_GRP_MASK,
},
};
static struct spear_modemux arm_gpio_modemux[] = {
{
.muxregs = arm_gpio_muxreg,
.nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
},
};
static struct spear_pingroup arm_gpio_pingroup = {
.name = "arm_gpio_grp",
.pins = arm_gpio_pins,
.npins = ARRAY_SIZE(arm_gpio_pins),
.modemuxs = arm_gpio_modemux,
.nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
};
static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
static struct spear_function arm_gpio_function = {
.name = "arm_gpio",
.groups = arm_gpio_grps,
.ngroups = ARRAY_SIZE(arm_gpio_grps),
};
/* Pad multiplexing for smi 2 chips device */
static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
static struct spear_muxreg smi_2_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
},
};
static struct spear_modemux smi_2_chips_modemux[] = {
{
.muxregs = smi_2_chips_muxreg,
.nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
},
};
static struct spear_pingroup smi_2_chips_pingroup = {
.name = "smi_2_chips_grp",
.pins = smi_2_chips_pins,
.npins = ARRAY_SIZE(smi_2_chips_pins),
.modemuxs = smi_2_chips_modemux,
.nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
};
static const unsigned smi_4_chips_pins[] = { 54, 55 };
static struct spear_muxreg smi_4_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
},
};
static struct spear_modemux smi_4_chips_modemux[] = {
{
.muxregs = smi_4_chips_muxreg,
.nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
},
};
static struct spear_pingroup smi_4_chips_pingroup = {
.name = "smi_4_chips_grp",
.pins = smi_4_chips_pins,
.npins = ARRAY_SIZE(smi_4_chips_pins),
.modemuxs = smi_4_chips_modemux,
.nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
};
static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
static struct spear_function smi_function = {
.name = "smi",
.groups = smi_grps,
.ngroups = ARRAY_SIZE(smi_grps),
};
/* Pad multiplexing for gmii device */
static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
195, 196, 197, 198, 199, 200 };
static struct spear_muxreg gmii_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_GMII_MASK,
.val = PMX_GMII_MASK,
},
};
static struct spear_modemux gmii_modemux[] = {
{
.muxregs = gmii_muxreg,
.nmuxregs = ARRAY_SIZE(gmii_muxreg),
},
};
static struct spear_pingroup gmii_pingroup = {
.name = "gmii_grp",
.pins = gmii_pins,
.npins = ARRAY_SIZE(gmii_pins),
.modemuxs = gmii_modemux,
.nmodemuxs = ARRAY_SIZE(gmii_modemux),
};
static const char *const gmii_grps[] = { "gmii_grp" };
static struct spear_function gmii_function = {
.name = "gmii",
.groups = gmii_grps,
.ngroups = ARRAY_SIZE(gmii_grps),
};
/* Pad multiplexing for rgmii device */
static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
static struct spear_muxreg rgmii_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_RGMII_REG0_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_RGMII_REG1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_RGMII_REG2_MASK,
.val = 0,
},
};
static struct spear_modemux rgmii_modemux[] = {
{
.muxregs = rgmii_muxreg,
.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
},
};
static struct spear_pingroup rgmii_pingroup = {
.name = "rgmii_grp",
.pins = rgmii_pins,
.npins = ARRAY_SIZE(rgmii_pins),
.modemuxs = rgmii_modemux,
.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
};
static const char *const rgmii_grps[] = { "rgmii_grp" };
static struct spear_function rgmii_function = {
.name = "rgmii",
.groups = rgmii_grps,
.ngroups = ARRAY_SIZE(rgmii_grps),
};
/* Pad multiplexing for smii_0_1_2 device */
static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53, 54, 55 };
static struct spear_muxreg smii_0_1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_SMII_0_1_2_MASK,
.val = 0,
},
};
static struct spear_modemux smii_0_1_2_modemux[] = {
{
.muxregs = smii_0_1_2_muxreg,
.nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
},
};
static struct spear_pingroup smii_0_1_2_pingroup = {
.name = "smii_0_1_2_grp",
.pins = smii_0_1_2_pins,
.npins = ARRAY_SIZE(smii_0_1_2_pins),
.modemuxs = smii_0_1_2_modemux,
.nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
};
static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
static struct spear_function smii_0_1_2_function = {
.name = "smii_0_1_2",
.groups = smii_0_1_2_grps,
.ngroups = ARRAY_SIZE(smii_0_1_2_grps),
};
/* Pad multiplexing for ras_mii_txclk device */
static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
static struct spear_muxreg ras_mii_txclk_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NFCE2_MASK,
.val = 0,
},
};
static struct spear_modemux ras_mii_txclk_modemux[] = {
{
.muxregs = ras_mii_txclk_muxreg,
.nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
},
};
static struct spear_pingroup ras_mii_txclk_pingroup = {
.name = "ras_mii_txclk_grp",
.pins = ras_mii_txclk_pins,
.npins = ARRAY_SIZE(ras_mii_txclk_pins),
.modemuxs = ras_mii_txclk_modemux,
.nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
};
static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
static struct spear_function ras_mii_txclk_function = {
.name = "ras_mii_txclk",
.groups = ras_mii_txclk_grps,
.ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
};
/* Pad multiplexing for nand 8bit device (cs0 only) */
static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
212 };
static struct spear_muxreg nand_8bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_NAND8BIT_0_MASK,
.val = PMX_NAND8BIT_0_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND8BIT_1_MASK,
.val = PMX_NAND8BIT_1_MASK,
},
};
static struct spear_modemux nand_8bit_modemux[] = {
{
.muxregs = nand_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
},
};
static struct spear_pingroup nand_8bit_pingroup = {
.name = "nand_8bit_grp",
.pins = nand_8bit_pins,
.npins = ARRAY_SIZE(nand_8bit_pins),
.modemuxs = nand_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
};
/* Pad multiplexing for nand 16bit device */
static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
210 };
static struct spear_muxreg nand_16bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND16BIT_1_MASK,
.val = PMX_NAND16BIT_1_MASK,
},
};
static struct spear_modemux nand_16bit_modemux[] = {
{
.muxregs = nand_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
},
};
static struct spear_pingroup nand_16bit_pingroup = {
.name = "nand_16bit_grp",
.pins = nand_16bit_pins,
.npins = ARRAY_SIZE(nand_16bit_pins),
.modemuxs = nand_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
};
/* Pad multiplexing for nand 4 chips */
static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
static struct spear_muxreg nand_4_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND_4CHIPS_MASK,
.val = PMX_NAND_4CHIPS_MASK,
},
};
static struct spear_modemux nand_4_chips_modemux[] = {
{
.muxregs = nand_4_chips_muxreg,
.nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
},
};
static struct spear_pingroup nand_4_chips_pingroup = {
.name = "nand_4_chips_grp",
.pins = nand_4_chips_pins,
.npins = ARRAY_SIZE(nand_4_chips_pins),
.modemuxs = nand_4_chips_modemux,
.nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
};
static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
"nand_4_chips_grp" };
static struct spear_function nand_function = {
.name = "nand",
.groups = nand_grps,
.ngroups = ARRAY_SIZE(nand_grps),
};
/* Pad multiplexing for keyboard_6x6 device */
static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
208, 209, 210, 211, 212 };
static struct spear_muxreg keyboard_6x6_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
PMX_NFWPRT2_MASK,
.val = PMX_KEYBOARD_6X6_MASK,
},
};
static struct spear_modemux keyboard_6x6_modemux[] = {
{
.muxregs = keyboard_6x6_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
},
};
static struct spear_pingroup keyboard_6x6_pingroup = {
.name = "keyboard_6x6_grp",
.pins = keyboard_6x6_pins,
.npins = ARRAY_SIZE(keyboard_6x6_pins),
.modemuxs = keyboard_6x6_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
};
/* Pad multiplexing for keyboard_rowcol6_8 device */
static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL68_MASK,
.val = PMX_KBD_ROWCOL68_MASK,
},
};
static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
{
.muxregs = keyboard_rowcol6_8_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
},
};
static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
.name = "keyboard_rowcol6_8_grp",
.pins = keyboard_rowcol6_8_pins,
.npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
.modemuxs = keyboard_rowcol6_8_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
};
static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp" };
static struct spear_function keyboard_function = {
.name = "keyboard",
.groups = keyboard_grps,
.ngroups = ARRAY_SIZE(keyboard_grps),
};
/* Pad multiplexing for uart0 device */
static const unsigned uart0_pins[] = { 100, 101 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_UART0_MASK,
.val = PMX_UART0_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
static struct spear_pingroup uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
/* Pad multiplexing for uart0_modem device */
static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
static struct spear_muxreg uart0_modem_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_UART0_MODEM_MASK,
.val = PMX_UART0_MODEM_MASK,
},
};
static struct spear_modemux uart0_modem_modemux[] = {
{
.muxregs = uart0_modem_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
},
};
static struct spear_pingroup uart0_modem_pingroup = {
.name = "uart0_modem_grp",
.pins = uart0_modem_pins,
.npins = ARRAY_SIZE(uart0_modem_pins),
.modemuxs = uart0_modem_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
static struct spear_function uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* Pad multiplexing for gpt0_tmr0 device */
static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
static struct spear_muxreg gpt0_tmr0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT0_TMR0_MASK,
.val = PMX_GPT0_TMR0_MASK,
},
};
static struct spear_modemux gpt0_tmr0_modemux[] = {
{
.muxregs = gpt0_tmr0_muxreg,
.nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
},
};
static struct spear_pingroup gpt0_tmr0_pingroup = {
.name = "gpt0_tmr0_grp",
.pins = gpt0_tmr0_pins,
.npins = ARRAY_SIZE(gpt0_tmr0_pins),
.modemuxs = gpt0_tmr0_modemux,
.nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
};
/* Pad multiplexing for gpt0_tmr1 device */
static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
static struct spear_muxreg gpt0_tmr1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT0_TMR1_MASK,
.val = PMX_GPT0_TMR1_MASK,
},
};
static struct spear_modemux gpt0_tmr1_modemux[] = {
{
.muxregs = gpt0_tmr1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
},
};
static struct spear_pingroup gpt0_tmr1_pingroup = {
.name = "gpt0_tmr1_grp",
.pins = gpt0_tmr1_pins,
.npins = ARRAY_SIZE(gpt0_tmr1_pins),
.modemuxs = gpt0_tmr1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
};
static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
static struct spear_function gpt0_function = {
.name = "gpt0",
.groups = gpt0_grps,
.ngroups = ARRAY_SIZE(gpt0_grps),
};
/* Pad multiplexing for gpt1_tmr0 device */
static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
static struct spear_muxreg gpt1_tmr0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT1_TMR0_MASK,
.val = PMX_GPT1_TMR0_MASK,
},
};
static struct spear_modemux gpt1_tmr0_modemux[] = {
{
.muxregs = gpt1_tmr0_muxreg,
.nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
},
};
static struct spear_pingroup gpt1_tmr0_pingroup = {
.name = "gpt1_tmr0_grp",
.pins = gpt1_tmr0_pins,
.npins = ARRAY_SIZE(gpt1_tmr0_pins),
.modemuxs = gpt1_tmr0_modemux,
.nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
};
/* Pad multiplexing for gpt1_tmr1 device */
static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
static struct spear_muxreg gpt1_tmr1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT1_TMR1_MASK,
.val = PMX_GPT1_TMR1_MASK,
},
};
static struct spear_modemux gpt1_tmr1_modemux[] = {
{
.muxregs = gpt1_tmr1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
},
};
static struct spear_pingroup gpt1_tmr1_pingroup = {
.name = "gpt1_tmr1_grp",
.pins = gpt1_tmr1_pins,
.npins = ARRAY_SIZE(gpt1_tmr1_pins),
.modemuxs = gpt1_tmr1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
};
static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
static struct spear_function gpt1_function = {
.name = "gpt1",
.groups = gpt1_grps,
.ngroups = ARRAY_SIZE(gpt1_grps),
};
/* Pad multiplexing for mcif device */
static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
243, 244, 245 };
#define MCIF_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = PMX_MCI_DATA8_15_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_1, \
.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
PMX_NFWPRT2_MASK, \
.val = PMX_MCIFALL_1_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_2, \
.mask = PMX_MCIFALL_2_MASK, \
.val = PMX_MCIFALL_2_MASK, \
}
/* sdhci device */
static struct spear_muxreg sdhci_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_SD,
},
};
static struct spear_modemux sdhci_modemux[] = {
{
.muxregs = sdhci_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
},
};
static struct spear_pingroup sdhci_pingroup = {
.name = "sdhci_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = sdhci_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* cf device */
static struct spear_muxreg cf_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_CF,
},
};
static struct spear_modemux cf_modemux[] = {
{
.muxregs = cf_muxreg,
.nmuxregs = ARRAY_SIZE(cf_muxreg),
},
};
static struct spear_pingroup cf_pingroup = {
.name = "cf_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = cf_modemux,
.nmodemuxs = ARRAY_SIZE(cf_modemux),
};
static const char *const cf_grps[] = { "cf_grp" };
static struct spear_function cf_function = {
.name = "cf",
.groups = cf_grps,
.ngroups = ARRAY_SIZE(cf_grps),
};
/* xd device */
static struct spear_muxreg xd_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_XD,
},
};
static struct spear_modemux xd_modemux[] = {
{
.muxregs = xd_muxreg,
.nmuxregs = ARRAY_SIZE(xd_muxreg),
},
};
static struct spear_pingroup xd_pingroup = {
.name = "xd_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = xd_modemux,
.nmodemuxs = ARRAY_SIZE(xd_modemux),
};
static const char *const xd_grps[] = { "xd_grp" };
static struct spear_function xd_function = {
.name = "xd",
.groups = xd_grps,
.ngroups = ARRAY_SIZE(xd_grps),
};
/* Pad multiplexing for touch_xy device */
static const unsigned touch_xy_pins[] = { 97 };
static struct spear_muxreg touch_xy_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_TOUCH_XY_MASK,
.val = PMX_TOUCH_XY_MASK,
},
};
static struct spear_modemux touch_xy_modemux[] = {
{
.muxregs = touch_xy_muxreg,
.nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
},
};
static struct spear_pingroup touch_xy_pingroup = {
.name = "touch_xy_grp",
.pins = touch_xy_pins,
.npins = ARRAY_SIZE(touch_xy_pins),
.modemuxs = touch_xy_modemux,
.nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
};
static const char *const touch_xy_grps[] = { "touch_xy_grp" };
static struct spear_function touch_xy_function = {
.name = "touchscreen",
.groups = touch_xy_grps,
.ngroups = ARRAY_SIZE(touch_xy_grps),
};
/* Pad multiplexing for uart1 device */
/* Muxed with I2C */
static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2C0_MASK,
.val = 0,
},
};
static struct spear_modemux uart1_dis_i2c_modemux[] = {
{
.muxregs = uart1_dis_i2c_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
},
};
static struct spear_pingroup uart_1_dis_i2c_pingroup = {
.name = "uart1_disable_i2c_grp",
.pins = uart1_dis_i2c_pins,
.npins = ARRAY_SIZE(uart1_dis_i2c_pins),
.modemuxs = uart1_dis_i2c_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
};
/* Muxed with SD/MMC */
static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
static struct spear_muxreg uart1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_MCIDATA1_MASK |
PMX_MCIDATA2_MASK,
.val = 0,
},
};
static struct spear_modemux uart1_dis_sd_modemux[] = {
{
.muxregs = uart1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
},
};
static struct spear_pingroup uart_1_dis_sd_pingroup = {
.name = "uart1_disable_sd_grp",
.pins = uart1_dis_sd_pins,
.npins = ARRAY_SIZE(uart1_dis_sd_pins),
.modemuxs = uart1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
};
static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
"uart1_disable_sd_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* Pad multiplexing for uart2_3 device */
static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
static struct spear_muxreg uart2_3_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK,
.val = 0,
},
};
static struct spear_modemux uart2_3_modemux[] = {
{
.muxregs = uart2_3_muxreg,
.nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
},
};
static struct spear_pingroup uart_2_3_pingroup = {
.name = "uart2_3_grp",
.pins = uart2_3_pins,
.npins = ARRAY_SIZE(uart2_3_pins),
.modemuxs = uart2_3_modemux,
.nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
};
static const char *const uart2_3_grps[] = { "uart2_3_grp" };
static struct spear_function uart2_3_function = {
.name = "uart2_3",
.groups = uart2_3_grps,
.ngroups = ARRAY_SIZE(uart2_3_grps),
};
/* Pad multiplexing for uart4 device */
static const unsigned uart4_pins[] = { 108, 113 };
static struct spear_muxreg uart4_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux uart4_modemux[] = {
{
.muxregs = uart4_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_muxreg),
},
};
static struct spear_pingroup uart_4_pingroup = {
.name = "uart4_grp",
.pins = uart4_pins,
.npins = ARRAY_SIZE(uart4_pins),
.modemuxs = uart4_modemux,
.nmodemuxs = ARRAY_SIZE(uart4_modemux),
};
static const char *const uart4_grps[] = { "uart4_grp" };
static struct spear_function uart4_function = {
.name = "uart4",
.groups = uart4_grps,
.ngroups = ARRAY_SIZE(uart4_grps),
};
/* Pad multiplexing for uart5 device */
static const unsigned uart5_pins[] = { 114, 115 };
static struct spear_muxreg uart5_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux uart5_modemux[] = {
{
.muxregs = uart5_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_muxreg),
},
};
static struct spear_pingroup uart_5_pingroup = {
.name = "uart5_grp",
.pins = uart5_pins,
.npins = ARRAY_SIZE(uart5_pins),
.modemuxs = uart5_modemux,
.nmodemuxs = ARRAY_SIZE(uart5_modemux),
};
static const char *const uart5_grps[] = { "uart5_grp" };
static struct spear_function uart5_function = {
.name = "uart5",
.groups = uart5_grps,
.ngroups = ARRAY_SIZE(uart5_grps),
};
/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
136, 137 };
static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
{
.muxregs = rs485_0_1_tdm_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
},
};
static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
.name = "rs485_0_1_tdm_0_1_grp",
.pins = rs485_0_1_tdm_0_1_pins,
.npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
.modemuxs = rs485_0_1_tdm_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
};
static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
static struct spear_function rs485_0_1_tdm_0_1_function = {
.name = "rs485_0_1_tdm_0_1",
.groups = rs485_0_1_tdm_0_1_grps,
.ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
};
/* Pad multiplexing for i2c_1_2 device */
static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
static struct spear_muxreg i2c_1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_1_2_modemux[] = {
{
.muxregs = i2c_1_2_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
},
};
static struct spear_pingroup i2c_1_2_pingroup = {
.name = "i2c_1_2_grp",
.pins = i2c_1_2_pins,
.npins = ARRAY_SIZE(i2c_1_2_pins),
.modemuxs = i2c_1_2_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
};
static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
static struct spear_function i2c_1_2_function = {
.name = "i2c_1_2",
.groups = i2c_1_2_grps,
.ngroups = ARRAY_SIZE(i2c_1_2_grps),
};
/* Pad multiplexing for i2c3_dis_smi_clcd device */
/* Muxed with SMI & CLCD */
static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
.val = 0,
},
};
static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
{
.muxregs = i2c3_dis_smi_clcd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
},
};
static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
.name = "i2c3_dis_smi_clcd_grp",
.pins = i2c3_dis_smi_clcd_pins,
.npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
.modemuxs = i2c3_dis_smi_clcd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
};
/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
/* Muxed with SD/MMC & I2S1 */
static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
.val = 0,
},
};
static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
{
.muxregs = i2c3_dis_sd_i2s0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
},
};
static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
.name = "i2c3_dis_sd_i2s0_grp",
.pins = i2c3_dis_sd_i2s0_pins,
.npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
.modemuxs = i2c3_dis_sd_i2s0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
};
static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
"i2c3_dis_sd_i2s0_grp" };
static struct spear_function i2c3_unction = {
.name = "i2c3_i2s1",
.groups = i2c3_grps,
.ngroups = ARRAY_SIZE(i2c3_grps),
};
/* Pad multiplexing for i2c_4_5_dis_smi device */
/* Muxed with SMI */
static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
{
.muxregs = i2c_4_5_dis_smi_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
},
};
static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
.name = "i2c_4_5_dis_smi_grp",
.pins = i2c_4_5_dis_smi_pins,
.npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
.modemuxs = i2c_4_5_dis_smi_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
};
/* Pad multiplexing for i2c4_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_MCIDATA4_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIDATA5_MASK,
.val = 0,
},
};
static struct spear_modemux i2c4_dis_sd_modemux[] = {
{
.muxregs = i2c4_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c4_dis_sd_pingroup = {
.name = "i2c4_dis_sd_grp",
.pins = i2c4_dis_sd_pins,
.npins = ARRAY_SIZE(i2c4_dis_sd_pins),
.modemuxs = i2c4_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
};
/* Pad multiplexing for i2c5_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIDATA6_MASK |
PMX_MCIDATA7_MASK,
.val = 0,
},
};
static struct spear_modemux i2c5_dis_sd_modemux[] = {
{
.muxregs = i2c5_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c5_dis_sd_pingroup = {
.name = "i2c5_dis_sd_grp",
.pins = i2c5_dis_sd_pins,
.npins = ARRAY_SIZE(i2c5_dis_sd_pins),
.modemuxs = i2c5_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
};
static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
"i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
static struct spear_function i2c_4_5_function = {
.name = "i2c_4_5",
.groups = i2c_4_5_grps,
.ngroups = ARRAY_SIZE(i2c_4_5_grps),
};
/* Pad multiplexing for i2c_6_7_dis_kbd device */
/* Muxed with KBD */
static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
{
.muxregs = i2c_6_7_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
},
};
static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
.name = "i2c_6_7_dis_kbd_grp",
.pins = i2c_6_7_dis_kbd_pins,
.npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
.modemuxs = i2c_6_7_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
};
/* Pad multiplexing for i2c6_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIIORDRE_MASK |
PMX_MCIIOWRWE_MASK,
.val = 0,
},
};
static struct spear_modemux i2c6_dis_sd_modemux[] = {
{
.muxregs = i2c6_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c6_dis_sd_pingroup = {
.name = "i2c6_dis_sd_grp",
.pins = i2c6_dis_sd_pins,
.npins = ARRAY_SIZE(i2c6_dis_sd_pins),
.modemuxs = i2c6_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
};
/* Pad multiplexing for i2c7_dis_sd device */
static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIRESETCF_MASK |
PMX_MCICS0CE_MASK,
.val = 0,
},
};
static struct spear_modemux i2c7_dis_sd_modemux[] = {
{
.muxregs = i2c7_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c7_dis_sd_pingroup = {
.name = "i2c7_dis_sd_grp",
.pins = i2c7_dis_sd_pins,
.npins = ARRAY_SIZE(i2c7_dis_sd_pins),
.modemuxs = i2c7_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
};
static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
"i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
static struct spear_function i2c_6_7_function = {
.name = "i2c_6_7",
.groups = i2c_6_7_grps,
.ngroups = ARRAY_SIZE(i2c_6_7_grps),
};
/* Pad multiplexing for can0_dis_nor device */
/* Muxed with NOR */
static const unsigned can0_dis_nor_pins[] = { 56, 57 };
static struct spear_muxreg can0_dis_nor_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_NFRSTPWDWN2_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NFRSTPWDWN3_MASK,
.val = 0,
},
};
static struct spear_modemux can0_dis_nor_modemux[] = {
{
.muxregs = can0_dis_nor_muxreg,
.nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
},
};
static struct spear_pingroup can0_dis_nor_pingroup = {
.name = "can0_dis_nor_grp",
.pins = can0_dis_nor_pins,
.npins = ARRAY_SIZE(can0_dis_nor_pins),
.modemuxs = can0_dis_nor_modemux,
.nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
};
/* Pad multiplexing for can0_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned can0_dis_sd_pins[] = { 240, 241 };
static struct spear_muxreg can0_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
.val = 0,
},
};
static struct spear_modemux can0_dis_sd_modemux[] = {
{
.muxregs = can0_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
},
};
static struct spear_pingroup can0_dis_sd_pingroup = {
.name = "can0_dis_sd_grp",
.pins = can0_dis_sd_pins,
.npins = ARRAY_SIZE(can0_dis_sd_pins),
.modemuxs = can0_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
};
static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
};
static struct spear_function can0_function = {
.name = "can0",
.groups = can0_grps,
.ngroups = ARRAY_SIZE(can0_grps),
};
/* Pad multiplexing for can1_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned can1_dis_sd_pins[] = { 242, 243 };
static struct spear_muxreg can1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
.val = 0,
},
};
static struct spear_modemux can1_dis_sd_modemux[] = {
{
.muxregs = can1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
},
};
static struct spear_pingroup can1_dis_sd_pingroup = {
.name = "can1_dis_sd_grp",
.pins = can1_dis_sd_pins,
.npins = ARRAY_SIZE(can1_dis_sd_pins),
.modemuxs = can1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
};
/* Pad multiplexing for can1_dis_kbd device */
/* Muxed with KBD */
static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
static struct spear_muxreg can1_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = 0,
},
};
static struct spear_modemux can1_dis_kbd_modemux[] = {
{
.muxregs = can1_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
},
};
static struct spear_pingroup can1_dis_kbd_pingroup = {
.name = "can1_dis_kbd_grp",
.pins = can1_dis_kbd_pins,
.npins = ARRAY_SIZE(can1_dis_kbd_pins),
.modemuxs = can1_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
};
static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
};
static struct spear_function can1_function = {
.name = "can1",
.groups = can1_grps,
.ngroups = ARRAY_SIZE(can1_grps),
};
/* Pad multiplexing for pci device */
static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
#define PCI_SATA_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = 0, \
}, { \
.reg = PAD_FUNCTION_EN_1, \
.mask = PMX_PCI_REG1_MASK, \
.val = 0, \
}, { \
.reg = PAD_FUNCTION_EN_2, \
.mask = PMX_PCI_REG2_MASK, \
.val = 0, \
}
/* pad multiplexing for pcie0 device */
static struct spear_muxreg pcie0_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(0),
.val = PCIE_CFG_VAL(0),
},
};
static struct spear_modemux pcie0_modemux[] = {
{
.muxregs = pcie0_muxreg,
.nmuxregs = ARRAY_SIZE(pcie0_muxreg),
},
};
static struct spear_pingroup pcie0_pingroup = {
.name = "pcie0_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie0_modemux,
.nmodemuxs = ARRAY_SIZE(pcie0_modemux),
};
/* pad multiplexing for pcie1 device */
static struct spear_muxreg pcie1_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(1),
.val = PCIE_CFG_VAL(1),
},
};
static struct spear_modemux pcie1_modemux[] = {
{
.muxregs = pcie1_muxreg,
.nmuxregs = ARRAY_SIZE(pcie1_muxreg),
},
};
static struct spear_pingroup pcie1_pingroup = {
.name = "pcie1_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie1_modemux,
.nmodemuxs = ARRAY_SIZE(pcie1_modemux),
};
/* pad multiplexing for pcie2 device */
static struct spear_muxreg pcie2_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(2),
.val = PCIE_CFG_VAL(2),
},
};
static struct spear_modemux pcie2_modemux[] = {
{
.muxregs = pcie2_muxreg,
.nmuxregs = ARRAY_SIZE(pcie2_muxreg),
},
};
static struct spear_pingroup pcie2_pingroup = {
.name = "pcie2_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie2_modemux,
.nmodemuxs = ARRAY_SIZE(pcie2_modemux),
};
static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
static struct spear_function pci_function = {
.name = "pci",
.groups = pci_grps,
.ngroups = ARRAY_SIZE(pci_grps),
};
/* pad multiplexing for sata0 device */
static struct spear_muxreg sata0_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(0),
.val = SATA_CFG_VAL(0),
},
};
static struct spear_modemux sata0_modemux[] = {
{
.muxregs = sata0_muxreg,
.nmuxregs = ARRAY_SIZE(sata0_muxreg),
},
};
static struct spear_pingroup sata0_pingroup = {
.name = "sata0_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata0_modemux,
.nmodemuxs = ARRAY_SIZE(sata0_modemux),
};
/* pad multiplexing for sata1 device */
static struct spear_muxreg sata1_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(1),
.val = SATA_CFG_VAL(1),
},
};
static struct spear_modemux sata1_modemux[] = {
{
.muxregs = sata1_muxreg,
.nmuxregs = ARRAY_SIZE(sata1_muxreg),
},
};
static struct spear_pingroup sata1_pingroup = {
.name = "sata1_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata1_modemux,
.nmodemuxs = ARRAY_SIZE(sata1_modemux),
};
/* pad multiplexing for sata2 device */
static struct spear_muxreg sata2_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(2),
.val = SATA_CFG_VAL(2),
},
};
static struct spear_modemux sata2_modemux[] = {
{
.muxregs = sata2_muxreg,
.nmuxregs = ARRAY_SIZE(sata2_muxreg),
},
};
static struct spear_pingroup sata2_pingroup = {
.name = "sata2_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata2_modemux,
.nmodemuxs = ARRAY_SIZE(sata2_modemux),
};
static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
};
static struct spear_function sata_function = {
.name = "sata",
.groups = sata_grps,
.ngroups = ARRAY_SIZE(sata_grps),
};
/* Pad multiplexing for ssp1_dis_kbd device */
static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
PMX_NFCE2_MASK,
.val = 0,
},
};
static struct spear_modemux ssp1_dis_kbd_modemux[] = {
{
.muxregs = ssp1_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
},
};
static struct spear_pingroup ssp1_dis_kbd_pingroup = {
.name = "ssp1_dis_kbd_grp",
.pins = ssp1_dis_kbd_pins,
.npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
.modemuxs = ssp1_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
};
/* Pad multiplexing for ssp1_dis_sd device */
static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
.val = 0,
},
};
static struct spear_modemux ssp1_dis_sd_modemux[] = {
{
.muxregs = ssp1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
},
};
static struct spear_pingroup ssp1_dis_sd_pingroup = {
.name = "ssp1_dis_sd_grp",
.pins = ssp1_dis_sd_pins,
.npins = ARRAY_SIZE(ssp1_dis_sd_pins),
.modemuxs = ssp1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
};
static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
"ssp1_dis_sd_grp" };
static struct spear_function ssp1_function = {
.name = "ssp1",
.groups = ssp1_grps,
.ngroups = ARRAY_SIZE(ssp1_grps),
};
/* Pad multiplexing for gpt64 device */
static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
static struct spear_muxreg gpt64_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
| PMX_MCILEDS_MASK,
.val = 0,
},
};
static struct spear_modemux gpt64_modemux[] = {
{
.muxregs = gpt64_muxreg,
.nmuxregs = ARRAY_SIZE(gpt64_muxreg),
},
};
static struct spear_pingroup gpt64_pingroup = {
.name = "gpt64_grp",
.pins = gpt64_pins,
.npins = ARRAY_SIZE(gpt64_pins),
.modemuxs = gpt64_modemux,
.nmodemuxs = ARRAY_SIZE(gpt64_modemux),
};
static const char *const gpt64_grps[] = { "gpt64_grp" };
static struct spear_function gpt64_function = {
.name = "gpt64",
.groups = gpt64_grps,
.ngroups = ARRAY_SIZE(gpt64_grps),
};
/* pingroups */
static struct spear_pingroup *spear1310_pingroups[] = {
&i2c0_pingroup,
&ssp0_pingroup,
&i2s0_pingroup,
&i2s1_pingroup,
&clcd_pingroup,
&clcd_high_res_pingroup,
&arm_gpio_pingroup,
&smi_2_chips_pingroup,
&smi_4_chips_pingroup,
&gmii_pingroup,
&rgmii_pingroup,
&smii_0_1_2_pingroup,
&ras_mii_txclk_pingroup,
&nand_8bit_pingroup,
&nand_16bit_pingroup,
&nand_4_chips_pingroup,
&keyboard_6x6_pingroup,
&keyboard_rowcol6_8_pingroup,
&uart0_pingroup,
&uart0_modem_pingroup,
&gpt0_tmr0_pingroup,
&gpt0_tmr1_pingroup,
&gpt1_tmr0_pingroup,
&gpt1_tmr1_pingroup,
&sdhci_pingroup,
&cf_pingroup,
&xd_pingroup,
&touch_xy_pingroup,
&ssp0_cs0_pingroup,
&ssp0_cs1_2_pingroup,
&uart_1_dis_i2c_pingroup,
&uart_1_dis_sd_pingroup,
&uart_2_3_pingroup,
&uart_4_pingroup,
&uart_5_pingroup,
&rs485_0_1_tdm_0_1_pingroup,
&i2c_1_2_pingroup,
&i2c3_dis_smi_clcd_pingroup,
&i2c3_dis_sd_i2s0_pingroup,
&i2c_4_5_dis_smi_pingroup,
&i2c4_dis_sd_pingroup,
&i2c5_dis_sd_pingroup,
&i2c_6_7_dis_kbd_pingroup,
&i2c6_dis_sd_pingroup,
&i2c7_dis_sd_pingroup,
&can0_dis_nor_pingroup,
&can0_dis_sd_pingroup,
&can1_dis_sd_pingroup,
&can1_dis_kbd_pingroup,
&pcie0_pingroup,
&pcie1_pingroup,
&pcie2_pingroup,
&sata0_pingroup,
&sata1_pingroup,
&sata2_pingroup,
&ssp1_dis_kbd_pingroup,
&ssp1_dis_sd_pingroup,
&gpt64_pingroup,
};
/* functions */
static struct spear_function *spear1310_functions[] = {
&i2c0_function,
&ssp0_function,
&i2s0_function,
&i2s1_function,
&clcd_function,
&arm_gpio_function,
&smi_function,
&gmii_function,
&rgmii_function,
&smii_0_1_2_function,
&ras_mii_txclk_function,
&nand_function,
&keyboard_function,
&uart0_function,
&gpt0_function,
&gpt1_function,
&sdhci_function,
&cf_function,
&xd_function,
&touch_xy_function,
&uart1_function,
&uart2_3_function,
&uart4_function,
&uart5_function,
&rs485_0_1_tdm_0_1_function,
&i2c_1_2_function,
&i2c3_unction,
&i2c_4_5_function,
&i2c_6_7_function,
&can0_function,
&can1_function,
&pci_function,
&sata_function,
&ssp1_function,
&gpt64_function,
};
static struct spear_pinctrl_machdata spear1310_machdata = {
.pins = spear1310_pins,
.npins = ARRAY_SIZE(spear1310_pins),
.groups = spear1310_pingroups,
.ngroups = ARRAY_SIZE(spear1310_pingroups),
.functions = spear1310_functions,
.nfunctions = ARRAY_SIZE(spear1310_functions),
.modes_supported = false,
};
static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
{
.compatible = "st,spear1310-pinmux",
},
{},
};
static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
{
return spear_pinctrl_probe(pdev, &spear1310_machdata);
}
static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
{
return spear_pinctrl_remove(pdev);
}
static struct platform_driver spear1310_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = spear1310_pinctrl_of_match,
},
.probe = spear1310_pinctrl_probe,
.remove = __devexit_p(spear1310_pinctrl_remove),
};
static int __init spear1310_pinctrl_init(void)
{
return platform_driver_register(&spear1310_pinctrl_driver);
}
arch_initcall(spear1310_pinctrl_init);
static void __exit spear1310_pinctrl_exit(void)
{
platform_driver_unregister(&spear1310_pinctrl_driver);
}
module_exit(spear1310_pinctrl_exit);
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
drivers/pinctrl/spear/pinctrl-spear1340.c 0 → 100644
View file @ 30b84288
/*
* Driver for the ST Microelectronics SPEAr1340 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear1340-pinmux"
/* pins */
static const struct pinctrl_pin_desc spear1340_pins[] = {
SPEAR_PIN_0_TO_101,
SPEAR_PIN_102_TO_245,
PINCTRL_PIN(246, "PLGPIO246"),
PINCTRL_PIN(247, "PLGPIO247"),
PINCTRL_PIN(248, "PLGPIO248"),
PINCTRL_PIN(249, "PLGPIO249"),
PINCTRL_PIN(250, "PLGPIO250"),
PINCTRL_PIN(251, "PLGPIO251"),
};
/* In SPEAr1340 there are two levels of pad muxing */
/* - pads as gpio OR peripherals */
#define PAD_FUNCTION_EN_1 0x668
#define PAD_FUNCTION_EN_2 0x66C
#define PAD_FUNCTION_EN_3 0x670
#define PAD_FUNCTION_EN_4 0x674
#define PAD_FUNCTION_EN_5 0x690
#define PAD_FUNCTION_EN_6 0x694
#define PAD_FUNCTION_EN_7 0x698
#define PAD_FUNCTION_EN_8 0x69C
/* - If peripherals, then primary OR alternate peripheral */
#define PAD_SHARED_IP_EN_1 0x6A0
#define PAD_SHARED_IP_EN_2 0x6A4
/*
* Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
* registers with 32 bits each for handling gpio pads, register 8 has only 26
* relevant bits.
*/
/* macro's for making pads as gpio's */
#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
/* macro's for making pads as peripherals */
#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
#define I2C1_REG0_MASK 0x01080000
#define SPDIF_IN_REG0_MASK 0x00100000
#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
#define VIP_AND_CAM3_REG0_MASK 0xFC200000
#define VIP_AND_CAM3_REG1_MASK 0x0000000F
#define VIP_REG1_MASK 0x00001EF0
#define VIP_AND_CAM2_REG1_MASK 0x007FE100
#define VIP_AND_CAM1_REG1_MASK 0xFF800000
#define VIP_AND_CAM1_REG2_MASK 0x00000003
#define VIP_AND_CAM0_REG2_MASK 0x00001FFC
#define SMI_REG2_MASK 0x0021E000
#define SSP0_REG2_MASK 0x001E0000
#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
#define UART0_REG2_MASK 0x01800000
#define UART1_REG2_MASK 0x06000000
#define I2S_IN_REG2_MASK 0xF8000000
#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
#define I2S_OUT_REG3_MASK 0x000001EF
#define I2S_IN_REG3_MASK 0x00000010
#define GMAC_REG3_MASK 0xFFFFFE00
#define GMAC_REG4_MASK 0x0000001F
#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
#define SSP0_CS3_REG4_MASK 0x00000020
#define I2C0_REG4_MASK 0x000000C0
#define CEC0_REG4_MASK 0x00000100
#define CEC1_REG4_MASK 0x00000200
#define SPDIF_OUT_REG4_MASK 0x00000400
#define CLCD_REG4_MASK 0x7FFFF800
#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
#define MCIF_REG6_MASK 0xF8C00000
#define MCIF_REG7_MASK 0x000043FF
#define FSMC_8BIT_REG7_MASK 0x07FFBC00
/* other registers */
#define PERIP_CFG 0x42C
/* PERIP_CFG register masks */
#define SSP_CS_CTL_HW 0
#define SSP_CS_CTL_SW 1
#define SSP_CS_CTL_MASK 1
#define SSP_CS_CTL_SHIFT 21
#define SSP_CS_VAL_MASK 1
#define SSP_CS_VAL_SHIFT 20
#define SSP_CS_SEL_CS0 0
#define SSP_CS_SEL_CS1 1
#define SSP_CS_SEL_CS2 2
#define SSP_CS_SEL_MASK 3
#define SSP_CS_SEL_SHIFT 18
#define I2S_CHNL_2_0 (0)
#define I2S_CHNL_3_1 (1)
#define I2S_CHNL_5_1 (2)
#define I2S_CHNL_7_1 (3)
#define I2S_CHNL_PLAY_SHIFT (4)
#define I2S_CHNL_PLAY_MASK (3 << 4)
#define I2S_CHNL_REC_SHIFT (6)
#define I2S_CHNL_REC_MASK (3 << 6)
#define SPDIF_OUT_ENB_MASK (1 << 2)
#define SPDIF_OUT_ENB_SHIFT 2
#define MCIF_SEL_SD 1
#define MCIF_SEL_CF 2
#define MCIF_SEL_XD 3
#define MCIF_SEL_MASK 3
#define MCIF_SEL_SHIFT 0
#define GMAC_CLK_CFG 0x248
#define GMAC_PHY_IF_GMII_VAL (0 << 3)
#define GMAC_PHY_IF_RGMII_VAL (1 << 3)
#define GMAC_PHY_IF_SGMII_VAL (2 << 3)
#define GMAC_PHY_IF_RMII_VAL (4 << 3)
#define GMAC_PHY_IF_SEL_MASK (7 << 3)
#define GMAC_PHY_INPUT_ENB_VAL 0
#define GMAC_PHY_SYNT_ENB_VAL 1
#define GMAC_PHY_CLK_MASK 1
#define GMAC_PHY_CLK_SHIFT 2
#define GMAC_PHY_125M_PAD_VAL 0
#define GMAC_PHY_PLL2_VAL 1
#define GMAC_PHY_OSC3_VAL 2
#define GMAC_PHY_INPUT_CLK_MASK 3
#define GMAC_PHY_INPUT_CLK_SHIFT 0
#define PCIE_SATA_CFG 0x424
/* PCIE CFG MASks */
#define PCIE_CFG_DEVICE_PRESENT (1 << 11)
#define PCIE_CFG_POWERUP_RESET (1 << 10)
#define PCIE_CFG_CORE_CLK_EN (1 << 9)
#define PCIE_CFG_AUX_CLK_EN (1 << 8)
#define SATA_CFG_TX_CLK_EN (1 << 4)
#define SATA_CFG_RX_CLK_EN (1 << 3)
#define SATA_CFG_POWERUP_RESET (1 << 2)
#define SATA_CFG_PM_CLK_EN (1 << 1)
#define PCIE_SATA_SEL_PCIE (0)
#define PCIE_SATA_SEL_SATA (1)
#define SATA_PCIE_CFG_MASK 0xF1F
#define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
PCIE_CFG_DEVICE_PRESENT)
#define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
SATA_CFG_TX_CLK_EN)
/* Macro's for second level of pmx - pads as primary OR alternate peripheral */
/* Write 0 to enable FSMC_16_BIT */
#define KBD_ROW_COL_MASK (1 << 0)
/* Write 0 to enable UART0_ENH */
#define GPT_MASK (1 << 1) /* Only clk & cpt */
/* Write 0 to enable PWM1 */
#define KBD_COL5_MASK (1 << 2)
/* Write 0 to enable PWM2 */
#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
/* Write 0 to enable PWM3 */
#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
/* Write 0 to enable PWM0 */
#define SSP0_CS1_MASK (1 << 5)
/* Write 0 to enable VIP */
#define CAM3_MASK (1 << 6)
/* Write 0 to enable VIP */
#define CAM2_MASK (1 << 7)
/* Write 0 to enable VIP */
#define CAM1_MASK (1 << 8)
/* Write 0 to enable VIP */
#define CAM0_MASK (1 << 9)
/* Write 0 to enable TS */
#define SSP0_CS2_MASK (1 << 10)
/* Write 0 to enable FSMC PNOR */
#define MCIF_MASK (1 << 11)
/* Write 0 to enable CLCD */
#define ARM_TRACE_MASK (1 << 12)
/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
#define MIPHY_DBG_MASK (1 << 13)
/*
* Pad multiplexing for making all pads as gpio's. This is done to override the
* values passed from bootloader and start from scratch.
*/
static const unsigned pads_as_gpio_pins[] = { 251 };
static struct spear_muxreg pads_as_gpio_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PADS_AS_GPIO_REG0_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_4,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_8,
.mask = PADS_AS_GPIO_REG7_MASK,
.val = 0x0,
},
};
static struct spear_modemux pads_as_gpio_modemux[] = {
{
.muxregs = pads_as_gpio_muxreg,
.nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
},
};
static struct spear_pingroup pads_as_gpio_pingroup = {
.name = "pads_as_gpio_grp",
.pins = pads_as_gpio_pins,
.npins = ARRAY_SIZE(pads_as_gpio_pins),
.modemuxs = pads_as_gpio_modemux,
.nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
};
static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
static struct spear_function pads_as_gpio_function = {
.name = "pads_as_gpio",
.groups = pads_as_gpio_grps,
.ngroups = ARRAY_SIZE(pads_as_gpio_grps),
};
/* Pad multiplexing for fsmc_8bit device */
static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
241, 242, 243, 244, 245, 246, 247, 248, 249 };
static struct spear_muxreg fsmc_8bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_8,
.mask = FSMC_8BIT_REG7_MASK,
.val = FSMC_8BIT_REG7_MASK,
}
};
static struct spear_modemux fsmc_8bit_modemux[] = {
{
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
},
};
static struct spear_pingroup fsmc_8bit_pingroup = {
.name = "fsmc_8bit_grp",
.pins = fsmc_8bit_pins,
.npins = ARRAY_SIZE(fsmc_8bit_pins),
.modemuxs = fsmc_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
};
/* Pad multiplexing for fsmc_16bit device */
static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
static struct spear_muxreg fsmc_16bit_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_ROW_COL_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
.val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
},
};
static struct spear_modemux fsmc_16bit_modemux[] = {
{
.muxregs = fsmc_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
},
};
static struct spear_pingroup fsmc_16bit_pingroup = {
.name = "fsmc_16bit_grp",
.pins = fsmc_16bit_pins,
.npins = ARRAY_SIZE(fsmc_16bit_pins),
.modemuxs = fsmc_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
};
/* pad multiplexing for fsmc_pnor device */
static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
215, 216, 217 };
static struct spear_muxreg fsmc_pnor_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = MCIF_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
.val = FSMC_PNOR_AND_MCIF_REG6_MASK,
},
};
static struct spear_modemux fsmc_pnor_modemux[] = {
{
.muxregs = fsmc_pnor_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
},
};
static struct spear_pingroup fsmc_pnor_pingroup = {
.name = "fsmc_pnor_grp",
.pins = fsmc_pnor_pins,
.npins = ARRAY_SIZE(fsmc_pnor_pins),
.modemuxs = fsmc_pnor_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
"fsmc_pnor_grp" };
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* pad multiplexing for keyboard rows-cols device */
static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10 };
static struct spear_muxreg keyboard_row_col_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_ROW_COL_MASK,
.val = KBD_ROW_COL_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
.val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
},
};
static struct spear_modemux keyboard_row_col_modemux[] = {
{
.muxregs = keyboard_row_col_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
},
};
static struct spear_pingroup keyboard_row_col_pingroup = {
.name = "keyboard_row_col_grp",
.pins = keyboard_row_col_pins,
.npins = ARRAY_SIZE(keyboard_row_col_pins),
.modemuxs = keyboard_row_col_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
};
/* pad multiplexing for keyboard col5 device */
static const unsigned keyboard_col5_pins[] = { 17 };
static struct spear_muxreg keyboard_col5_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_COL5_MASK,
.val = KBD_COL5_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM1_AND_KBD_COL5_REG0_MASK,
.val = PWM1_AND_KBD_COL5_REG0_MASK,
},
};
static struct spear_modemux keyboard_col5_modemux[] = {
{
.muxregs = keyboard_col5_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
},
};
static struct spear_pingroup keyboard_col5_pingroup = {
.name = "keyboard_col5_grp",
.pins = keyboard_col5_pins,
.npins = ARRAY_SIZE(keyboard_col5_pins),
.modemuxs = keyboard_col5_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
};
static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
"keyboard_col5_grp" };
static struct spear_function keyboard_function = {
.name = "keyboard",
.groups = keyboard_grps,
.ngroups = ARRAY_SIZE(keyboard_grps),
};
/* pad multiplexing for spdif_in device */
static const unsigned spdif_in_pins[] = { 19 };
static struct spear_muxreg spdif_in_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = SPDIF_IN_REG0_MASK,
.val = SPDIF_IN_REG0_MASK,
},
};
static struct spear_modemux spdif_in_modemux[] = {
{
.muxregs = spdif_in_muxreg,
.nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
},
};
static struct spear_pingroup spdif_in_pingroup = {
.name = "spdif_in_grp",
.pins = spdif_in_pins,
.npins = ARRAY_SIZE(spdif_in_pins),
.modemuxs = spdif_in_modemux,
.nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
};
static const char *const spdif_in_grps[] = { "spdif_in_grp" };
static struct spear_function spdif_in_function = {
.name = "spdif_in",
.groups = spdif_in_grps,
.ngroups = ARRAY_SIZE(spdif_in_grps),
};
/* pad multiplexing for spdif_out device */
static const unsigned spdif_out_pins[] = { 137 };
static struct spear_muxreg spdif_out_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = SPDIF_OUT_REG4_MASK,
.val = SPDIF_OUT_REG4_MASK,
}, {
.reg = PERIP_CFG,
.mask = SPDIF_OUT_ENB_MASK,
.val = SPDIF_OUT_ENB_MASK,
}
};
static struct spear_modemux spdif_out_modemux[] = {
{
.muxregs = spdif_out_muxreg,
.nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
},
};
static struct spear_pingroup spdif_out_pingroup = {
.name = "spdif_out_grp",
.pins = spdif_out_pins,
.npins = ARRAY_SIZE(spdif_out_pins),
.modemuxs = spdif_out_modemux,
.nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
};
static const char *const spdif_out_grps[] = { "spdif_out_grp" };
static struct spear_function spdif_out_function = {
.name = "spdif_out",
.groups = spdif_out_grps,
.ngroups = ARRAY_SIZE(spdif_out_grps),
};
/* pad multiplexing for gpt_0_1 device */
static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
static struct spear_muxreg gpt_0_1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
.val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = UART0_ENH_AND_GPT_REG0_MASK |
PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
.val = UART0_ENH_AND_GPT_REG0_MASK |
PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
},
};
static struct spear_modemux gpt_0_1_modemux[] = {
{
.muxregs = gpt_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
},
};
static struct spear_pingroup gpt_0_1_pingroup = {
.name = "gpt_0_1_grp",
.pins = gpt_0_1_pins,
.npins = ARRAY_SIZE(gpt_0_1_pins),
.modemuxs = gpt_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
};
static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
static struct spear_function gpt_0_1_function = {
.name = "gpt_0_1",
.groups = gpt_0_1_grps,
.ngroups = ARRAY_SIZE(gpt_0_1_grps),
};
/* pad multiplexing for pwm0 device */
static const unsigned pwm0_pins[] = { 24 };
static struct spear_muxreg pwm0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM0_AND_SSP0_CS1_REG0_MASK,
.val = PWM0_AND_SSP0_CS1_REG0_MASK,
},
};
static struct spear_modemux pwm0_modemux[] = {
{
.muxregs = pwm0_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_muxreg),
},
};
static struct spear_pingroup pwm0_pingroup = {
.name = "pwm0_grp",
.pins = pwm0_pins,
.npins = ARRAY_SIZE(pwm0_pins),
.modemuxs = pwm0_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_modemux),
};
/* pad multiplexing for pwm1 device */
static const unsigned pwm1_pins[] = { 17 };
static struct spear_muxreg pwm1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_COL5_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM1_AND_KBD_COL5_REG0_MASK,
.val = PWM1_AND_KBD_COL5_REG0_MASK,
},
};
static struct spear_modemux pwm1_modemux[] = {
{
.muxregs = pwm1_muxreg,
.nmuxregs = ARRAY_SIZE(pwm1_muxreg),
},
};
static struct spear_pingroup pwm1_pingroup = {
.name = "pwm1_grp",
.pins = pwm1_pins,
.npins = ARRAY_SIZE(pwm1_pins),
.modemuxs = pwm1_modemux,
.nmodemuxs = ARRAY_SIZE(pwm1_modemux),
};
/* pad multiplexing for pwm2 device */
static const unsigned pwm2_pins[] = { 21 };
static struct spear_muxreg pwm2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT0_TMR0_CPT_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
.val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
},
};
static struct spear_modemux pwm2_modemux[] = {
{
.muxregs = pwm2_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_muxreg),
},
};
static struct spear_pingroup pwm2_pingroup = {
.name = "pwm2_grp",
.pins = pwm2_pins,
.npins = ARRAY_SIZE(pwm2_pins),
.modemuxs = pwm2_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_modemux),
};
/* pad multiplexing for pwm3 device */
static const unsigned pwm3_pins[] = { 22 };
static struct spear_muxreg pwm3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT0_TMR1_CLK_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
.val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
},
};
static struct spear_modemux pwm3_modemux[] = {
{
.muxregs = pwm3_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
},
};
static struct spear_pingroup pwm3_pingroup = {
.name = "pwm3_grp",
.pins = pwm3_pins,
.npins = ARRAY_SIZE(pwm3_pins),
.modemuxs = pwm3_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_modemux),
};
static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp" };
static struct spear_function pwm_function = {
.name = "pwm",
.groups = pwm_grps,
.ngroups = ARRAY_SIZE(pwm_grps),
};
/* pad multiplexing for vip_mux device */
static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
static struct spear_muxreg vip_mux_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_REG1_MASK,
.val = VIP_REG1_MASK,
},
};
static struct spear_modemux vip_mux_modemux[] = {
{
.muxregs = vip_mux_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
},
};
static struct spear_pingroup vip_mux_pingroup = {
.name = "vip_mux_grp",
.pins = vip_mux_pins,
.npins = ARRAY_SIZE(vip_mux_pins),
.modemuxs = vip_mux_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
};
/* pad multiplexing for vip_mux_cam0 (disables cam0) device */
static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
73, 74, 75 };
static struct spear_muxreg vip_mux_cam0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM0_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM0_REG2_MASK,
.val = VIP_AND_CAM0_REG2_MASK,
},
};
static struct spear_modemux vip_mux_cam0_modemux[] = {
{
.muxregs = vip_mux_cam0_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
},
};
static struct spear_pingroup vip_mux_cam0_pingroup = {
.name = "vip_mux_cam0_grp",
.pins = vip_mux_cam0_pins,
.npins = ARRAY_SIZE(vip_mux_cam0_pins),
.modemuxs = vip_mux_cam0_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
};
/* pad multiplexing for vip_mux_cam1 (disables cam1) device */
static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
62, 63, 64 };
static struct spear_muxreg vip_mux_cam1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM1_REG1_MASK,
.val = VIP_AND_CAM1_REG1_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM1_REG2_MASK,
.val = VIP_AND_CAM1_REG2_MASK,
},
};
static struct spear_modemux vip_mux_cam1_modemux[] = {
{
.muxregs = vip_mux_cam1_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
},
};
static struct spear_pingroup vip_mux_cam1_pingroup = {
.name = "vip_mux_cam1_grp",
.pins = vip_mux_cam1_pins,
.npins = ARRAY_SIZE(vip_mux_cam1_pins),
.modemuxs = vip_mux_cam1_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
};
/* pad multiplexing for vip_mux_cam2 (disables cam2) device */
static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53 };
static struct spear_muxreg vip_mux_cam2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM2_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM2_REG1_MASK,
.val = VIP_AND_CAM2_REG1_MASK,
},
};
static struct spear_modemux vip_mux_cam2_modemux[] = {
{
.muxregs = vip_mux_cam2_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
},
};
static struct spear_pingroup vip_mux_cam2_pingroup = {
.name = "vip_mux_cam2_grp",
.pins = vip_mux_cam2_pins,
.npins = ARRAY_SIZE(vip_mux_cam2_pins),
.modemuxs = vip_mux_cam2_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
};
/* pad multiplexing for vip_mux_cam3 (disables cam3) device */
static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34 };
static struct spear_muxreg vip_mux_cam3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM3_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = VIP_AND_CAM3_REG0_MASK,
.val = VIP_AND_CAM3_REG0_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM3_REG1_MASK,
.val = VIP_AND_CAM3_REG1_MASK,
},
};
static struct spear_modemux vip_mux_cam3_modemux[] = {
{
.muxregs = vip_mux_cam3_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
},
};
static struct spear_pingroup vip_mux_cam3_pingroup = {
.name = "vip_mux_cam3_grp",
.pins = vip_mux_cam3_pins,
.npins = ARRAY_SIZE(vip_mux_cam3_pins),
.modemuxs = vip_mux_cam3_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
};
static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
"vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
static struct spear_function vip_function = {
.name = "vip",
.groups = vip_grps,
.ngroups = ARRAY_SIZE(vip_grps),
};
/* pad multiplexing for cam0 device */
static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
};
static struct spear_muxreg cam0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM0_MASK,
.val = CAM0_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM0_REG2_MASK,
.val = VIP_AND_CAM0_REG2_MASK,
},
};
static struct spear_modemux cam0_modemux[] = {
{
.muxregs = cam0_muxreg,
.nmuxregs = ARRAY_SIZE(cam0_muxreg),
},
};
static struct spear_pingroup cam0_pingroup = {
.name = "cam0_grp",
.pins = cam0_pins,
.npins = ARRAY_SIZE(cam0_pins),
.modemuxs = cam0_modemux,
.nmodemuxs = ARRAY_SIZE(cam0_modemux),
};
static const char *const cam0_grps[] = { "cam0_grp" };
static struct spear_function cam0_function = {
.name = "cam0",
.groups = cam0_grps,
.ngroups = ARRAY_SIZE(cam0_grps),
};
/* pad multiplexing for cam1 device */
static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
};
static struct spear_muxreg cam1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM1_MASK,
.val = CAM1_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM1_REG1_MASK,
.val = VIP_AND_CAM1_REG1_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM1_REG2_MASK,
.val = VIP_AND_CAM1_REG2_MASK,
},
};
static struct spear_modemux cam1_modemux[] = {
{
.muxregs = cam1_muxreg,
.nmuxregs = ARRAY_SIZE(cam1_muxreg),
},
};
static struct spear_pingroup cam1_pingroup = {
.name = "cam1_grp",
.pins = cam1_pins,
.npins = ARRAY_SIZE(cam1_pins),
.modemuxs = cam1_modemux,
.nmodemuxs = ARRAY_SIZE(cam1_modemux),
};
static const char *const cam1_grps[] = { "cam1_grp" };
static struct spear_function cam1_function = {
.name = "cam1",
.groups = cam1_grps,
.ngroups = ARRAY_SIZE(cam1_grps),
};
/* pad multiplexing for cam2 device */
static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
};
static struct spear_muxreg cam2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM2_MASK,
.val = CAM2_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM2_REG1_MASK,
.val = VIP_AND_CAM2_REG1_MASK,
},
};
static struct spear_modemux cam2_modemux[] = {
{
.muxregs = cam2_muxreg,
.nmuxregs = ARRAY_SIZE(cam2_muxreg),
},
};
static struct spear_pingroup cam2_pingroup = {
.name = "cam2_grp",
.pins = cam2_pins,
.npins = ARRAY_SIZE(cam2_pins),
.modemuxs = cam2_modemux,
.nmodemuxs = ARRAY_SIZE(cam2_modemux),
};
static const char *const cam2_grps[] = { "cam2_grp" };
static struct spear_function cam2_function = {
.name = "cam2",
.groups = cam2_grps,
.ngroups = ARRAY_SIZE(cam2_grps),
};
/* pad multiplexing for cam3 device */
static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
};
static struct spear_muxreg cam3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM3_MASK,
.val = CAM3_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = VIP_AND_CAM3_REG0_MASK,
.val = VIP_AND_CAM3_REG0_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM3_REG1_MASK,
.val = VIP_AND_CAM3_REG1_MASK,
},
};
static struct spear_modemux cam3_modemux[] = {
{
.muxregs = cam3_muxreg,
.nmuxregs = ARRAY_SIZE(cam3_muxreg),
},
};
static struct spear_pingroup cam3_pingroup = {
.name = "cam3_grp",
.pins = cam3_pins,
.npins = ARRAY_SIZE(cam3_pins),
.modemuxs = cam3_modemux,
.nmodemuxs = ARRAY_SIZE(cam3_modemux),
};
static const char *const cam3_grps[] = { "cam3_grp" };
static struct spear_function cam3_function = {
.name = "cam3",
.groups = cam3_grps,
.ngroups = ARRAY_SIZE(cam3_grps),
};
/* pad multiplexing for smi device */
static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
static struct spear_muxreg smi_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = SMI_REG2_MASK,
.val = SMI_REG2_MASK,
},
};
static struct spear_modemux smi_modemux[] = {
{
.muxregs = smi_muxreg,
.nmuxregs = ARRAY_SIZE(smi_muxreg),
},
};
static struct spear_pingroup smi_pingroup = {
.name = "smi_grp",
.pins = smi_pins,
.npins = ARRAY_SIZE(smi_pins),
.modemuxs = smi_modemux,
.nmodemuxs = ARRAY_SIZE(smi_modemux),
};
static const char *const smi_grps[] = { "smi_grp" };
static struct spear_function smi_function = {
.name = "smi",
.groups = smi_grps,
.ngroups = ARRAY_SIZE(smi_grps),
};
/* pad multiplexing for ssp0 device */
static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
static struct spear_muxreg ssp0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = SSP0_REG2_MASK,
.val = SSP0_REG2_MASK,
},
};
static struct spear_modemux ssp0_modemux[] = {
{
.muxregs = ssp0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
},
};
static struct spear_pingroup ssp0_pingroup = {
.name = "ssp0_grp",
.pins = ssp0_pins,
.npins = ARRAY_SIZE(ssp0_pins),
.modemuxs = ssp0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
};
/* pad multiplexing for ssp0_cs1 device */
static const unsigned ssp0_cs1_pins[] = { 24 };
static struct spear_muxreg ssp0_cs1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS1_MASK,
.val = SSP0_CS1_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM0_AND_SSP0_CS1_REG0_MASK,
.val = PWM0_AND_SSP0_CS1_REG0_MASK,
},
};
static struct spear_modemux ssp0_cs1_modemux[] = {
{
.muxregs = ssp0_cs1_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
},
};
static struct spear_pingroup ssp0_cs1_pingroup = {
.name = "ssp0_cs1_grp",
.pins = ssp0_cs1_pins,
.npins = ARRAY_SIZE(ssp0_cs1_pins),
.modemuxs = ssp0_cs1_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
};
/* pad multiplexing for ssp0_cs2 device */
static const unsigned ssp0_cs2_pins[] = { 85 };
static struct spear_muxreg ssp0_cs2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS2_MASK,
.val = SSP0_CS2_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = TS_AND_SSP0_CS2_REG2_MASK,
.val = TS_AND_SSP0_CS2_REG2_MASK,
},
};
static struct spear_modemux ssp0_cs2_modemux[] = {
{
.muxregs = ssp0_cs2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
},
};
static struct spear_pingroup ssp0_cs2_pingroup = {
.name = "ssp0_cs2_grp",
.pins = ssp0_cs2_pins,
.npins = ARRAY_SIZE(ssp0_cs2_pins),
.modemuxs = ssp0_cs2_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
};
/* pad multiplexing for ssp0_cs3 device */
static const unsigned ssp0_cs3_pins[] = { 132 };
static struct spear_muxreg ssp0_cs3_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = SSP0_CS3_REG4_MASK,
.val = SSP0_CS3_REG4_MASK,
},
};
static struct spear_modemux ssp0_cs3_modemux[] = {
{
.muxregs = ssp0_cs3_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
},
};
static struct spear_pingroup ssp0_cs3_pingroup = {
.name = "ssp0_cs3_grp",
.pins = ssp0_cs3_pins,
.npins = ARRAY_SIZE(ssp0_cs3_pins),
.modemuxs = ssp0_cs3_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
};
static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp" };
static struct spear_function ssp0_function = {
.name = "ssp0",
.groups = ssp0_grps,
.ngroups = ARRAY_SIZE(ssp0_grps),
};
/* pad multiplexing for uart0 device */
static const unsigned uart0_pins[] = { 86, 87 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = UART0_REG2_MASK,
.val = UART0_REG2_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
static struct spear_pingroup uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
/* pad multiplexing for uart0_enh device */
static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
static struct spear_muxreg uart0_enh_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = UART0_ENH_AND_GPT_REG0_MASK,
.val = UART0_ENH_AND_GPT_REG0_MASK,
},
};
static struct spear_modemux uart0_enh_modemux[] = {
{
.muxregs = uart0_enh_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
},
};
static struct spear_pingroup uart0_enh_pingroup = {
.name = "uart0_enh_grp",
.pins = uart0_enh_pins,
.npins = ARRAY_SIZE(uart0_enh_pins),
.modemuxs = uart0_enh_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
static struct spear_function uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* pad multiplexing for uart1 device */
static const unsigned uart1_pins[] = { 88, 89 };
static struct spear_muxreg uart1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = UART1_REG2_MASK,
.val = UART1_REG2_MASK,
},
};
static struct spear_modemux uart1_modemux[] = {
{
.muxregs = uart1_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
},
};
static struct spear_pingroup uart1_pingroup = {
.name = "uart1_grp",
.pins = uart1_pins,
.npins = ARRAY_SIZE(uart1_pins),
.modemuxs = uart1_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
};
static const char *const uart1_grps[] = { "uart1_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* pad multiplexing for i2s_in device */
static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
static struct spear_muxreg i2s_in_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = I2S_IN_REG2_MASK,
.val = I2S_IN_REG2_MASK,
}, {
.reg = PAD_FUNCTION_EN_4,
.mask = I2S_IN_REG3_MASK,
.val = I2S_IN_REG3_MASK,
},
};
static struct spear_modemux i2s_in_modemux[] = {
{
.muxregs = i2s_in_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
},
};
static struct spear_pingroup i2s_in_pingroup = {
.name = "i2s_in_grp",
.pins = i2s_in_pins,
.npins = ARRAY_SIZE(i2s_in_pins),
.modemuxs = i2s_in_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
};
/* pad multiplexing for i2s_out device */
static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
static struct spear_muxreg i2s_out_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_4,
.mask = I2S_OUT_REG3_MASK,
.val = I2S_OUT_REG3_MASK,
},
};
static struct spear_modemux i2s_out_modemux[] = {
{
.muxregs = i2s_out_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
},
};
static struct spear_pingroup i2s_out_pingroup = {
.name = "i2s_out_grp",
.pins = i2s_out_pins,
.npins = ARRAY_SIZE(i2s_out_pins),
.modemuxs = i2s_out_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
};
static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
static struct spear_function i2s_function = {
.name = "i2s",
.groups = i2s_grps,
.ngroups = ARRAY_SIZE(i2s_grps),
};
/* pad multiplexing for gmac device */
static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
126, 127, 128, 129, 130, 131 };
#define GMAC_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_4, \
.mask = GMAC_REG3_MASK, \
.val = GMAC_REG3_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_5, \
.mask = GMAC_REG4_MASK, \
.val = GMAC_REG4_MASK, \
}
/* pad multiplexing for gmii device */
static struct spear_muxreg gmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_GMII_VAL,
},
};
static struct spear_modemux gmii_modemux[] = {
{
.muxregs = gmii_muxreg,
.nmuxregs = ARRAY_SIZE(gmii_muxreg),
},
};
static struct spear_pingroup gmii_pingroup = {
.name = "gmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = gmii_modemux,
.nmodemuxs = ARRAY_SIZE(gmii_modemux),
};
/* pad multiplexing for rgmii device */
static struct spear_muxreg rgmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_RGMII_VAL,
},
};
static struct spear_modemux rgmii_modemux[] = {
{
.muxregs = rgmii_muxreg,
.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
},
};
static struct spear_pingroup rgmii_pingroup = {
.name = "rgmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = rgmii_modemux,
.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
};
/* pad multiplexing for rmii device */
static struct spear_muxreg rmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_RMII_VAL,
},
};
static struct spear_modemux rmii_modemux[] = {
{
.muxregs = rmii_muxreg,
.nmuxregs = ARRAY_SIZE(rmii_muxreg),
},
};
static struct spear_pingroup rmii_pingroup = {
.name = "rmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = rmii_modemux,
.nmodemuxs = ARRAY_SIZE(rmii_modemux),
};
/* pad multiplexing for sgmii device */
static struct spear_muxreg sgmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_SGMII_VAL,
},
};
static struct spear_modemux sgmii_modemux[] = {
{
.muxregs = sgmii_muxreg,
.nmuxregs = ARRAY_SIZE(sgmii_muxreg),
},
};
static struct spear_pingroup sgmii_pingroup = {
.name = "sgmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = sgmii_modemux,
.nmodemuxs = ARRAY_SIZE(sgmii_modemux),
};
static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
"sgmii_grp" };
static struct spear_function gmac_function = {
.name = "gmac",
.groups = gmac_grps,
.ngroups = ARRAY_SIZE(gmac_grps),
};
/* pad multiplexing for i2c0 device */
static const unsigned i2c0_pins[] = { 133, 134 };
static struct spear_muxreg i2c0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = I2C0_REG4_MASK,
.val = I2C0_REG4_MASK,
},
};
static struct spear_modemux i2c0_modemux[] = {
{
.muxregs = i2c0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
},
};
static struct spear_pingroup i2c0_pingroup = {
.name = "i2c0_grp",
.pins = i2c0_pins,
.npins = ARRAY_SIZE(i2c0_pins),
.modemuxs = i2c0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
};
static const char *const i2c0_grps[] = { "i2c0_grp" };
static struct spear_function i2c0_function = {
.name = "i2c0",
.groups = i2c0_grps,
.ngroups = ARRAY_SIZE(i2c0_grps),
};
/* pad multiplexing for i2c1 device */
static const unsigned i2c1_pins[] = { 18, 23 };
static struct spear_muxreg i2c1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = I2C1_REG0_MASK,
.val = I2C1_REG0_MASK,
},
};
static struct spear_modemux i2c1_modemux[] = {
{
.muxregs = i2c1_muxreg,
.nmuxregs = ARRAY_SIZE(i2c1_muxreg),
},
};
static struct spear_pingroup i2c1_pingroup = {
.name = "i2c1_grp",
.pins = i2c1_pins,
.npins = ARRAY_SIZE(i2c1_pins),
.modemuxs = i2c1_modemux,
.nmodemuxs = ARRAY_SIZE(i2c1_modemux),
};
static const char *const i2c1_grps[] = { "i2c1_grp" };
static struct spear_function i2c1_function = {
.name = "i2c1",
.groups = i2c1_grps,
.ngroups = ARRAY_SIZE(i2c1_grps),
};
/* pad multiplexing for cec0 device */
static const unsigned cec0_pins[] = { 135 };
static struct spear_muxreg cec0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = CEC0_REG4_MASK,
.val = CEC0_REG4_MASK,
},
};
static struct spear_modemux cec0_modemux[] = {
{
.muxregs = cec0_muxreg,
.nmuxregs = ARRAY_SIZE(cec0_muxreg),
},
};
static struct spear_pingroup cec0_pingroup = {
.name = "cec0_grp",
.pins = cec0_pins,
.npins = ARRAY_SIZE(cec0_pins),
.modemuxs = cec0_modemux,
.nmodemuxs = ARRAY_SIZE(cec0_modemux),
};
static const char *const cec0_grps[] = { "cec0_grp" };
static struct spear_function cec0_function = {
.name = "cec0",
.groups = cec0_grps,
.ngroups = ARRAY_SIZE(cec0_grps),
};
/* pad multiplexing for cec1 device */
static const unsigned cec1_pins[] = { 136 };
static struct spear_muxreg cec1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = CEC1_REG4_MASK,
.val = CEC1_REG4_MASK,
},
};
static struct spear_modemux cec1_modemux[] = {
{
.muxregs = cec1_muxreg,
.nmuxregs = ARRAY_SIZE(cec1_muxreg),
},
};
static struct spear_pingroup cec1_pingroup = {
.name = "cec1_grp",
.pins = cec1_pins,
.npins = ARRAY_SIZE(cec1_pins),
.modemuxs = cec1_modemux,
.nmodemuxs = ARRAY_SIZE(cec1_modemux),
};
static const char *const cec1_grps[] = { "cec1_grp" };
static struct spear_function cec1_function = {
.name = "cec1",
.groups = cec1_grps,
.ngroups = ARRAY_SIZE(cec1_grps),
};
/* pad multiplexing for mcif devices */
static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 237 };
#define MCIF_MUXREG \
{ \
.reg = PAD_SHARED_IP_EN_1, \
.mask = MCIF_MASK, \
.val = MCIF_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_7, \
.mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
.val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_8, \
.mask = MCIF_REG7_MASK, \
.val = MCIF_REG7_MASK, \
}
/* Pad multiplexing for sdhci device */
static struct spear_muxreg sdhci_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_SD,
},
};
static struct spear_modemux sdhci_modemux[] = {
{
.muxregs = sdhci_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
},
};
static struct spear_pingroup sdhci_pingroup = {
.name = "sdhci_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = sdhci_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* Pad multiplexing for cf device */
static struct spear_muxreg cf_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_CF,
},
};
static struct spear_modemux cf_modemux[] = {
{
.muxregs = cf_muxreg,
.nmuxregs = ARRAY_SIZE(cf_muxreg),
},
};
static struct spear_pingroup cf_pingroup = {
.name = "cf_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = cf_modemux,
.nmodemuxs = ARRAY_SIZE(cf_modemux),
};
static const char *const cf_grps[] = { "cf_grp" };
static struct spear_function cf_function = {
.name = "cf",
.groups = cf_grps,
.ngroups = ARRAY_SIZE(cf_grps),
};
/* Pad multiplexing for xd device */
static struct spear_muxreg xd_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_XD,
},
};
static struct spear_modemux xd_modemux[] = {
{
.muxregs = xd_muxreg,
.nmuxregs = ARRAY_SIZE(xd_muxreg),
},
};
static struct spear_pingroup xd_pingroup = {
.name = "xd_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = xd_modemux,
.nmodemuxs = ARRAY_SIZE(xd_modemux),
};
static const char *const xd_grps[] = { "xd_grp" };
static struct spear_function xd_function = {
.name = "xd",
.groups = xd_grps,
.ngroups = ARRAY_SIZE(xd_grps),
};
/* pad multiplexing for clcd device */
static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
188, 189, 190, 191 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
.val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = CLCD_AND_ARM_TRACE_REG5_MASK,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = CLCD_AND_ARM_TRACE_REG6_MASK,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
/* pad multiplexing for arm_trace device */
static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
193, 194, 195, 196, 197, 198, 199, 200 };
static struct spear_muxreg arm_trace_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK,
.val = ARM_TRACE_MASK,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_AND_ARM_TRACE_REG4_MASK,
.val = CLCD_AND_ARM_TRACE_REG4_MASK,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = CLCD_AND_ARM_TRACE_REG5_MASK,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = CLCD_AND_ARM_TRACE_REG6_MASK,
},
};
static struct spear_modemux arm_trace_modemux[] = {
{
.muxregs = arm_trace_muxreg,
.nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
},
};
static struct spear_pingroup arm_trace_pingroup = {
.name = "arm_trace_grp",
.pins = arm_trace_pins,
.npins = ARRAY_SIZE(arm_trace_pins),
.modemuxs = arm_trace_modemux,
.nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
};
static const char *const arm_trace_grps[] = { "arm_trace_grp" };
static struct spear_function arm_trace_function = {
.name = "arm_trace",
.groups = arm_trace_grps,
.ngroups = ARRAY_SIZE(arm_trace_grps),
};
/* pad multiplexing for miphy_dbg device */
static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
static struct spear_muxreg miphy_dbg_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = MIPHY_DBG_MASK,
.val = MIPHY_DBG_MASK,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
.val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
},
};
static struct spear_modemux miphy_dbg_modemux[] = {
{
.muxregs = miphy_dbg_muxreg,
.nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
},
};
static struct spear_pingroup miphy_dbg_pingroup = {
.name = "miphy_dbg_grp",
.pins = miphy_dbg_pins,
.npins = ARRAY_SIZE(miphy_dbg_pins),
.modemuxs = miphy_dbg_modemux,
.nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
};
static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
static struct spear_function miphy_dbg_function = {
.name = "miphy_dbg",
.groups = miphy_dbg_grps,
.ngroups = ARRAY_SIZE(miphy_dbg_grps),
};
/* pad multiplexing for pcie device */
static const unsigned pcie_pins[] = { 250 };
static struct spear_muxreg pcie_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_PCIE_CFG_MASK,
.val = PCIE_CFG_VAL,
},
};
static struct spear_modemux pcie_modemux[] = {
{
.muxregs = pcie_muxreg,
.nmuxregs = ARRAY_SIZE(pcie_muxreg),
},
};
static struct spear_pingroup pcie_pingroup = {
.name = "pcie_grp",
.pins = pcie_pins,
.npins = ARRAY_SIZE(pcie_pins),
.modemuxs = pcie_modemux,
.nmodemuxs = ARRAY_SIZE(pcie_modemux),
};
static const char *const pcie_grps[] = { "pcie_grp" };
static struct spear_function pcie_function = {
.name = "pcie",
.groups = pcie_grps,
.ngroups = ARRAY_SIZE(pcie_grps),
};
/* pad multiplexing for sata device */
static const unsigned sata_pins[] = { 250 };
static struct spear_muxreg sata_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_PCIE_CFG_MASK,
.val = SATA_CFG_VAL,
},
};
static struct spear_modemux sata_modemux[] = {
{
.muxregs = sata_muxreg,
.nmuxregs = ARRAY_SIZE(sata_muxreg),
},
};
static struct spear_pingroup sata_pingroup = {
.name = "sata_grp",
.pins = sata_pins,
.npins = ARRAY_SIZE(sata_pins),
.modemuxs = sata_modemux,
.nmodemuxs = ARRAY_SIZE(sata_modemux),
};
static const char *const sata_grps[] = { "sata_grp" };
static struct spear_function sata_function = {
.name = "sata",
.groups = sata_grps,
.ngroups = ARRAY_SIZE(sata_grps),
};
/* pingroups */
static struct spear_pingroup *spear1340_pingroups[] = {
&pads_as_gpio_pingroup,
&fsmc_8bit_pingroup,
&fsmc_16bit_pingroup,
&fsmc_pnor_pingroup,
&keyboard_row_col_pingroup,
&keyboard_col5_pingroup,
&spdif_in_pingroup,
&spdif_out_pingroup,
&gpt_0_1_pingroup,
&pwm0_pingroup,
&pwm1_pingroup,
&pwm2_pingroup,
&pwm3_pingroup,
&vip_mux_pingroup,
&vip_mux_cam0_pingroup,
&vip_mux_cam1_pingroup,
&vip_mux_cam2_pingroup,
&vip_mux_cam3_pingroup,
&cam0_pingroup,
&cam1_pingroup,
&cam2_pingroup,
&cam3_pingroup,
&smi_pingroup,
&ssp0_pingroup,
&ssp0_cs1_pingroup,
&ssp0_cs2_pingroup,
&ssp0_cs3_pingroup,
&uart0_pingroup,
&uart0_enh_pingroup,
&uart1_pingroup,
&i2s_in_pingroup,
&i2s_out_pingroup,
&gmii_pingroup,
&rgmii_pingroup,
&rmii_pingroup,
&sgmii_pingroup,
&i2c0_pingroup,
&i2c1_pingroup,
&cec0_pingroup,
&cec1_pingroup,
&sdhci_pingroup,
&cf_pingroup,
&xd_pingroup,
&clcd_pingroup,
&arm_trace_pingroup,
&miphy_dbg_pingroup,
&pcie_pingroup,
&sata_pingroup,
};
/* functions */
static struct spear_function *spear1340_functions[] = {
&pads_as_gpio_function,
&fsmc_function,
&keyboard_function,
&spdif_in_function,
&spdif_out_function,
&gpt_0_1_function,
&pwm_function,
&vip_function,
&cam0_function,
&cam1_function,
&cam2_function,
&cam3_function,
&smi_function,
&ssp0_function,
&uart0_function,
&uart1_function,
&i2s_function,
&gmac_function,
&i2c0_function,
&i2c1_function,
&cec0_function,
&cec1_function,
&sdhci_function,
&cf_function,
&xd_function,
&clcd_function,
&arm_trace_function,
&miphy_dbg_function,
&pcie_function,
&sata_function,
};
static struct spear_pinctrl_machdata spear1340_machdata = {
.pins = spear1340_pins,
.npins = ARRAY_SIZE(spear1340_pins),
.groups = spear1340_pingroups,
.ngroups = ARRAY_SIZE(spear1340_pingroups),
.functions = spear1340_functions,
.nfunctions = ARRAY_SIZE(spear1340_functions),
.modes_supported = false,
};
static struct of_device_id spear1340_pinctrl_of_match[] __devinitdata = {
{
.compatible = "st,spear1340-pinmux",
},
{},
};
static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev)
{
return spear_pinctrl_probe(pdev, &spear1340_machdata);
}
static int __devexit spear1340_pinctrl_remove(struct platform_device *pdev)
{
return spear_pinctrl_remove(pdev);
}
static struct platform_driver spear1340_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = spear1340_pinctrl_of_match,
},
.probe = spear1340_pinctrl_probe,
.remove = __devexit_p(spear1340_pinctrl_remove),
};
static int __init spear1340_pinctrl_init(void)
{
return platform_driver_register(&spear1340_pinctrl_driver);
}
arch_initcall(spear1340_pinctrl_init);
static void __exit spear1340_pinctrl_exit(void)
{
platform_driver_unregister(&spear1340_pinctrl_driver);
}
module_exit(spear1340_pinctrl_exit);
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match);
drivers/pinctrl/spear/pinctrl-spear3xx.c
View file @ 30b84288
......@@ -15,108 +15,7 @@
/* pins */
static const struct pinctrl_pin_desc spear3xx_pins[] = {
PINCTRL_PIN(0, "PLGPIO0"),
PINCTRL_PIN(1, "PLGPIO1"),
PINCTRL_PIN(2, "PLGPIO2"),
PINCTRL_PIN(3, "PLGPIO3"),
PINCTRL_PIN(4, "PLGPIO4"),
PINCTRL_PIN(5, "PLGPIO5"),
PINCTRL_PIN(6, "PLGPIO6"),
PINCTRL_PIN(7, "PLGPIO7"),
PINCTRL_PIN(8, "PLGPIO8"),
PINCTRL_PIN(9, "PLGPIO9"),
PINCTRL_PIN(10, "PLGPIO10"),
PINCTRL_PIN(11, "PLGPIO11"),
PINCTRL_PIN(12, "PLGPIO12"),
PINCTRL_PIN(13, "PLGPIO13"),
PINCTRL_PIN(14, "PLGPIO14"),
PINCTRL_PIN(15, "PLGPIO15"),
PINCTRL_PIN(16, "PLGPIO16"),
PINCTRL_PIN(17, "PLGPIO17"),
PINCTRL_PIN(18, "PLGPIO18"),
PINCTRL_PIN(19, "PLGPIO19"),
PINCTRL_PIN(20, "PLGPIO20"),
PINCTRL_PIN(21, "PLGPIO21"),
PINCTRL_PIN(22, "PLGPIO22"),
PINCTRL_PIN(23, "PLGPIO23"),
PINCTRL_PIN(24, "PLGPIO24"),
PINCTRL_PIN(25, "PLGPIO25"),
PINCTRL_PIN(26, "PLGPIO26"),
PINCTRL_PIN(27, "PLGPIO27"),
PINCTRL_PIN(28, "PLGPIO28"),
PINCTRL_PIN(29, "PLGPIO29"),
PINCTRL_PIN(30, "PLGPIO30"),
PINCTRL_PIN(31, "PLGPIO31"),
PINCTRL_PIN(32, "PLGPIO32"),
PINCTRL_PIN(33, "PLGPIO33"),
PINCTRL_PIN(34, "PLGPIO34"),
PINCTRL_PIN(35, "PLGPIO35"),
PINCTRL_PIN(36, "PLGPIO36"),
PINCTRL_PIN(37, "PLGPIO37"),
PINCTRL_PIN(38, "PLGPIO38"),
PINCTRL_PIN(39, "PLGPIO39"),
PINCTRL_PIN(40, "PLGPIO40"),
PINCTRL_PIN(41, "PLGPIO41"),
PINCTRL_PIN(42, "PLGPIO42"),
PINCTRL_PIN(43, "PLGPIO43"),
PINCTRL_PIN(44, "PLGPIO44"),
PINCTRL_PIN(45, "PLGPIO45"),
PINCTRL_PIN(46, "PLGPIO46"),
PINCTRL_PIN(47, "PLGPIO47"),
PINCTRL_PIN(48, "PLGPIO48"),
PINCTRL_PIN(49, "PLGPIO49"),
PINCTRL_PIN(50, "PLGPIO50"),
PINCTRL_PIN(51, "PLGPIO51"),
PINCTRL_PIN(52, "PLGPIO52"),
PINCTRL_PIN(53, "PLGPIO53"),
PINCTRL_PIN(54, "PLGPIO54"),
PINCTRL_PIN(55, "PLGPIO55"),
PINCTRL_PIN(56, "PLGPIO56"),
PINCTRL_PIN(57, "PLGPIO57"),
PINCTRL_PIN(58, "PLGPIO58"),
PINCTRL_PIN(59, "PLGPIO59"),
PINCTRL_PIN(60, "PLGPIO60"),
PINCTRL_PIN(61, "PLGPIO61"),
PINCTRL_PIN(62, "PLGPIO62"),
PINCTRL_PIN(63, "PLGPIO63"),
PINCTRL_PIN(64, "PLGPIO64"),
PINCTRL_PIN(65, "PLGPIO65"),
PINCTRL_PIN(66, "PLGPIO66"),
PINCTRL_PIN(67, "PLGPIO67"),
PINCTRL_PIN(68, "PLGPIO68"),
PINCTRL_PIN(69, "PLGPIO69"),
PINCTRL_PIN(70, "PLGPIO70"),
PINCTRL_PIN(71, "PLGPIO71"),
PINCTRL_PIN(72, "PLGPIO72"),
PINCTRL_PIN(73, "PLGPIO73"),
PINCTRL_PIN(74, "PLGPIO74"),
PINCTRL_PIN(75, "PLGPIO75"),
PINCTRL_PIN(76, "PLGPIO76"),
PINCTRL_PIN(77, "PLGPIO77"),
PINCTRL_PIN(78, "PLGPIO78"),
PINCTRL_PIN(79, "PLGPIO79"),
PINCTRL_PIN(80, "PLGPIO80"),
PINCTRL_PIN(81, "PLGPIO81"),
PINCTRL_PIN(82, "PLGPIO82"),
PINCTRL_PIN(83, "PLGPIO83"),
PINCTRL_PIN(84, "PLGPIO84"),
PINCTRL_PIN(85, "PLGPIO85"),
PINCTRL_PIN(86, "PLGPIO86"),
PINCTRL_PIN(87, "PLGPIO87"),
PINCTRL_PIN(88, "PLGPIO88"),
PINCTRL_PIN(89, "PLGPIO89"),
PINCTRL_PIN(90, "PLGPIO90"),
PINCTRL_PIN(91, "PLGPIO91"),
PINCTRL_PIN(92, "PLGPIO92"),
PINCTRL_PIN(93, "PLGPIO93"),
PINCTRL_PIN(94, "PLGPIO94"),
PINCTRL_PIN(95, "PLGPIO95"),
PINCTRL_PIN(96, "PLGPIO96"),
PINCTRL_PIN(97, "PLGPIO97"),
PINCTRL_PIN(98, "PLGPIO98"),
PINCTRL_PIN(99, "PLGPIO99"),
PINCTRL_PIN(100, "PLGPIO100"),
PINCTRL_PIN(101, "PLGPIO101"),
SPEAR_PIN_0_TO_101,
};
/* firda_pins */
......
drivers/spi/Kconfig
View file @ 30b84288
......@@ -311,7 +311,7 @@ config SPI_S3C24XX_FIQ
config SPI_S3C64XX
tristate "Samsung S3C64XX series type SPI"
depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
select S3C64XX_DMA if ARCH_S3C64XX
help
SPI driver for Samsung S3C64XX and newer SoCs.
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