Commit 325b94f7 authored by Byungho An's avatar Byungho An Committed by David S. Miller

net: sxgbe: Added rxqueue enable function

This patch adds rxqueue enable function according to number of rxqueue
and adds rxqueue disable function for removing.
Signed-off-by: default avatarByungho An <bh74.an@samsung.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0a0347b1
...@@ -358,6 +358,8 @@ struct sxgbe_core_ops { ...@@ -358,6 +358,8 @@ struct sxgbe_core_ops {
/* Enable disable checksum offload operations */ /* Enable disable checksum offload operations */
void (*enable_rx_csum)(void __iomem *ioaddr); void (*enable_rx_csum)(void __iomem *ioaddr);
void (*disable_rx_csum)(void __iomem *ioaddr); void (*disable_rx_csum)(void __iomem *ioaddr);
void (*enable_rxqueue)(void __iomem *ioaddr, int queue_num);
void (*disable_rxqueue)(void __iomem *ioaddr, int queue_num);
}; };
const struct sxgbe_core_ops *sxgbe_get_core_ops(void); const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
......
...@@ -165,6 +165,26 @@ static void sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed) ...@@ -165,6 +165,26 @@ static void sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed)
writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG); writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
} }
static void sxgbe_core_enable_rxqueue(void __iomem *ioaddr, int queue_num)
{
u32 reg_val;
reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
reg_val |= SXGBE_CORE_RXQ_ENABLE;
writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
}
static void sxgbe_core_disable_rxqueue(void __iomem *ioaddr, int queue_num)
{
u32 reg_val;
reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
reg_val |= SXGBE_CORE_RXQ_DISABLE;
writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
}
static void sxgbe_set_eee_mode(void __iomem *ioaddr) static void sxgbe_set_eee_mode(void __iomem *ioaddr)
{ {
u32 ctrl; u32 ctrl;
...@@ -254,6 +274,8 @@ static const struct sxgbe_core_ops core_ops = { ...@@ -254,6 +274,8 @@ static const struct sxgbe_core_ops core_ops = {
.set_eee_pls = sxgbe_set_eee_pls, .set_eee_pls = sxgbe_set_eee_pls,
.enable_rx_csum = sxgbe_enable_rx_csum, .enable_rx_csum = sxgbe_enable_rx_csum,
.disable_rx_csum = sxgbe_disable_rx_csum, .disable_rx_csum = sxgbe_disable_rx_csum,
.enable_rxqueue = sxgbe_core_enable_rxqueue,
.disable_rxqueue = sxgbe_core_disable_rxqueue,
}; };
const struct sxgbe_core_ops *sxgbe_get_core_ops(void) const struct sxgbe_core_ops *sxgbe_get_core_ops(void)
......
...@@ -1076,6 +1076,9 @@ static int sxgbe_open(struct net_device *dev) ...@@ -1076,6 +1076,9 @@ static int sxgbe_open(struct net_device *dev)
/* Initialize the MAC Core */ /* Initialize the MAC Core */
priv->hw->mac->core_init(priv->ioaddr); priv->hw->mac->core_init(priv->ioaddr);
SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
}
/* Request the IRQ lines */ /* Request the IRQ lines */
ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt, ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
...@@ -2240,9 +2243,14 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device, ...@@ -2240,9 +2243,14 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
int sxgbe_drv_remove(struct net_device *ndev) int sxgbe_drv_remove(struct net_device *ndev)
{ {
struct sxgbe_priv_data *priv = netdev_priv(ndev); struct sxgbe_priv_data *priv = netdev_priv(ndev);
u8 queue_num;
netdev_info(ndev, "%s: removing driver\n", __func__); netdev_info(ndev, "%s: removing driver\n", __func__);
SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
}
priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES); priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES); priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
......
...@@ -52,6 +52,10 @@ ...@@ -52,6 +52,10 @@
#define SXGBE_CORE_RX_CTL2_REG 0x00A8 #define SXGBE_CORE_RX_CTL2_REG 0x00A8
#define SXGBE_CORE_RX_CTL3_REG 0x00AC #define SXGBE_CORE_RX_CTL3_REG 0x00AC
#define SXGBE_CORE_RXQ_ENABLE_MASK 0x0003
#define SXGBE_CORE_RXQ_ENABLE 0x0002
#define SXGBE_CORE_RXQ_DISABLE 0x0000
/* Interrupt Registers */ /* Interrupt Registers */
#define SXGBE_CORE_INT_STATUS_REG 0x00B0 #define SXGBE_CORE_INT_STATUS_REG 0x00B0
#define SXGBE_CORE_INT_ENABLE_REG 0x00B4 #define SXGBE_CORE_INT_ENABLE_REG 0x00B4
......
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