Commit 32f784b5 authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller

drivers: net: xgene: Add SGMII based 1GbE support

Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarKeyur Chudgar <kchudgar@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent dc8385f0
...@@ -2,6 +2,6 @@ ...@@ -2,6 +2,6 @@
# Makefile for APM X-Gene Ethernet Driver. # Makefile for APM X-Gene Ethernet Driver.
# #
xgene-enet-objs := xgene_enet_hw.o xgene_enet_xgmac.o \ xgene-enet-objs := xgene_enet_hw.o xgene_enet_sgmac.o xgene_enet_xgmac.o \
xgene_enet_main.o xgene_enet_ethtool.o xgene_enet_main.o xgene_enet_ethtool.o
obj-$(CONFIG_NET_XGENE) += xgene-enet.o obj-$(CONFIG_NET_XGENE) += xgene-enet.o
...@@ -44,6 +44,7 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) ...@@ -44,6 +44,7 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
enum xgene_enet_rm { enum xgene_enet_rm {
RM0, RM0,
RM1,
RM3 = 3 RM3 = 3
}; };
...@@ -143,6 +144,8 @@ enum xgene_enet_rm { ...@@ -143,6 +144,8 @@ enum xgene_enet_rm {
#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
#define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0))
#define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16))
#define ICM_CONFIG0_REG_0_ADDR 0x0400 #define ICM_CONFIG0_REG_0_ADDR 0x0400
#define ICM_CONFIG2_REG_0_ADDR 0x0410 #define ICM_CONFIG2_REG_0_ADDR 0x0410
#define RX_DV_GATE_REG_0_ADDR 0x05fc #define RX_DV_GATE_REG_0_ADDR 0x05fc
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include "xgene_enet_main.h" #include "xgene_enet_main.h"
#include "xgene_enet_hw.h" #include "xgene_enet_hw.h"
#include "xgene_enet_sgmac.h"
#include "xgene_enet_xgmac.h" #include "xgene_enet_xgmac.h"
static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
...@@ -813,6 +814,7 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) ...@@ -813,6 +814,7 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
return pdata->phy_mode; return pdata->phy_mode;
} }
if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII && if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) { pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
dev_err(dev, "Incorrect phy-connection-type specified\n"); dev_err(dev, "Incorrect phy-connection-type specified\n");
return -ENODEV; return -ENODEV;
...@@ -830,7 +832,8 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) ...@@ -830,7 +832,8 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) { if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET; pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET;
pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET; pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET;
} else { } else {
...@@ -881,6 +884,11 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) ...@@ -881,6 +884,11 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
pdata->port_ops = &xgene_gport_ops; pdata->port_ops = &xgene_gport_ops;
pdata->rm = RM3; pdata->rm = RM3;
break; break;
case PHY_INTERFACE_MODE_SGMII:
pdata->mac_ops = &xgene_sgmac_ops;
pdata->port_ops = &xgene_sgport_ops;
pdata->rm = RM1;
break;
default: default:
pdata->mac_ops = &xgene_xgmac_ops; pdata->mac_ops = &xgene_xgmac_ops;
pdata->port_ops = &xgene_xgport_ops; pdata->port_ops = &xgene_xgport_ops;
......
...@@ -39,6 +39,9 @@ ...@@ -39,6 +39,9 @@
#define NUM_PKT_BUF 64 #define NUM_PKT_BUF 64
#define NUM_BUFPOOL 32 #define NUM_BUFPOOL 32
#define PHY_POLL_LINK_ON (10 * HZ)
#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
/* software context of a descriptor ring */ /* software context of a descriptor ring */
struct xgene_enet_desc_ring { struct xgene_enet_desc_ring {
struct net_device *ndev; struct net_device *ndev;
...@@ -118,6 +121,13 @@ struct xgene_enet_pdata { ...@@ -118,6 +121,13 @@ struct xgene_enet_pdata {
struct delayed_work link_work; struct delayed_work link_work;
}; };
struct xgene_indirect_ctl {
void __iomem *addr;
void __iomem *ctl;
void __iomem *cmd;
void __iomem *cmd_done;
};
/* Set the specified value into a bit-field defined by its starting position /* Set the specified value into a bit-field defined by its starting position
* and length within a single u64. * and length within a single u64.
*/ */
......
This diff is collapsed.
/* Applied Micro X-Gene SoC Ethernet Driver
*
* Copyright (c) 2014, Applied Micro Circuits Corporation
* Authors: Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_SGMAC_H__
#define __XGENE_ENET_SGMAC_H__
#define PHY_ADDR(src) (((src)<<8) & GENMASK(12, 8))
#define REG_ADDR(src) ((src) & GENMASK(4, 0))
#define PHY_CONTROL(src) ((src) & GENMASK(15, 0))
#define INT_PHY_ADDR 0x1e
#define SGMII_TBI_CONTROL_ADDR 0x44
#define SGMII_CONTROL_ADDR 0x00
#define SGMII_STATUS_ADDR 0x04
#define SGMII_BASE_PAGE_ABILITY_ADDR 0x14
#define AUTO_NEG_COMPLETE BIT(5)
#define LINK_STATUS BIT(2)
#define LINK_UP BIT(15)
#define MPA_IDLE_WITH_QMI_EMPTY BIT(12)
#define SG_RX_DV_GATE_REG_0_ADDR 0x0dfc
extern struct xgene_mac_ops xgene_sgmac_ops;
extern struct xgene_port_ops xgene_sgport_ops;
#endif /* __XGENE_ENET_SGMAC_H__ */
...@@ -47,9 +47,6 @@ ...@@ -47,9 +47,6 @@
#define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410 #define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410
#define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804 #define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804
#define PHY_POLL_LINK_ON (10 * HZ)
#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
extern struct xgene_mac_ops xgene_xgmac_ops; extern struct xgene_mac_ops xgene_xgmac_ops;
extern struct xgene_port_ops xgene_xgport_ops; extern struct xgene_port_ops xgene_xgport_ops;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment