Commit 363eb0b4 authored by Alex Deucher's avatar Alex Deucher

drm/radeon: add hard_reset module parameter

Enabling this parameter enables pci config reset,
aka hard reset, which is a bus level chip reset.
In some cases this works more reliably than a soft
reset.  Disabled by default.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 56492e0f
...@@ -99,6 +99,7 @@ extern int radeon_fastfb; ...@@ -99,6 +99,7 @@ extern int radeon_fastfb;
extern int radeon_dpm; extern int radeon_dpm;
extern int radeon_aspm; extern int radeon_aspm;
extern int radeon_runtime_pm; extern int radeon_runtime_pm;
extern int radeon_hard_reset;
/* /*
* Copy from radeon_drv.h so we don't have to include both and have conflicting * Copy from radeon_drv.h so we don't have to include both and have conflicting
......
...@@ -167,6 +167,7 @@ int radeon_fastfb = 0; ...@@ -167,6 +167,7 @@ int radeon_fastfb = 0;
int radeon_dpm = -1; int radeon_dpm = -1;
int radeon_aspm = -1; int radeon_aspm = -1;
int radeon_runtime_pm = -1; int radeon_runtime_pm = -1;
int radeon_hard_reset = 0;
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
module_param_named(no_wb, radeon_no_wb, int, 0444); module_param_named(no_wb, radeon_no_wb, int, 0444);
...@@ -231,6 +232,9 @@ module_param_named(aspm, radeon_aspm, int, 0444); ...@@ -231,6 +232,9 @@ module_param_named(aspm, radeon_aspm, int, 0444);
MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
module_param_named(runpm, radeon_runtime_pm, int, 0444); module_param_named(runpm, radeon_runtime_pm, int, 0444);
MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
module_param_named(hard_reset, radeon_hard_reset, int, 0444);
static struct pci_device_id pciidlist[] = { static struct pci_device_id pciidlist[] = {
radeon_PCI_IDS radeon_PCI_IDS
}; };
......
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