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Commit 39d30770 authored by Mike Travis's avatar Mike Travis Committed by Ingo Molnar
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x86: SGI UV: Fix writes to led registers on remote uv hubs 

The wrong address was being used to write the SCIR led regs on
remote hubs.  Also, there was an inconsistency between how BIOS
and the kernel indexed these regs.  Standardize on using the
lower 6 bits of the APIC ID as the index.

This patch fixes the problem of writing to an errant address to
a cpu # >= 64.
Signed-off-by: default avatarMike Travis <travis@sgi.com>
Reviewed-by: default avatarJack Steiner <steiner@sgi.com>
Cc: Robin Holt <holt@sgi.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: stable@kernel.org
LKML-Reference: <4B3922F9.3060905@sgi.com>
[ v2: fix a number of annoying checkpatch artifacts and whitespace noise ]
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent c0ca9da4
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Showing with 54 additions and 44 deletions
arch/x86/include/asm/uv/uv_hub.h
View file @ 39d30770
...@@ -31,20 +31,20 @@ ...@@ -31,20 +31,20 @@
* contiguous (although various IO spaces may punch holes in * contiguous (although various IO spaces may punch holes in
* it).. * it)..
* *
* N - Number of bits in the node portion of a socket physical * N - Number of bits in the node portion of a socket physical
* address. * address.
* *
* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
* routers always have low bit of 1, C/MBricks have low bit * routers always have low bit of 1, C/MBricks have low bit
* equal to 0. Most addressing macros that target UV hub chips * equal to 0. Most addressing macros that target UV hub chips
* right shift the NASID by 1 to exclude the always-zero bit. * right shift the NASID by 1 to exclude the always-zero bit.
* NASIDs contain up to 15 bits. * NASIDs contain up to 15 bits.
* *
* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
* of nasids. * of nasids.
* *
* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
* of the nasid for socket usage. * of the nasid for socket usage.
* *
* *
* NumaLink Global Physical Address Format: * NumaLink Global Physical Address Format:
...@@ -71,12 +71,12 @@ ...@@ -71,12 +71,12 @@
* *
* *
* APICID format * APICID format
* NOTE!!!!!! This is the current format of the APICID. However, code * NOTE!!!!!! This is the current format of the APICID. However, code
* should assume that this will change in the future. Use functions * should assume that this will change in the future. Use functions
* in this file for all APICID bit manipulations and conversion. * in this file for all APICID bit manipulations and conversion.
* *
* 1111110000000000 * 1111110000000000
* 5432109876543210 * 5432109876543210
* pppppppppplc0cch * pppppppppplc0cch
* sssssssssss * sssssssssss
* *
...@@ -89,9 +89,9 @@ ...@@ -89,9 +89,9 @@
* Note: Processor only supports 12 bits in the APICID register. The ACPI * Note: Processor only supports 12 bits in the APICID register. The ACPI
* tables hold all 16 bits. Software needs to be aware of this. * tables hold all 16 bits. Software needs to be aware of this.
* *
* Unless otherwise specified, all references to APICID refer to * Unless otherwise specified, all references to APICID refer to
* the FULL value contained in ACPI tables, not the subset in the * the FULL value contained in ACPI tables, not the subset in the
* processor APICID register. * processor APICID register.
*/ */
...@@ -151,16 +151,16 @@ struct uv_hub_info_s { ...@@ -151,16 +151,16 @@ struct uv_hub_info_s {
}; };
DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info (&__get_cpu_var(__uv_hub_info)) #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
/* /*
* Local & Global MMR space macros. * Local & Global MMR space macros.
* Note: macros are intended to be used ONLY by inline functions * Note: macros are intended to be used ONLY by inline functions
* in this file - not by other kernel code. * in this file - not by other kernel code.
* n - NASID (full 15-bit global nasid) * n - NASID (full 15-bit global nasid)
* g - GNODE (full 15-bit global nasid, right shifted 1) * g - GNODE (full 15-bit global nasid, right shifted 1)
* p - PNODE (local part of nsids, right shifted 1) * p - PNODE (local part of nsids, right shifted 1)
*/ */
#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
...@@ -215,8 +215,8 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); ...@@ -215,8 +215,8 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
/* /*
* Macros for converting between kernel virtual addresses, socket local physical * Macros for converting between kernel virtual addresses, socket local physical
* addresses, and UV global physical addresses. * addresses, and UV global physical addresses.
* Note: use the standard __pa() & __va() macros for converting * Note: use the standard __pa() & __va() macros for converting
* between socket virtual and socket physical addresses. * between socket virtual and socket physical addresses.
*/ */
/* socket phys RAM --> UV global physical address */ /* socket phys RAM --> UV global physical address */
...@@ -287,21 +287,18 @@ static inline int uv_apicid_to_pnode(int apicid) ...@@ -287,21 +287,18 @@ static inline int uv_apicid_to_pnode(int apicid)
* Access global MMRs using the low memory MMR32 space. This region supports * Access global MMRs using the low memory MMR32 space. This region supports
* faster MMR access but not all MMRs are accessible in this space. * faster MMR access but not all MMRs are accessible in this space.
*/ */
static inline unsigned long *uv_global_mmr32_address(int pnode, static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
unsigned long offset)
{ {
return __va(UV_GLOBAL_MMR32_BASE | return __va(UV_GLOBAL_MMR32_BASE |
UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
} }
static inline void uv_write_global_mmr32(int pnode, unsigned long offset, static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
unsigned long val)
{ {
writeq(val, uv_global_mmr32_address(pnode, offset)); writeq(val, uv_global_mmr32_address(pnode, offset));
} }
static inline unsigned long uv_read_global_mmr32(int pnode, static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
unsigned long offset)
{ {
return readq(uv_global_mmr32_address(pnode, offset)); return readq(uv_global_mmr32_address(pnode, offset));
} }
...@@ -310,21 +307,18 @@ static inline unsigned long uv_read_global_mmr32(int pnode, ...@@ -310,21 +307,18 @@ static inline unsigned long uv_read_global_mmr32(int pnode,
* Access Global MMR space using the MMR space located at the top of physical * Access Global MMR space using the MMR space located at the top of physical
* memory. * memory.
*/ */
static inline unsigned long *uv_global_mmr64_address(int pnode, static inline unsigned long *uv_global_mmr64_address(int pnode, unsigned long offset)
unsigned long offset)
{ {
return __va(UV_GLOBAL_MMR64_BASE | return __va(UV_GLOBAL_MMR64_BASE |
UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
} }
static inline void uv_write_global_mmr64(int pnode, unsigned long offset, static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
unsigned long val)
{ {
writeq(val, uv_global_mmr64_address(pnode, offset)); writeq(val, uv_global_mmr64_address(pnode, offset));
} }
static inline unsigned long uv_read_global_mmr64(int pnode, static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
unsigned long offset)
{ {
return readq(uv_global_mmr64_address(pnode, offset)); return readq(uv_global_mmr64_address(pnode, offset));
} }
...@@ -338,6 +332,16 @@ static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long o ...@@ -338,6 +332,16 @@ static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long o
return UV_GLOBAL_GRU_MMR_BASE | offset | (pnode << uv_hub_info->m_val); return UV_GLOBAL_GRU_MMR_BASE | offset | (pnode << uv_hub_info->m_val);
} }
static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
{
writeb(val, uv_global_mmr64_address(pnode, offset));
}
static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
{
return readb(uv_global_mmr64_address(pnode, offset));
}
/* /*
* Access hub local MMRs. Faster than using global space but only local MMRs * Access hub local MMRs. Faster than using global space but only local MMRs
* are accessible. * are accessible.
...@@ -457,11 +461,17 @@ static inline void uv_set_scir_bits(unsigned char value) ...@@ -457,11 +461,17 @@ static inline void uv_set_scir_bits(unsigned char value)
} }
} }
static inline unsigned long uv_scir_offset(int apicid)
{
return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
}
static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
{ {
if (uv_cpu_hub_info(cpu)->scir.state != value) { if (uv_cpu_hub_info(cpu)->scir.state != value) {
uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
uv_cpu_hub_info(cpu)->scir.offset, value);
uv_cpu_hub_info(cpu)->scir.state = value; uv_cpu_hub_info(cpu)->scir.state = value;
uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
} }
} }
......
arch/x86/kernel/apic/x2apic_uv_x.c
View file @ 39d30770
...@@ -629,8 +629,10 @@ void __init uv_system_init(void) ...@@ -629,8 +629,10 @@ void __init uv_system_init(void)
uv_rtc_init(); uv_rtc_init();
for_each_present_cpu(cpu) { for_each_present_cpu(cpu) {
int apicid = per_cpu(x86_cpu_to_apicid, cpu);
nid = cpu_to_node(cpu); nid = cpu_to_node(cpu);
pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu)); pnode = uv_apicid_to_pnode(apicid);
blade = boot_pnode_to_blade(pnode); blade = boot_pnode_to_blade(pnode);
lcpu = uv_blade_info[blade].nr_possible_cpus; lcpu = uv_blade_info[blade].nr_possible_cpus;
uv_blade_info[blade].nr_possible_cpus++; uv_blade_info[blade].nr_possible_cpus++;
...@@ -651,15 +653,13 @@ void __init uv_system_init(void) ...@@ -651,15 +653,13 @@ void __init uv_system_init(void)
uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu; uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
uv_node_to_blade[nid] = blade; uv_node_to_blade[nid] = blade;
uv_cpu_to_blade[cpu] = blade; uv_cpu_to_blade[cpu] = blade;
max_pnode = max(pnode, max_pnode); max_pnode = max(pnode, max_pnode);
printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, " printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, lcpu %d, blade %d\n",
"lcpu %d, blade %d\n", cpu, apicid, pnode, nid, lcpu, blade);
cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
lcpu, blade);
} }
/* Add blade/pnode info for nodes without cpus */ /* Add blade/pnode info for nodes without cpus */
......
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