Commit 3c6c8685 authored by Silvio Fricke's avatar Silvio Fricke Committed by Shawn Guo

ARM: dts: imx6: edmqmx6: Add two other i2c buses

Signed-off-by: default avatarSilvio Fricke <silvio.fricke@gmail.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent fd101c4c
...@@ -118,6 +118,13 @@ &fec { ...@@ -118,6 +118,13 @@ &fec {
status = "okay"; status = "okay";
}; };
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 { &i2c2 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -274,6 +281,13 @@ rtc: m41t62@68 { ...@@ -274,6 +281,13 @@ rtc: m41t62@68 {
}; };
}; };
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc { &iomuxc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_hog>;
...@@ -316,6 +330,13 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ...@@ -316,6 +330,13 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>; >;
}; };
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp { pinctrl_i2c2: i2c2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
...@@ -323,6 +344,13 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ...@@ -323,6 +344,13 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>; >;
}; };
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp { pinctrl_pcie: pciegrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
......
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