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Commit 3d9d6859 authored by Dave Jones's avatar Dave Jones
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Merge tetrachloride.(none):/mnt/stuff/kernel/2.5/bk-linus 

into tetrachloride.(none):/mnt/stuff/kernel/2.5/agpgart-respin
parents f2478c00 13d5e170
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Showing with 1529 additions and 1295 deletions
drivers/char/agp/Kconfig
View file @ 3d9d6859
......@@ -61,16 +61,6 @@ config AGP_VIA
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
config AGP_VIA_KT400
tristate "VIA KT400 chipset support"
depends on AGP3
help
This option gives you AGP support for the GLX component of the
XFree86 4.x on VIA KT400 AGP 3.0 chipsets.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
config AGP_AMD
tristate "AMD Irongate, 761, and 762 support"
depends on AGP
......@@ -141,6 +131,11 @@ config AGP_HP_ZX1
This option gives you AGP GART support for the HP ZX1 chipset
for IA64 processors.
config AGP_ALPHA_CORE
tristate
depends on AGP && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL)
default AGP
# Put AGP 3.0 entries below here.
config AGP_I7505
......
drivers/char/agp/Makefile
View file @ 3d9d6859
......@@ -10,7 +10,6 @@ obj-$(CONFIG_AGP) += agpgart.o
obj-$(CONFIG_AGP_INTEL) += intel-agp.o
obj-$(CONFIG_AGP_VIA) += via-agp.o
obj-$(CONFIG_AGP_VIA_KT400) += via-kt400.o
obj-$(CONFIG_AGP_AMD) += amd-k7-agp.o
obj-$(CONFIG_AGP_SIS) += sis-agp.o
obj-$(CONFIG_AGP_ALI) += ali-agp.o
......@@ -18,6 +17,7 @@ obj-$(CONFIG_AGP_SWORKS) += sworks-agp.o
obj-$(CONFIG_AGP_I460) += i460-agp.o
obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
obj-$(CONFIG_AGP_AMD_8151) += amd-k8-agp.o
obj-$(CONFIG_AGP_ALPHA_CORE) += alpha-agp.o
obj-$(CONFIG_AGP_I7x05) += i7x05-agp.o
drivers/char/agp/agp.h
View file @ 3d9d6859
......@@ -30,7 +30,7 @@
#include <asm/agp.h> /* for flush_agp_cache() */
extern struct agp_bridge_data agp_bridge;
extern struct agp_bridge_data *agp_bridge;
#define PFX "agpgart: "
......@@ -128,6 +128,7 @@ struct agp_bridge_data {
int num_aperture_sizes;
int capndx;
int cant_use_aperture;
struct vm_operations_struct *vm_ops;
/* Links to driver specific functions */
......@@ -165,20 +166,20 @@ struct agp_bridge_data {
#define MB(x) (KB (KB (x)))
#define GB(x) (MB (KB (x)))
#define CACHE_FLUSH agp_bridge.cache_flush
#define CACHE_FLUSH agp_bridge->cache_flush
#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
#define A_IDX8() (A_SIZE_8(agp_bridge.aperture_sizes) + i)
#define A_IDX16() (A_SIZE_16(agp_bridge.aperture_sizes) + i)
#define A_IDX32() (A_SIZE_32(agp_bridge.aperture_sizes) + i)
#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i)
#define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
#define A_IDX8() (A_SIZE_8(agp_bridge->aperture_sizes) + i)
#define A_IDX16() (A_SIZE_16(agp_bridge->aperture_sizes) + i)
#define A_IDX32() (A_SIZE_32(agp_bridge->aperture_sizes) + i)
#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge->aperture_sizes) + i)
#define A_IDXFIX() (A_SIZE_FIX(agp_bridge->aperture_sizes) + i)
#define MAXKEY (4096 * 32)
#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge->scratch_page)
/* intel register */
#define INTEL_APBASE 0x10
......@@ -366,7 +367,7 @@ struct agp_driver {
/* Generic routines. */
void agp_generic_agp_enable(u32 mode);
int agp_generic_agp_3_0_enable(u32 mode);
void agp_generic_agp_3_0_enable(u32 mode);
int agp_generic_create_gatt_table(void);
int agp_generic_free_gatt_table(void);
agp_memory *agp_create_memory(int scratch_pages);
......
drivers/char/agp/ali-agp.c
View file @ 3d9d6859
......@@ -17,15 +17,15 @@ static int ali_fetch_size(void)
u32 temp;
struct aper_size_info_32 *values;
pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
temp &= ~(0xfffffff0);
values = A_SIZE_32(agp_bridge.aperture_sizes);
values = A_SIZE_32(agp_bridge->aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -37,9 +37,9 @@ static void ali_tlbflush(agp_memory * mem)
{
u32 temp;
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
// clear tag
pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
((temp & 0xfffffff0) | 0x00000001|0x00000002));
}
......@@ -48,15 +48,15 @@ static void ali_cleanup(void)
struct aper_size_info_32 *previous_size;
u32 temp;
previous_size = A_SIZE_32(agp_bridge.previous_size);
previous_size = A_SIZE_32(agp_bridge->previous_size);
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
// clear tag
pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
((temp & 0xffffff00) | 0x00000001|0x00000002));
pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
((temp & 0x00000ff0) | previous_size->size_value));
}
......@@ -65,24 +65,24 @@ static int ali_configure(void)
u32 temp;
struct aper_size_info_32 *current_size;
current_size = A_SIZE_32(agp_bridge.current_size);
current_size = A_SIZE_32(agp_bridge->current_size);
/* aperture size and gatt addr */
pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
temp = (((temp & 0x00000ff0) | (agp_bridge.gatt_bus_addr & 0xfffff000))
pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
| (current_size->size_value & 0xf));
pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, temp);
pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
/* tlb control */
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
/* address to map to */
pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, ALI_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
#if 0
if (agp_bridge.type == ALI_M1541) {
if (agp_bridge->type == ALI_M1541) {
u32 nlvm_addr = 0;
switch (current_size->size_value) {
......@@ -101,15 +101,15 @@ static int ali_configure(void)
nlvm_addr--;
nlvm_addr&=0xfff00000;
nlvm_addr+= agp_bridge.gart_bus_addr;
nlvm_addr|=(agp_bridge.gart_bus_addr>>12);
nlvm_addr+= agp_bridge->gart_bus_addr;
nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr);
}
#endif
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
temp &= 0xffffff7f; //enable TLB
pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, temp);
pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
return 0;
}
......@@ -118,23 +118,23 @@ static unsigned long ali_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
static void ali_cache_flush(void)
{
global_cache_flush();
if (agp_bridge.type == ALI_M1541) {
if (agp_bridge->type == ALI_M1541) {
int i, page_count;
u32 temp;
page_count = 1 << A_SIZE_32(agp_bridge.current_size)->page_order;
page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
(agp_bridge.gatt_bus_addr + i)) |
(agp_bridge->gatt_bus_addr + i)) |
ALI_CACHE_FLUSH_EN));
}
}
......@@ -148,9 +148,9 @@ static void *ali_alloc_page(void)
if (adr == 0)
return 0;
if (agp_bridge.type == ALI_M1541) {
pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
if (agp_bridge->type == ALI_M1541) {
pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(adr)) |
ALI_CACHE_FLUSH_EN ));
......@@ -167,9 +167,9 @@ static void ali_destroy_page(void * addr)
global_cache_flush();
if (agp_bridge.type == ALI_M1541) {
pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
if (agp_bridge->type == ALI_M1541) {
pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(addr)) |
ALI_CACHE_FLUSH_EN));
......@@ -197,30 +197,30 @@ static struct aper_size_info_32 ali_generic_sizes[7] =
static int __init ali_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = ali_generic_masks;
agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
agp_bridge.size_type = U32_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = ali_configure;
agp_bridge.fetch_size = ali_fetch_size;
agp_bridge.cleanup = ali_cleanup;
agp_bridge.tlb_flush = ali_tlbflush;
agp_bridge.mask_memory = ali_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = ali_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = ali_alloc_page;
agp_bridge.agp_destroy_page = ali_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = ali_generic_masks;
agp_bridge->aperture_sizes = (void *) ali_generic_sizes;
agp_bridge->size_type = U32_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = ali_configure;
agp_bridge->fetch_size = ali_fetch_size;
agp_bridge->cleanup = ali_cleanup;
agp_bridge->tlb_flush = ali_tlbflush;
agp_bridge->mask_memory = ali_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = ali_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = ali_alloc_page;
agp_bridge->agp_destroy_page = ali_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -313,7 +313,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
printk (KERN_INFO PFX "Detected ALi %s chipset\n",
devs[j].chipset_name);
agp_bridge.type = devs[j].chipset;
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
......@@ -327,7 +327,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic ALi routines"
" for device id: %04x\n", pdev->device);
agp_bridge.type = ALI_GENERIC;
agp_bridge->type = ALI_GENERIC;
return ali_generic_setup(pdev);
}
......@@ -350,10 +350,10 @@ static int __init agp_ali_probe (struct pci_dev *dev, const struct pci_device_id
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
ali_agp_driver.dev = dev;
agp_register_driver(&ali_agp_driver);
return 0;
......@@ -387,7 +387,7 @@ static int __init agp_ali_init(void)
ret_val = pci_module_init(&agp_ali_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/alpha-agp.c 0 → 100644
View file @ 3d9d6859
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <asm/machvec.h>
#include <asm/agp_backend.h>
#include "../../../arch/alpha/kernel/pci_impl.h"
#include "agp.h"
static struct page *alpha_core_agp_vm_nopage(struct vm_area_struct *vma,
unsigned long address,
int write_access)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
dma_addr_t dma_addr;
unsigned long pa;
struct page *page;
dma_addr = address - vma->vm_start + agp->aperture.bus_base;
pa = agp->ops->translate(agp, dma_addr);
if (pa == (unsigned long)-EINVAL) return NULL; /* no translation */
/*
* Get the page, inc the use count, and return it
*/
page = virt_to_page(__va(pa));
get_page(page);
return page;
}
static struct aper_size_info_fixed alpha_core_agp_sizes[] =
{
{ 0, 0, 0 }, /* filled in by alpha_core_agp_setup */
};
static struct gatt_mask alpha_core_agp_masks[] = {
{ .mask = 0, .type = 0 },
};
struct vm_operations_struct alpha_core_agp_vm_ops = {
.nopage = alpha_core_agp_vm_nopage,
};
static int alpha_core_agp_nop(void)
{
/* just return success */
return 0;
}
static int alpha_core_agp_fetch_size(void)
{
return alpha_core_agp_sizes[0].size;
}
static int alpha_core_agp_configure(void)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
agp_bridge->gart_bus_addr = agp->aperture.bus_base;
return 0;
}
static void alpha_core_agp_cleanup(void)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
agp->ops->cleanup(agp);
}
static void alpha_core_agp_tlbflush(agp_memory *mem)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
alpha_mv.mv_pci_tbi(agp->hose, 0, -1);
}
static unsigned long alpha_core_agp_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge->masks[0].mask;
}
static void alpha_core_agp_enable(u32 mode)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw);
agp->mode.bits.enable = 1;
agp->ops->configure(agp);
agp_device_command(agp->mode.lw, 0);
}
static int alpha_core_agp_insert_memory(agp_memory *mem, off_t pg_start,
int type)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
int num_entries, status;
void *temp;
temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if ((pg_start + mem->page_count) > num_entries) return -EINVAL;
status = agp->ops->bind(agp, pg_start, mem);
mb();
agp_bridge->tlb_flush(mem);
return status;
}
static int alpha_core_agp_remove_memory(agp_memory *mem, off_t pg_start,
int type)
{
alpha_agp_info *agp = agp_bridge->dev_private_data;
int status;
status = agp->ops->unbind(agp, pg_start, mem);
agp_bridge->tlb_flush(mem);
return status;
}
static struct agp_driver alpha_core_agp_driver = {
.owner = THIS_MODULE,
};
int __init
alpha_core_agp_setup(void)
{
alpha_agp_info *agp = alpha_mv.agp_info();
struct aper_size_info_fixed *aper_size;
if (!agp) return -ENODEV;
if (agp->ops->setup(agp)) return -ENODEV;
/*
* Build the aperture size descriptor
*/
aper_size = alpha_core_agp_sizes;
if (!aper_size) return -ENOMEM;
aper_size->size = agp->aperture.size / (1024 * 1024);
aper_size->num_entries = agp->aperture.size / PAGE_SIZE;
aper_size->page_order = ffs(aper_size->num_entries / 1024) - 1;
/*
* Build a fake pci_dev struct
*/
if (!(agp_bridge->dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) {
return -ENOMEM;
}
agp_bridge->dev->vendor = 0xffff;
agp_bridge->dev->device = 0xffff;
agp_bridge->dev->sysdata = agp->hose;
/*
* Fill in the rest of the agp_bridge struct
*/
agp_bridge->masks = alpha_core_agp_masks;
agp_bridge->aperture_sizes = aper_size;
agp_bridge->current_size = aper_size; /* only one entry */
agp_bridge->size_type = FIXED_APER_SIZE;
agp_bridge->num_aperture_sizes = 1;
agp_bridge->dev_private_data = agp;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = alpha_core_agp_configure;
agp_bridge->fetch_size = alpha_core_agp_fetch_size;
agp_bridge->cleanup = alpha_core_agp_cleanup;
agp_bridge->tlb_flush = alpha_core_agp_tlbflush;
agp_bridge->mask_memory = alpha_core_agp_mask_memory;
agp_bridge->agp_enable = alpha_core_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = alpha_core_agp_nop;
agp_bridge->free_gatt_table = alpha_core_agp_nop;
agp_bridge->insert_memory = alpha_core_agp_insert_memory;
agp_bridge->remove_memory = alpha_core_agp_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->mode = agp->capability.lw;
agp_bridge->cant_use_aperture = 1;
agp_bridgevm_ops = &alpha_core_agp_vm_ops;
alpha_core_agp_driver.dev = agp_bridge->dev;
agp_register_driver(&alpha_core_agp_driver);
printk(KERN_INFO "Detected AGP on hose %d\n", agp->hose->index);
return 0;
}
static int __init agp_alpha_core_init(void)
{
int ret_val = -ENODEV;
if (alpha_mv.agp_info) {
agp_bridge->type = ALPHA_CORE_AGP;
ret_val = alpha_core_agp_setup();
}
return ret_val;
}
static void __exit agp_alpha_core_cleanup(void)
{
agp_unregister_driver(&alpha_core_agp_driver);
/* no pci driver for core */
}
module_init(agp_alpha_core_init);
module_exit(agp_alpha_core_cleanup);
MODULE_AUTHOR("Jeff Wiedemeier <Jeff.Wiedemeier@hp.com>");
MODULE_LICENSE("GPL and additional rights");
drivers/char/agp/amd-k7-agp.c
View file @ 3d9d6859
......@@ -45,7 +45,7 @@ static int amd_create_page_map(struct amd_page_map *page_map)
CACHE_FLUSH();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
page_map->remapped[i] = agp_bridge.scratch_page;
page_map->remapped[i] = agp_bridge->scratch_page;
}
return 0;
......@@ -115,7 +115,7 @@ static int amd_create_gatt_pages(int nr_tables)
#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr))
GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
GET_PAGE_DIR_IDX(addr)]->remapped)
......@@ -129,7 +129,7 @@ static int amd_create_gatt_table(void)
u32 temp;
int i;
value = A_SIZE_LVL2(agp_bridge.current_size);
value = A_SIZE_LVL2(agp_bridge->current_size);
retval = amd_create_page_map(&page_dir);
if (retval != 0) {
return retval;
......@@ -141,18 +141,18 @@ static int amd_create_gatt_table(void)
return retval;
}
agp_bridge.gatt_table_real = (u32 *)page_dir.real;
agp_bridge.gatt_table = (u32 *)page_dir.remapped;
agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real);
agp_bridge->gatt_table_real = (u32 *)page_dir.real;
agp_bridge->gatt_table = (u32 *)page_dir.remapped;
agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
*/
pci_read_config_dword(agp_bridge.dev, AMD_APBASE, &temp);
pci_read_config_dword(agp_bridge->dev, AMD_APBASE, &temp);
addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
agp_bridge.gart_bus_addr = addr;
agp_bridge->gart_bus_addr = addr;
/* Calculate the agp offset */
for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
......@@ -168,8 +168,8 @@ static int amd_free_gatt_table(void)
{
struct amd_page_map page_dir;
page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
amd_free_gatt_pages();
amd_free_page_map(&page_dir);
......@@ -182,15 +182,15 @@ static int amd_irongate_fetch_size(void)
u32 temp;
struct aper_size_info_lvl2 *values;
pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = (temp & 0x0000000e);
values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
values = A_SIZE_LVL2(agp_bridge->aperture_sizes);
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -204,22 +204,22 @@ static int amd_irongate_configure(void)
u32 temp;
u16 enable_reg;
current_size = A_SIZE_LVL2(agp_bridge.current_size);
current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
pci_read_config_dword(agp_bridge.dev, AMD_MMBASE, &temp);
pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
/* Write out the address of the gatt table */
OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
agp_bridge.gatt_bus_addr);
agp_bridge->gatt_bus_addr);
/* Write the Sync register */
pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL, 0x80);
pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
/* Set indexing mode */
pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL2, 0x00);
pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
/* Write the enable register */
enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
......@@ -227,10 +227,10 @@ static int amd_irongate_configure(void)
OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
/* Write out the size register */
pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = (((temp & ~(0x0000000e)) | current_size->size_value)
| 0x00000001);
pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
/* Flush the tlb */
OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
......@@ -244,16 +244,16 @@ static void amd_irongate_cleanup(void)
u32 temp;
u16 enable_reg;
previous_size = A_SIZE_LVL2(agp_bridge.previous_size);
previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
enable_reg = (enable_reg & ~(0x0004));
OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
/* Write back the previous size and disable gart translation */
pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
iounmap((void *) amd_irongate_private.registers);
}
......@@ -274,7 +274,7 @@ static unsigned long amd_irongate_mask_memory(unsigned long addr, int type)
{
/* Only type 0 is supported by the irongate */
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
static int amd_insert_memory(agp_memory * mem,
......@@ -284,7 +284,7 @@ static int amd_insert_memory(agp_memory * mem,
unsigned long *cur_gatt;
unsigned long addr;
num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
if (type != 0 || mem->type != 0) {
return -EINVAL;
......@@ -295,7 +295,7 @@ static int amd_insert_memory(agp_memory * mem,
j = pg_start;
while (j < (pg_start + mem->page_count)) {
addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
......@@ -309,12 +309,12 @@ static int amd_insert_memory(agp_memory * mem,
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
agp_bridge.mask_memory(mem->memory[i], mem->type);
agp_bridge->mask_memory(mem->memory[i], mem->type);
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -329,13 +329,13 @@ static int amd_remove_memory(agp_memory * mem, off_t pg_start,
return -EINVAL;
}
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr;
addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
(unsigned long) agp_bridge.scratch_page;
(unsigned long) agp_bridge->scratch_page;
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -357,30 +357,30 @@ static struct gatt_mask amd_irongate_masks[] =
static int __init amd_irongate_setup (struct pci_dev *pdev)
{
agp_bridge.masks = amd_irongate_masks;
agp_bridge.aperture_sizes = (void *) amd_irongate_sizes;
agp_bridge.size_type = LVL2_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = (void *) &amd_irongate_private;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = amd_irongate_configure;
agp_bridge.fetch_size = amd_irongate_fetch_size;
agp_bridge.cleanup = amd_irongate_cleanup;
agp_bridge.tlb_flush = amd_irongate_tlbflush;
agp_bridge.mask_memory = amd_irongate_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = amd_create_gatt_table;
agp_bridge.free_gatt_table = amd_free_gatt_table;
agp_bridge.insert_memory = amd_insert_memory;
agp_bridge.remove_memory = amd_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = amd_irongate_masks;
agp_bridge->aperture_sizes = (void *) amd_irongate_sizes;
agp_bridge->size_type = LVL2_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = (void *) &amd_irongate_private;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = amd_irongate_configure;
agp_bridge->fetch_size = amd_irongate_fetch_size;
agp_bridge->cleanup = amd_irongate_cleanup;
agp_bridge->tlb_flush = amd_irongate_tlbflush;
agp_bridge->mask_memory = amd_irongate_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = amd_create_gatt_table;
agp_bridge->free_gatt_table = amd_free_gatt_table;
agp_bridge->insert_memory = amd_insert_memory;
agp_bridge->remove_memory = amd_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -416,7 +416,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
while (devs[j].chipset_name != NULL) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected AMD %s chipset\n", devs[j].chipset_name);
agp_bridge.type = devs[j].chipset;
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
......@@ -430,7 +430,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic AMD routines"
" for device id: %04x\n", pdev->device);
agp_bridge.type = AMD_GENERIC;
agp_bridge->type = AMD_GENERIC;
return amd_irongate_setup(pdev);
}
......@@ -455,10 +455,10 @@ static int __init agp_amdk7_probe (struct pci_dev *dev, const struct pci_device_
return -ENODEV;
if (agp_lookup_host_bridge(dev) != -ENODEV) {
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_k7_agp_driver.dev = dev;
agp_register_driver(&amd_k7_agp_driver);
return 0;
......@@ -492,7 +492,7 @@ static int __init agp_amdk7_init(void)
ret_val = pci_module_init(&agp_amdk7_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/amd-k8-agp.c
View file @ 3d9d6859
......@@ -70,7 +70,7 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
/* gatt table should be empty. */
while (j < (pg_start + mem->page_count)) {
if (!PGE_EMPTY(agp_bridge.gatt_table[j]))
if (!PGE_EMPTY(agp_bridge->gatt_table[j]))
return -EBUSY;
j++;
}
......@@ -81,7 +81,7 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = agp_bridge.mask_memory(mem->memory[i], mem->type);
addr = agp_bridge->mask_memory(mem->memory[i], mem->type);
tmp = addr;
BUG_ON(tmp & 0xffffff0000000ffc);
......@@ -89,9 +89,9 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
pte |=(tmp & 0x00000000fffff000);
pte |= 1<<1|1<<0;
agp_bridge.gatt_table[j] = pte;
agp_bridge->gatt_table[j] = pte;
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -134,12 +134,12 @@ static int amd_x86_64_fetch_size(void)
temp = (temp & 0xe);
values = A_SIZE_32(x86_64_aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -225,14 +225,14 @@ static int amd_8151_configure(void)
int current_size;
int tmp, tmp2, i;
u64 aperbar;
unsigned long gatt_bus = virt_to_phys(agp_bridge.gatt_table_real);
unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
/* Configure AGP regs in each x86-64 host bridge. */
pci_for_each_dev(dev) {
if (dev->bus->number==0 &&
PCI_FUNC(dev->devfn)==3 &&
PCI_SLOT(dev->devfn)>=24 && PCI_SLOT(dev->devfn)<=31) {
agp_bridge.gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
agp_bridge->gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
hammer = dev;
/*
......@@ -248,7 +248,7 @@ static int amd_8151_configure(void)
/* Shadow x86-64 registers into 8151 registers. */
dev = agp_bridge.dev;
dev = agp_bridge->dev;
if (!dev)
return -ENODEV;
......@@ -315,7 +315,7 @@ static void amd_8151_cleanup(void)
static unsigned long amd_8151_mask_memory(unsigned long addr, int type)
{
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
......@@ -368,12 +368,12 @@ static void agp_x86_64_agp_enable(u32 mode)
}
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &command);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_COMMAND, command);
pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_COMMAND, command);
agp_device_command(command, 1);
}
......@@ -381,30 +381,30 @@ static void agp_x86_64_agp_enable(u32 mode)
static int __init amd_8151_setup (struct pci_dev *pdev)
{
agp_bridge.masks = amd_8151_masks;
agp_bridge.aperture_sizes = (void *) amd_8151_sizes;
agp_bridge.size_type = U32_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = amd_8151_configure;
agp_bridge.fetch_size = amd_x86_64_fetch_size;
agp_bridge.cleanup = amd_8151_cleanup;
agp_bridge.tlb_flush = amd_x86_64_tlbflush;
agp_bridge.mask_memory = amd_8151_mask_memory;
agp_bridge.agp_enable = agp_x86_64_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = x86_64_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = amd_8151_masks;
agp_bridge->aperture_sizes = (void *) amd_8151_sizes;
agp_bridge->size_type = U32_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = amd_8151_configure;
agp_bridge->fetch_size = amd_x86_64_fetch_size;
agp_bridge->cleanup = amd_8151_cleanup;
agp_bridge->tlb_flush = amd_x86_64_tlbflush;
agp_bridge->mask_memory = amd_8151_mask_memory;
agp_bridge->agp_enable = agp_x86_64_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = x86_64_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -420,11 +420,11 @@ static int __init agp_amdk8_probe (struct pci_dev *dev, const struct pci_device_
if (cap_ptr == 0)
return -ENODEV;
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_8151_setup(dev);
amd_k8_agp_driver.dev = dev;
agp_register_driver(&amd_k8_agp_driver);
......@@ -458,9 +458,9 @@ int __init agp_amdk8_init(void)
ret_val = pci_module_init(&agp_amdk8_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
agp_bridge.type = AMD_8151;
agp_bridge->type = AMD_8151;
return ret_val;
}
......
drivers/char/agp/backend.c
View file @ 3d9d6859
......@@ -44,26 +44,27 @@
#define AGPGART_VERSION_MAJOR 0
#define AGPGART_VERSION_MINOR 100
struct agp_bridge_data agp_bridge = { .type = NOT_SUPPORTED };
struct agp_bridge_data agp_bridge_dummy = { .type = NOT_SUPPORTED };
struct agp_bridge_data *agp_bridge = &agp_bridge_dummy;
int agp_backend_acquire(void)
{
if (agp_bridge.type == NOT_SUPPORTED)
if (agp_bridge->type == NOT_SUPPORTED)
return -EINVAL;
if (atomic_read(&agp_bridge.agp_in_use) != 0)
if (atomic_read(&agp_bridge->agp_in_use) != 0)
return -EBUSY;
atomic_inc(&agp_bridge.agp_in_use);
atomic_inc(&agp_bridge->agp_in_use);
return 0;
}
void agp_backend_release(void)
{
if (agp_bridge.type == NOT_SUPPORTED)
if (agp_bridge->type == NOT_SUPPORTED)
return;
atomic_dec(&agp_bridge.agp_in_use);
atomic_dec(&agp_bridge->agp_in_use);
}
struct agp_max_table {
......@@ -114,38 +115,38 @@ static int agp_backend_initialize(struct pci_dev *dev)
{
int size_value, rc, got_gatt=0, got_keylist=0;
agp_bridge.max_memory_agp = agp_find_max();
agp_bridge.version = &agp_current_version;
agp_bridge->max_memory_agp = agp_find_max();
agp_bridge->version = &agp_current_version;
if (agp_bridge.needs_scratch_page == TRUE) {
if (agp_bridge->needs_scratch_page == TRUE) {
void *addr;
addr = agp_bridge.agp_alloc_page();
addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
printk(KERN_ERR PFX "unable to get memory for scratch page.\n");
return -ENOMEM;
}
agp_bridge.scratch_page_real = virt_to_phys(addr);
agp_bridge.scratch_page =
agp_bridge.mask_memory(agp_bridge.scratch_page_real, 0);
agp_bridge->scratch_page_real = virt_to_phys(addr);
agp_bridge->scratch_page =
agp_bridge->mask_memory(agp_bridge->scratch_page_real, 0);
}
size_value = agp_bridge.fetch_size();
size_value = agp_bridge->fetch_size();
if (size_value == 0) {
printk(KERN_ERR PFX "unable to determine aperture size.\n");
rc = -EINVAL;
goto err_out;
}
if (agp_bridge.create_gatt_table()) {
if (agp_bridge->create_gatt_table()) {
printk(KERN_ERR PFX "unable to get memory for graphics translation table.\n");
rc = -ENOMEM;
goto err_out;
}
got_gatt = 1;
agp_bridge.key_list = vmalloc(PAGE_SIZE * 4);
if (agp_bridge.key_list == NULL) {
agp_bridge->key_list = vmalloc(PAGE_SIZE * 4);
if (agp_bridge->key_list == NULL) {
printk(KERN_ERR PFX "error allocating memory for key lists.\n");
rc = -ENOMEM;
goto err_out;
......@@ -153,27 +154,27 @@ static int agp_backend_initialize(struct pci_dev *dev)
got_keylist = 1;
/* FIXME vmalloc'd memory not guaranteed contiguous */
memset(agp_bridge.key_list, 0, PAGE_SIZE * 4);
memset(agp_bridge->key_list, 0, PAGE_SIZE * 4);
if (agp_bridge.configure()) {
if (agp_bridge->configure()) {
printk(KERN_ERR PFX "error configuring host chipset.\n");
rc = -EINVAL;
goto err_out;
}
printk(KERN_INFO PFX "AGP aperture is %dM @ 0x%lx\n",
size_value, agp_bridge.gart_bus_addr);
size_value, agp_bridge->gart_bus_addr);
return 0;
err_out:
if (agp_bridge.needs_scratch_page == TRUE) {
agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
if (agp_bridge->needs_scratch_page == TRUE) {
agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
if (got_gatt)
agp_bridge.free_gatt_table();
agp_bridge->free_gatt_table();
if (got_keylist)
vfree(agp_bridge.key_list);
vfree(agp_bridge->key_list);
return rc;
}
......@@ -181,13 +182,16 @@ static int agp_backend_initialize(struct pci_dev *dev)
/* cannot be __exit b/c as it could be called from __init code */
static void agp_backend_cleanup(void)
{
agp_bridge.cleanup();
agp_bridge.free_gatt_table();
vfree(agp_bridge.key_list);
if (agp_bridge.needs_scratch_page == TRUE) {
agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
}
if (agp_bridge->cleanup != NULL)
agp_bridge->cleanup();
if (agp_bridge->free_gatt_table != NULL)
agp_bridge->free_gatt_table();
if (agp_bridge->key_list)
vfree(agp_bridge->key_list);
if ((agp_bridge->agp_destroy_page!=NULL) &&
(agp_bridge->needs_scratch_page == TRUE))
agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
......@@ -195,9 +199,9 @@ static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
switch(rq)
{
case PM_SUSPEND:
return agp_bridge.suspend();
return agp_bridge->suspend();
case PM_RESUME:
agp_bridge.resume();
agp_bridge->resume();
return 0;
}
return 0;
......@@ -248,21 +252,25 @@ int agp_register_driver (struct agp_driver *drv)
/* FIXME: What to do with this? */
inter_module_register("drm_agp", THIS_MODULE, &drm_agp);
pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge.dev), agp_power);
pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge->dev), agp_power);
agp_count++;
return 0;
frontend_err:
agp_backend_cleanup();
err_out:
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
module_put(drv->owner);
drv->dev = NULL;
return ret_val;
}
int agp_unregister_driver(struct agp_driver *drv)
{
agp_bridge.type = NOT_SUPPORTED;
if (drv->dev==NULL)
return -ENODEV;
agp_bridge->type = NOT_SUPPORTED;
pm_unregister_all(agp_power);
agp_frontend_cleanup();
agp_backend_cleanup();
......@@ -282,8 +290,8 @@ int __init agp_init(void)
already_initialised = 1;
memset(&agp_bridge, 0, sizeof(struct agp_bridge_data));
agp_bridge.type = NOT_SUPPORTED;
memset(agp_bridge, 0, sizeof(struct agp_bridge_data));
agp_bridge->type = NOT_SUPPORTED;
printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Dave Jones\n",
AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR);
......
drivers/char/agp/frontend.c
View file @ 3d9d6859
......@@ -97,7 +97,9 @@ static agp_segment_priv *agp_find_seg_in_client(const agp_client * client,
int size, pgprot_t page_prot)
{
agp_segment_priv *seg;
int num_segments, pg_start, pg_count, i;
int num_segments, i;
off_t pg_start;
size_t pg_count;
pg_start = offset / 4096;
pg_count = size / 4096;
......@@ -174,7 +176,7 @@ static int agp_create_segment(agp_client * client, agp_region * region)
agp_segment_priv **ret_seg;
agp_segment_priv *seg;
agp_segment *user_seg;
int i;
size_t i;
seg = kmalloc((sizeof(agp_segment_priv) * region->seg_count), GFP_KERNEL);
if (seg == NULL) {
......@@ -578,8 +580,7 @@ static int agp_remove_client(pid_t id)
static int agp_mmap(struct file *file, struct vm_area_struct *vma)
{
int size;
int current_size;
unsigned int size, current_size;
unsigned long offset;
agp_client *client;
agp_file_private *priv = (agp_file_private *) file->private_data;
......@@ -611,8 +612,11 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
if (!agp_find_seg_in_client(client, offset, size, vma->vm_page_prot))
goto out_inval;
if (remap_page_range(vma, vma->vm_start, (kerninfo.aper_base + offset),
size, vma->vm_page_prot)) {
if (kerninfo.vm_ops) {
vma->vm_ops = kerninfo.vm_ops;
} else if (remap_page_range(vma, vma->vm_start,
(kerninfo.aper_base + offset),
size, vma->vm_page_prot)) {
goto out_again;
}
AGP_UNLOCK();
......@@ -623,8 +627,11 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
if (size != current_size)
goto out_inval;
if (remap_page_range(vma, vma->vm_start, kerninfo.aper_base,
size, vma->vm_page_prot)) {
if (kerninfo.vm_ops) {
vma->vm_ops = kerninfo.vm_ops;
} else if (remap_page_range(vma, vma->vm_start,
kerninfo.aper_base,
size, vma->vm_page_prot)) {
goto out_again;
}
AGP_UNLOCK();
......
drivers/char/agp/generic-3.0.c
View file @ 3d9d6859
......@@ -77,7 +77,7 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
struct agp_3_0_dev *dev;
};
struct pci_dev *td = agp_bridge.dev, *dev;
struct pci_dev *td = agp_bridge->dev, *dev;
struct list_head *head = &dev_list->list, *pos;
struct agp_3_0_dev *cur;
struct isoch_data *master, target;
......@@ -117,8 +117,8 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0)
goto free_and_exit;
pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
/* Extract power-on defaults from the target */
target.maxbw = (tnistat >> 16) & 0xff;
......@@ -170,13 +170,13 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
* in the target's NISTAT register, so we need to do this now
* to get an accurate value for ISOCH_N later.
*/
pci_read_config_word(td, agp_bridge.capndx + 0x20, &tnicmd);
pci_read_config_word(td, agp_bridge->capndx + 0x20, &tnicmd);
tnicmd &= ~(0x3 << 6);
tnicmd |= target.y << 6;
pci_write_config_word(td, agp_bridge.capndx + 0x20, tnicmd);
pci_write_config_word(td, agp_bridge->capndx + 0x20, tnicmd);
/* Reread the target's ISOCH_N */
pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
target.n = (tnistat >> 8) & 0xff;
/* Calculate the minimum ISOCH_N needed by each master */
......@@ -296,7 +296,7 @@ static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsi
u32 trq, mrq, rem;
unsigned int cdev = 0;
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x04, &tstatus);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x04, &tstatus);
trq = (tstatus >> 24) & 0xff;
mrq = trq / ndevs;
......@@ -321,7 +321,7 @@ static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsi
*/
static int agp_3_0_node_enable(u32 mode, u32 minor)
{
struct pci_dev *td = agp_bridge.dev, *dev;
struct pci_dev *td = agp_bridge->dev, *dev;
u8 bus_num, mcapndx;
u32 isoch, arqsz, cal_cycle, tmp, rate;
u32 tstatus, tcmd, mcmd, mstatus, ncapid;
......@@ -364,7 +364,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
}
/* Extract some power-on defaults from the target */
pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
isoch = (tstatus >> 17) & 0x1;
arqsz = (tstatus >> 13) & 0x7;
cal_cycle = (tstatus >> 10) & 0x7;
......@@ -470,7 +470,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
* Also set the AGP_ENABLE bit, effectively 'turning on' the
* target (this has to be done _before_ turning on the masters).
*/
pci_read_config_dword(td, agp_bridge.capndx + 0x08, &tcmd);
pci_read_config_dword(td, agp_bridge->capndx + 0x08, &tcmd);
tcmd &= ~(0x7 << 10);
tcmd &= ~0x7;
......@@ -479,7 +479,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
tcmd |= 0x1 << 8;
tcmd |= rate;
pci_write_config_dword(td, agp_bridge.capndx + 0x08, tcmd);
pci_write_config_dword(td, agp_bridge->capndx + 0x08, tcmd);
/*
* Set the target's advertised arqsz value, the minimum supported
......@@ -525,11 +525,11 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
* (AGP 3.0 devices are required to operate as AGP 2.0 devices
* when not using 3.0 electricals.
*/
int agp_generic_agp_3_0_enable(u32 mode)
void agp_generic_agp_3_0_enable(u32 mode)
{
u32 ncapid, major, minor, agp_3_0;
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx, &ncapid);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid);
major = (ncapid >> 20) & 0xf;
minor = (ncapid >> 16) & 0xf;
......@@ -537,16 +537,13 @@ int agp_generic_agp_3_0_enable(u32 mode)
printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n",major, minor);
if(major >= 3) {
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x4, &agp_3_0);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0);
/*
* Check to see if we are operating in 3.0 mode
*/
if((agp_3_0 >> 3) & 0x1) {
if((agp_3_0 >> 3) & 0x1)
agp_3_0_node_enable(mode, minor);
return TRUE;
}
}
return FALSE;
}
EXPORT_SYMBOL(agp_generic_agp_3_0_enable);
......
drivers/char/agp/generic.c
View file @ 3d9d6859
......@@ -52,16 +52,16 @@ void agp_free_key(int key)
return;
if (key < MAXKEY)
clear_bit(key, agp_bridge.key_list);
clear_bit(key, agp_bridge->key_list);
}
static int agp_get_key(void)
{
int bit;
bit = find_first_zero_bit(agp_bridge.key_list, MAXKEY);
bit = find_first_zero_bit(agp_bridge->key_list, MAXKEY);
if (bit < MAXKEY) {
set_bit(bit, agp_bridge.key_list);
set_bit(bit, agp_bridge->key_list);
return bit;
}
return -1;
......@@ -96,21 +96,21 @@ agp_memory *agp_create_memory(int scratch_pages)
void agp_free_memory(agp_memory * curr)
{
int i;
size_t i;
if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL))
if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL))
return;
if (curr->is_bound == TRUE)
agp_unbind_memory(curr);
if (curr->type != 0) {
agp_bridge.free_by_type(curr);
agp_bridge->free_by_type(curr);
return;
}
if (curr->page_count != 0) {
for (i = 0; i < curr->page_count; i++) {
agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[i]));
agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[i]));
}
}
agp_free_key(curr->key);
......@@ -124,16 +124,16 @@ agp_memory *agp_allocate_memory(size_t page_count, u32 type)
{
int scratch_pages;
agp_memory *new;
int i;
size_t i;
if (agp_bridge.type == NOT_SUPPORTED)
if (agp_bridge->type == NOT_SUPPORTED)
return NULL;
if ((atomic_read(&agp_bridge.current_memory_agp) + page_count) > agp_bridge.max_memory_agp)
if ((atomic_read(&agp_bridge->current_memory_agp) + page_count) > agp_bridge->max_memory_agp)
return NULL;
if (type != 0) {
new = agp_bridge.alloc_by_type(page_count, type);
new = agp_bridge->alloc_by_type(page_count, type);
return new;
}
......@@ -145,7 +145,7 @@ agp_memory *agp_allocate_memory(size_t page_count, u32 type)
return NULL;
for (i = 0; i < page_count; i++) {
void *addr = agp_bridge.agp_alloc_page();
void *addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
agp_free_memory(new);
......@@ -167,9 +167,9 @@ static int agp_return_size(void)
int current_size;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
switch (agp_bridge.size_type) {
switch (agp_bridge->size_type) {
case U8_APER_SIZE:
current_size = A_SIZE_8(temp)->size;
break;
......@@ -201,9 +201,9 @@ int agp_num_entries(void)
int num_entries;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
switch (agp_bridge.size_type) {
switch (agp_bridge->size_type) {
case U8_APER_SIZE:
num_entries = A_SIZE_8(temp)->num_entries;
break;
......@@ -235,20 +235,21 @@ int agp_num_entries(void)
int agp_copy_info(agp_kern_info * info)
{
memset(info, 0, sizeof(agp_kern_info));
if (agp_bridge.type == NOT_SUPPORTED) {
info->chipset = agp_bridge.type;
if (agp_bridge->type == NOT_SUPPORTED) {
info->chipset = agp_bridge->type;
return -EIO;
}
info->version.major = agp_bridge.version->major;
info->version.minor = agp_bridge.version->minor;
info->device = agp_bridge.dev;
info->chipset = agp_bridge.type;
info->mode = agp_bridge.mode;
info->aper_base = agp_bridge.gart_bus_addr;
info->version.major = agp_bridge->version->major;
info->version.minor = agp_bridge->version->minor;
info->device = agp_bridge->dev;
info->chipset = agp_bridge->type;
info->mode = agp_bridge->mode;
info->aper_base = agp_bridge->gart_bus_addr;
info->aper_size = agp_return_size();
info->max_memory = agp_bridge.max_memory_agp;
info->current_memory = atomic_read(&agp_bridge.current_memory_agp);
info->cant_use_aperture = agp_bridge.cant_use_aperture;
info->max_memory = agp_bridge->max_memory_agp;
info->current_memory = atomic_read(&agp_bridge->current_memory_agp);
info->cant_use_aperture = agp_bridge->cant_use_aperture;
info->vm_ops = agp_bridge->vm_ops;
info->page_mask = ~0UL;
return 0;
}
......@@ -265,7 +266,7 @@ int agp_bind_memory(agp_memory * curr, off_t pg_start)
{
int ret_val;
if ((agp_bridge.type == NOT_SUPPORTED) ||
if ((agp_bridge->type == NOT_SUPPORTED) ||
(curr == NULL) || (curr->is_bound == TRUE)) {
return -EINVAL;
}
......@@ -273,7 +274,7 @@ int agp_bind_memory(agp_memory * curr, off_t pg_start)
CACHE_FLUSH();
curr->is_flushed = TRUE;
}
ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type);
ret_val = agp_bridge->insert_memory(curr, pg_start, curr->type);
if (ret_val != 0)
return ret_val;
......@@ -287,13 +288,13 @@ int agp_unbind_memory(agp_memory * curr)
{
int ret_val;
if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL))
if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL))
return -EINVAL;
if (curr->is_bound != TRUE)
return -EINVAL;
ret_val = agp_bridge.remove_memory(curr, curr->pg_start, curr->type);
ret_val = agp_bridge->remove_memory(curr, curr->pg_start, curr->type);
if (ret_val != 0)
return ret_val;
......@@ -395,15 +396,15 @@ void agp_generic_agp_enable(u32 mode)
{
u32 command;
pci_read_config_dword(agp_bridge.dev,
agp_bridge.capndx + PCI_AGP_STATUS,
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
pci_write_config_dword(agp_bridge.dev,
agp_bridge.capndx + PCI_AGP_COMMAND,
pci_write_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
......@@ -421,17 +422,17 @@ int agp_generic_create_gatt_table(void)
struct page *page;
/* The generic routines can't handle 2 level gatt's */
if (agp_bridge.size_type == LVL2_APER_SIZE)
if (agp_bridge->size_type == LVL2_APER_SIZE)
return -EINVAL;
table = NULL;
i = agp_bridge.aperture_size_idx;
temp = agp_bridge.current_size;
i = agp_bridge->aperture_size_idx;
temp = agp_bridge->current_size;
size = page_order = num_entries = 0;
if (agp_bridge.size_type != FIXED_APER_SIZE) {
if (agp_bridge->size_type != FIXED_APER_SIZE) {
do {
switch (agp_bridge.size_type) {
switch (agp_bridge->size_type) {
case U8_APER_SIZE:
size = A_SIZE_8(temp)->size;
page_order =
......@@ -462,15 +463,15 @@ int agp_generic_create_gatt_table(void)
if (table == NULL) {
i++;
switch (agp_bridge.size_type) {
switch (agp_bridge->size_type) {
case U8_APER_SIZE:
agp_bridge.current_size = A_IDX8();
agp_bridge->current_size = A_IDX8();
break;
case U16_APER_SIZE:
agp_bridge.current_size = A_IDX16();
agp_bridge->current_size = A_IDX16();
break;
case U32_APER_SIZE:
agp_bridge.current_size = A_IDX32();
agp_bridge->current_size = A_IDX32();
break;
/* This case will never really
* happen.
......@@ -478,15 +479,15 @@ int agp_generic_create_gatt_table(void)
case FIXED_APER_SIZE:
case LVL2_APER_SIZE:
default:
agp_bridge.current_size =
agp_bridge.current_size;
agp_bridge->current_size =
agp_bridge->current_size;
break;
}
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
} else {
agp_bridge.aperture_size_idx = i;
agp_bridge->aperture_size_idx = i;
}
} while ((table == NULL) && (i < agp_bridge.num_aperture_sizes));
} while ((table == NULL) && (i < agp_bridge->num_aperture_sizes));
} else {
size = ((struct aper_size_info_fixed *) temp)->size;
page_order = ((struct aper_size_info_fixed *) temp)->page_order;
......@@ -502,14 +503,14 @@ int agp_generic_create_gatt_table(void)
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
SetPageReserved(page);
agp_bridge.gatt_table_real = (u32 *) table;
agp_bridge->gatt_table_real = (u32 *) table;
agp_gatt_table = (void *)table;
CACHE_FLUSH();
agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
agp_bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
(PAGE_SIZE * (1 << page_order)));
CACHE_FLUSH();
if (agp_bridge.gatt_table == NULL) {
if (agp_bridge->gatt_table == NULL) {
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
......@@ -517,11 +518,11 @@ int agp_generic_create_gatt_table(void)
return -ENOMEM;
}
agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real);
agp_bridge->gatt_bus_addr = virt_to_phys(agp_bridge->gatt_table_real);
/* AK: bogus, should encode addresses > 4GB */
for (i = 0; i < num_entries; i++)
agp_bridge.gatt_table[i] = (unsigned long) agp_bridge.scratch_page;
agp_bridge->gatt_table[i] = (unsigned long) agp_bridge->scratch_page;
return 0;
}
......@@ -543,9 +544,9 @@ int agp_generic_free_gatt_table(void)
void *temp;
struct page *page;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
switch (agp_bridge.size_type) {
switch (agp_bridge->size_type) {
case U8_APER_SIZE:
page_order = A_SIZE_8(temp)->page_order;
break;
......@@ -572,25 +573,27 @@ int agp_generic_free_gatt_table(void)
* from the table.
*/
iounmap(agp_bridge.gatt_table);
table = (char *) agp_bridge.gatt_table_real;
iounmap(agp_bridge->gatt_table);
table = (char *) agp_bridge->gatt_table_real;
table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
free_pages((unsigned long) agp_bridge.gatt_table_real, page_order);
free_pages((unsigned long) agp_bridge->gatt_table_real, page_order);
return 0;
}
int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type)
{
int i, j, num_entries;
int num_entries;
size_t i;
off_t j;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
switch (agp_bridge.size_type) {
switch (agp_bridge->size_type) {
case U8_APER_SIZE:
num_entries = A_SIZE_8(temp)->num_entries;
break;
......@@ -627,7 +630,7 @@ int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type)
j = pg_start;
while (j < (pg_start + mem->page_count)) {
if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
if (!PGE_EMPTY(agp_bridge->gatt_table[j])) {
return -EBUSY;
}
j++;
......@@ -639,16 +642,16 @@ int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type)
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
agp_bridge.gatt_table[j] =
agp_bridge.mask_memory(mem->memory[i], mem->type);
agp_bridge->gatt_table[j] =
agp_bridge->mask_memory(mem->memory[i], mem->type);
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
int agp_generic_remove_memory(agp_memory * mem, off_t pg_start, int type)
{
int i;
size_t i;
if (type != 0 || mem->type != 0) {
/* The generic routines know nothing of memory types */
......@@ -657,11 +660,11 @@ int agp_generic_remove_memory(agp_memory * mem, off_t pg_start, int type)
/* AK: bogus, should encode addresses > 4GB */
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
agp_bridge.gatt_table[i] =
(unsigned long) agp_bridge.scratch_page;
agp_bridge->gatt_table[i] =
(unsigned long) agp_bridge->scratch_page;
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -700,7 +703,7 @@ void *agp_generic_alloc_page(void)
get_page(page);
SetPageLocked(page);
atomic_inc(&agp_bridge.current_memory_agp);
atomic_inc(&agp_bridge->current_memory_agp);
return page_address(page);
}
......@@ -716,16 +719,16 @@ void agp_generic_destroy_page(void *addr)
put_page(page);
unlock_page(page);
free_page((unsigned long)addr);
atomic_dec(&agp_bridge.current_memory_agp);
atomic_dec(&agp_bridge->current_memory_agp);
}
/* End Basic Page Allocation Routines */
void agp_enable(u32 mode)
{
if (agp_bridge.type == NOT_SUPPORTED)
if (agp_bridge->type == NOT_SUPPORTED)
return;
agp_bridge.agp_enable(mode);
agp_bridge->agp_enable(mode);
}
EXPORT_SYMBOL(agp_free_memory);
......
drivers/char/agp/hp-agp.c
View file @ 3d9d6859
......@@ -176,7 +176,7 @@ static int hp_zx1_fetch_size(void)
size = hp_private.gart_size / MB(1);
hp_zx1_sizes[0].size = size;
agp_bridge.current_size = (void *) &hp_zx1_sizes[0];
agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
return size;
}
......@@ -184,10 +184,10 @@ static int hp_zx1_configure(void)
{
struct _hp_private *hp = &hp_private;
agp_bridge.gart_bus_addr = hp->gart_base;
agp_bridge.capndx = pci_find_capability(agp_bridge.dev, PCI_CAP_ID_AGP);
pci_read_config_dword(agp_bridge.dev,
agp_bridge.capndx + PCI_AGP_STATUS, &agp_bridge.mode);
agp_bridge->gart_bus_addr = hp->gart_base;
agp_bridge->capndx = pci_find_capability(agp_bridge->dev, PCI_CAP_ID_AGP);
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_STATUS, &agp_bridge->mode);
if (hp->io_pdir_owner) {
OUTREG64(hp->registers, HP_ZX1_PDIR_BASE,
......@@ -241,7 +241,7 @@ static int hp_zx1_create_gatt_table(void)
}
for (i = 0; i < hp->gatt_entries; i++) {
hp->gatt[i] = (unsigned long) agp_bridge.scratch_page;
hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
}
return 0;
......@@ -296,11 +296,11 @@ static int hp_zx1_insert_memory(agp_memory * mem, off_t pg_start, int type)
for (k = 0;
k < hp->io_pages_per_kpage;
k++, j++, paddr += hp->io_page_size) {
hp->gatt[j] = agp_bridge.mask_memory(paddr, type);
hp->gatt[j] = agp_bridge->mask_memory(paddr, type);
}
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -316,10 +316,10 @@ static int hp_zx1_remove_memory(agp_memory * mem, off_t pg_start, int type)
io_pg_start = hp->io_pages_per_kpage * pg_start;
io_pg_count = hp->io_pages_per_kpage * mem->page_count;
for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
hp->gatt[i] = agp_bridge.scratch_page;
hp->gatt[i] = agp_bridge->scratch_page;
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -330,39 +330,39 @@ static unsigned long hp_zx1_mask_memory(unsigned long addr, int type)
static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
{
agp_bridge.masks = hp_zx1_masks;
agp_bridge.dev_private_data = NULL;
agp_bridge.size_type = FIXED_APER_SIZE;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = hp_zx1_configure;
agp_bridge.fetch_size = hp_zx1_fetch_size;
agp_bridge.cleanup = hp_zx1_cleanup;
agp_bridge.tlb_flush = hp_zx1_tlbflush;
agp_bridge.mask_memory = hp_zx1_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = hp_zx1_create_gatt_table;
agp_bridge.free_gatt_table = hp_zx1_free_gatt_table;
agp_bridge.insert_memory = hp_zx1_insert_memory;
agp_bridge.remove_memory = hp_zx1_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.cant_use_aperture = 1;
agp_bridge->masks = hp_zx1_masks;
agp_bridge->dev_private_data = NULL;
agp_bridge->size_type = FIXED_APER_SIZE;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = hp_zx1_configure;
agp_bridge->fetch_size = hp_zx1_fetch_size;
agp_bridge->cleanup = hp_zx1_cleanup;
agp_bridge->tlb_flush = hp_zx1_tlbflush;
agp_bridge->mask_memory = hp_zx1_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = hp_zx1_create_gatt_table;
agp_bridge->free_gatt_table = hp_zx1_free_gatt_table;
agp_bridge->insert_memory = hp_zx1_insert_memory;
agp_bridge->remove_memory = hp_zx1_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->cant_use_aperture = 1;
return hp_zx1_ioc_init();
}
static int __init agp_find_supported_device(struct pci_dev *dev)
{
agp_bridge.dev = dev;
agp_bridge->dev = dev;
/* ZX1 LBAs can be either PCI or AGP bridges */
if (pci_find_capability(dev, PCI_CAP_ID_AGP)) {
printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n",
dev->slot_name);
agp_bridge.type = HP_ZX1;
agp_bridge.dev = dev;
agp_bridge->type = HP_ZX1;
agp_bridge->dev = dev;
return hp_zx1_setup(dev);
}
return -ENODEV;
......@@ -408,7 +408,7 @@ static int __init agp_hp_init(void)
ret_val = pci_module_init(&agp_hp_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/i460-agp.c
View file @ 3d9d6859
......@@ -96,7 +96,7 @@ static int i460_fetch_size (void)
struct aper_size_info_8 *values;
/* Determine the GART page size */
pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp);
pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
......@@ -107,9 +107,9 @@ static int i460_fetch_size (void)
return 0;
}
values = A_SIZE_8(agp_bridge.aperture_sizes);
values = A_SIZE_8(agp_bridge->aperture_sizes);
pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
/* Exit now if the IO drivers for the GART SRAMS are turned off */
if (temp & I460_SRAM_IO_DISABLE) {
......@@ -130,7 +130,7 @@ static int i460_fetch_size (void)
else
i460.dynamic_apbase = INTEL_I460_APBASE;
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
/*
* Dynamically calculate the proper num_entries and page_order values for
* the define aperture sizes. Take care not to shift off the end of
......@@ -140,11 +140,11 @@ static int i460_fetch_size (void)
values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
}
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
/* Neglect control bits when matching up size_value */
if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -166,8 +166,8 @@ static void i460_write_agpsiz (u8 size_value)
{
u8 temp;
pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ,
pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
((temp & ~I460_AGPSIZ_MASK) | size_value));
}
......@@ -175,7 +175,7 @@ static void i460_cleanup (void)
{
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
previous_size = A_SIZE_8(agp_bridge->previous_size);
i460_write_agpsiz(previous_size->size_value);
if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
......@@ -194,7 +194,7 @@ static int i460_configure (void)
temp.large = 0;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
i460_write_agpsiz(current_size->size_value);
/*
......@@ -202,14 +202,14 @@ static int i460_configure (void)
* This has to be done since the AGP aperture can be above 4GB on
* 460 based systems.
*/
pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase, &(temp.small[0]));
pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase + 4, &(temp.small[1]));
pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
/* Clear BAR control bits */
agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1);
agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch);
pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL,
pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
(scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
/*
......@@ -234,16 +234,16 @@ static int i460_create_gatt_table (void)
/*
* Load up the fixed address of the GART SRAMS which hold our GATT table.
*/
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
page_order = A_SIZE_8(temp)->page_order;
num_entries = A_SIZE_8(temp)->num_entries;
i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
/* These are no good, the should be removed from the agp_bridge strucure... */
agp_bridge.gatt_table_real = NULL;
agp_bridge.gatt_table = NULL;
agp_bridge.gatt_bus_addr = 0;
agp_bridge->gatt_table_real = NULL;
agp_bridge->gatt_table = NULL;
agp_bridge->gatt_bus_addr = 0;
for (i = 0; i < num_entries; ++i)
WR_GATT(i, 0);
......@@ -256,7 +256,7 @@ static int i460_free_gatt_table (void)
int num_entries, i;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
......@@ -284,7 +284,7 @@ static int i460_insert_memory_small_io_page (agp_memory *mem, off_t pg_start, in
io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
......@@ -306,7 +306,7 @@ static int i460_insert_memory_small_io_page (agp_memory *mem, off_t pg_start, in
for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
paddr = mem->memory[i];
for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
WR_GATT(j, agp_bridge.mask_memory(paddr, mem->type));
WR_GATT(j, agp_bridge->mask_memory(paddr, mem->type));
}
WR_FLUSH_GATT(j - 1);
return 0;
......@@ -364,7 +364,7 @@ static int i460_alloc_large_page (struct lp_desc *lp)
lp->paddr = virt_to_phys(lpage);
lp->refcount = 0;
atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp);
atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
return 0;
}
......@@ -374,7 +374,7 @@ static void i460_free_large_page (struct lp_desc *lp)
lp->alloced_map = NULL;
free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp);
atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
}
static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, int type)
......@@ -383,7 +383,7 @@ static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, i
struct lp_desc *start, *end, *lp;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
/* Figure out what pg_start means in terms of our large GART pages */
......@@ -417,7 +417,7 @@ static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, i
if (i460_alloc_large_page(lp) < 0)
return -ENOMEM;
pg = lp - i460.lp_desc;
WR_GATT(pg, agp_bridge.mask_memory(lp->paddr, 0));
WR_GATT(pg, agp_bridge->mask_memory(lp->paddr, 0));
WR_FLUSH_GATT(pg);
}
......@@ -439,7 +439,7 @@ static int i460_remove_memory_large_io_page (agp_memory * mem, off_t pg_start, i
struct lp_desc *start, *end, *lp;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
/* Figure out what pg_start means in terms of our large GART pages */
......@@ -519,43 +519,43 @@ static void i460_destroy_page (void *page)
static unsigned long i460_mask_memory (unsigned long addr, int type)
{
/* Make sure the returned address is a valid GATT entry */
return (agp_bridge.masks[0].mask
return (agp_bridge->masks[0].mask
| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12));
}
static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
{
agp_bridge.masks = i460_masks;
agp_bridge.aperture_sizes = (void *) i460_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 3;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = i460_configure;
agp_bridge.fetch_size = i460_fetch_size;
agp_bridge.cleanup = i460_cleanup;
agp_bridge.tlb_flush = i460_tlb_flush;
agp_bridge.mask_memory = i460_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = i460_create_gatt_table;
agp_bridge.free_gatt_table = i460_free_gatt_table;
agp_bridge->masks = i460_masks;
agp_bridge->aperture_sizes = (void *) i460_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 3;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = i460_configure;
agp_bridge->fetch_size = i460_fetch_size;
agp_bridge->cleanup = i460_cleanup;
agp_bridge->tlb_flush = i460_tlb_flush;
agp_bridge->mask_memory = i460_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = i460_create_gatt_table;
agp_bridge->free_gatt_table = i460_free_gatt_table;
#if I460_LARGE_IO_PAGES
agp_bridge.insert_memory = i460_insert_memory;
agp_bridge.remove_memory = i460_remove_memory;
agp_bridge.agp_alloc_page = i460_alloc_page;
agp_bridge.agp_destroy_page = i460_destroy_page;
agp_bridge->insert_memory = i460_insert_memory;
agp_bridge->remove_memory = i460_remove_memory;
agp_bridge->agp_alloc_page = i460_alloc_page;
agp_bridge->agp_destroy_page = i460_destroy_page;
#else
agp_bridge.insert_memory = i460_insert_memory_small_io_page;
agp_bridge.remove_memory = i460_remove_memory_small_io_page;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge->insert_memory = i460_insert_memory_small_io_page;
agp_bridge->remove_memory = i460_remove_memory_small_io_page;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
#endif
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 1;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 1;
return 0;
}
......@@ -571,8 +571,8 @@ static int __init agp_intel_i460_probe (struct pci_dev *dev, const struct pci_de
if (cap_ptr == 0)
return -ENODEV;
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
intel_i460_setup(dev);
i460_agp_driver.dev = dev;
agp_register_driver(&i460_agp_driver);
......@@ -605,7 +605,7 @@ static int __init agp_intel_i460_init(void)
ret_val = pci_module_init(&agp_intel_i460_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/i7x05-agp.c
View file @ 3d9d6859
......@@ -13,16 +13,16 @@ static int intel_7505_fetch_size(void)
/*
* For AGP 3.0 APSIZE is now 16 bits
*/
pci_read_config_word (agp_bridge.dev, INTEL_I7505_APSIZE, &tmp);
pci_read_config_word (agp_bridge->dev, INTEL_I7505_APSIZE, &tmp);
tmp = (tmp & 0xfff);
values = A_SIZE_16(agp_bridge.aperture_sizes);
values = A_SIZE_16(agp_bridge->aperture_sizes);
for (i=0; i < agp_bridge.num_aperture_sizes; i++) {
for (i=0; i < agp_bridge->num_aperture_sizes; i++) {
if (tmp == values[i].size_value) {
agp_bridge.previous_size = agp_bridge.current_size =
agp_bridge->previous_size = agp_bridge->current_size =
(void *)(values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -33,18 +33,18 @@ static int intel_7505_fetch_size(void)
static void intel_7505_tlbflush(agp_memory *mem)
{
u32 temp;
pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
}
static void intel_7505_cleanup(void)
{
aper_size_info_16 *previous_size;
previous_size = A_SIZE_16(agp_bridge.previous_size);
pci_write_config_byte(agp_bridge.dev, INTEL_I7505_APSIZE,
previous_size = A_SIZE_16(agp_bridge->previous_size);
pci_write_config_byte(agp_bridge->dev, INTEL_I7505_APSIZE,
previous_size->size_value);
}
......@@ -54,25 +54,25 @@ static int intel_7505_configure(void)
u32 temp;
aper_size_info_16 *current_size;
current_size = A_SIZE_16(agp_bridge.current_size);
current_size = A_SIZE_16(agp_bridge->current_size);
/* aperture size */
pci_write_config_word(agp_bridge.dev, INTEL_I7505_APSIZE,
pci_write_config_word(agp_bridge->dev, INTEL_I7505_APSIZE,
current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_I7505_NAPBASELO, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_I7505_NAPBASELO, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase */
pci_write_config_dword(agp_bridge.dev, INTEL_I7505_ATTBASE,
agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_I7505_ATTBASE,
agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, 0x0000);
/* clear error registers */
pci_write_config_byte(agp_bridge.dev, INTEL_I7505_ERRSTS, 0xff);
pci_write_config_byte(agp_bridge->dev, INTEL_I7505_ERRSTS, 0xff);
return 0;
}
......@@ -95,30 +95,30 @@ static void i7505_setup (u32 mode)
static int __init intel_7505_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_7505_sizes;
agp_bridge.size_type = U16_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_7505_configure;
agp_bridge.fetch_size = intel_7505_fetch_size;
agp_bridge.cleanup = intel_7505_cleanup;
agp_bridge.tlb_flush = intel_7505_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = i7505_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_7505_sizes;
agp_bridge->size_type = U16_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_7505_configure;
agp_bridge->fetch_size = intel_7505_fetch_size;
agp_bridge->cleanup = intel_7505_cleanup;
agp_bridge->tlb_flush = intel_7505_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = i7505_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -149,7 +149,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected Intel %s chipset\n",
devs[j].chipset_name);
agp_bridge.type = devs[j].chipset;
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
......@@ -177,10 +177,10 @@ static int __init agp_i7x05_probe (struct pci_dev *dev, const struct pci_device_
return -ENODEV;
if (agp_lookup_host_bridge(dev) != -ENODEV) {
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode)
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode)
i7x05_agp_driver.dev = dev;
agp_register_driver(&i7x05_agp_driver);
return 0;
......@@ -215,7 +215,7 @@ int __init agp_i7x05_init(void)
ret_val = pci_module_init(&agp_i7x05_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/intel-agp.c
View file @ 3d9d6859
......@@ -39,22 +39,22 @@ static int intel_i810_fetch_size(void)
u32 smram_miscc;
struct aper_size_info_fixed *values;
pci_read_config_dword(agp_bridge.dev, I810_SMRAM_MISCC, &smram_miscc);
values = A_SIZE_FIX(agp_bridge.aperture_sizes);
pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
values = A_SIZE_FIX(agp_bridge->aperture_sizes);
if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
printk(KERN_WARNING PFX "i810 is disabled\n");
return 0;
}
if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + 1);
agp_bridge.aperture_size_idx = 1;
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + 1);
agp_bridge->aperture_size_idx = 1;
return values[1].size;
} else {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values);
agp_bridge.aperture_size_idx = 0;
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values);
agp_bridge->aperture_size_idx = 0;
return values[0].size;
}
......@@ -67,7 +67,7 @@ static int intel_i810_configure(void)
u32 temp;
int i;
current_size = A_SIZE_FIX(agp_bridge.current_size);
current_size = A_SIZE_FIX(agp_bridge->current_size);
pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
temp &= 0xfff80000;
......@@ -81,16 +81,16 @@ static int intel_i810_configure(void)
intel_i810_private.num_dcache_entries = 1024;
}
pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
OUTREG32(intel_i810_private.registers, I810_PGETBL_CTL,
agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED);
CACHE_FLUSH();
if (agp_bridge.needs_scratch_page == TRUE) {
if (agp_bridge->needs_scratch_page == TRUE) {
for (i = 0; i < current_size->num_entries; i++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (i * 4),
agp_bridge.scratch_page);
agp_bridge->scratch_page);
}
}
return 0;
......@@ -118,14 +118,14 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
int i, j, num_entries;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if ((pg_start + mem->page_count) > num_entries) {
return -EINVAL;
}
for (j = pg_start; j < (pg_start + mem->page_count); j++) {
if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
if (!PGE_EMPTY(agp_bridge->gatt_table[j])) {
return -EBUSY;
}
}
......@@ -141,7 +141,7 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
I810_PTE_VALID);
}
CACHE_FLUSH();
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
......@@ -154,11 +154,11 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (j * 4),
agp_bridge.mask_memory(mem->memory[i], mem->type));
agp_bridge->mask_memory(mem->memory[i], mem->type));
}
CACHE_FLUSH();
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -170,11 +170,11 @@ static int intel_i810_remove_entries(agp_memory * mem, off_t pg_start,
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (i * 4),
agp_bridge.scratch_page);
agp_bridge->scratch_page);
}
CACHE_FLUSH();
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -211,7 +211,7 @@ static agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
if (new == NULL)
return NULL;
addr = agp_bridge.agp_alloc_page();
addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
/* Free this structure */
......@@ -232,7 +232,7 @@ static void intel_i810_free_by_type(agp_memory * curr)
{
agp_free_key(curr->key);
if(curr->type == AGP_PHYS_MEMORY) {
agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[0]));
agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[0]));
vfree(curr->memory);
}
kfree(curr);
......@@ -241,37 +241,37 @@ static void intel_i810_free_by_type(agp_memory * curr)
static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
{
/* Type checking must be done elsewhere */
return addr | agp_bridge.masks[type].mask;
return addr | agp_bridge->masks[type].mask;
}
static int __init intel_i810_setup(struct pci_dev *i810_dev)
{
intel_i810_private.i810_dev = i810_dev;
agp_bridge.masks = intel_i810_masks;
agp_bridge.aperture_sizes = (void *) intel_i810_sizes;
agp_bridge.size_type = FIXED_APER_SIZE;
agp_bridge.num_aperture_sizes = 2;
agp_bridge.dev_private_data = (void *) &intel_i810_private;
agp_bridge.needs_scratch_page = TRUE;
agp_bridge.configure = intel_i810_configure;
agp_bridge.fetch_size = intel_i810_fetch_size;
agp_bridge.cleanup = intel_i810_cleanup;
agp_bridge.tlb_flush = intel_i810_tlbflush;
agp_bridge.mask_memory = intel_i810_mask_memory;
agp_bridge.agp_enable = intel_i810_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = intel_i810_insert_entries;
agp_bridge.remove_memory = intel_i810_remove_entries;
agp_bridge.alloc_by_type = intel_i810_alloc_by_type;
agp_bridge.free_by_type = intel_i810_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_i810_masks;
agp_bridge->aperture_sizes = (void *) intel_i810_sizes;
agp_bridge->size_type = FIXED_APER_SIZE;
agp_bridge->num_aperture_sizes = 2;
agp_bridge->dev_private_data = (void *) &intel_i810_private;
agp_bridge->needs_scratch_page = TRUE;
agp_bridge->configure = intel_i810_configure;
agp_bridge->fetch_size = intel_i810_fetch_size;
agp_bridge->cleanup = intel_i810_cleanup;
agp_bridge->tlb_flush = intel_i810_tlbflush;
agp_bridge->mask_memory = intel_i810_mask_memory;
agp_bridge->agp_enable = intel_i810_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = intel_i810_insert_entries;
agp_bridge->remove_memory = intel_i810_remove_entries;
agp_bridge->alloc_by_type = intel_i810_alloc_by_type;
agp_bridge->free_by_type = intel_i810_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -296,7 +296,7 @@ static void intel_i830_init_gtt_entries(void)
u8 rdct;
static const int ddt[4] = { 0, 16, 32, 64 };
pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
case I830_GMCH_GMS_STOLEN_512:
......@@ -337,10 +337,10 @@ static int intel_i830_create_gatt_table(void)
int num_entries;
u32 temp;
size = agp_bridge.current_size;
size = agp_bridge->current_size;
page_order = size->page_order;
num_entries = size->num_entries;
agp_bridge.gatt_table_real = 0;
agp_bridge->gatt_table_real = 0;
pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
temp &= 0xfff80000;
......@@ -354,9 +354,9 @@ static int intel_i830_create_gatt_table(void)
/* we have to call this as early as possible after the MMIO base address is known */
intel_i830_init_gtt_entries();
agp_bridge.gatt_table = NULL;
agp_bridge->gatt_table = NULL;
agp_bridge.gatt_bus_addr = temp;
agp_bridge->gatt_bus_addr = temp;
return(0);
}
......@@ -374,16 +374,16 @@ static int intel_i830_fetch_size(void)
u16 gmch_ctrl;
struct aper_size_info_fixed *values;
pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
values = A_SIZE_FIX(agp_bridge.aperture_sizes);
pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
values = A_SIZE_FIX(agp_bridge->aperture_sizes);
if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
agp_bridge.aperture_size_idx = 0;
agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
agp_bridge->aperture_size_idx = 0;
return(values[0].size);
} else {
agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
agp_bridge.aperture_size_idx = 1;
agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
agp_bridge->aperture_size_idx = 1;
return(values[1].size);
}
......@@ -397,21 +397,21 @@ static int intel_i830_configure(void)
u16 gmch_ctrl;
int i;
current_size = A_SIZE_FIX(agp_bridge.current_size);
current_size = A_SIZE_FIX(agp_bridge->current_size);
pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
gmch_ctrl |= I830_GMCH_ENABLED;
pci_write_config_word(agp_bridge.dev,I830_GMCH_CTRL,gmch_ctrl);
pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED);
CACHE_FLUSH();
if (agp_bridge.needs_scratch_page == TRUE)
if (agp_bridge->needs_scratch_page == TRUE)
for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++)
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page);
return (0);
}
......@@ -426,7 +426,7 @@ static int intel_i830_insert_entries(agp_memory *mem,off_t pg_start,int type)
int i,j,num_entries;
void *temp;
temp = agp_bridge.current_size;
temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if (pg_start < intel_i830_private.gtt_entries) {
......@@ -452,11 +452,11 @@ static int intel_i830_insert_entries(agp_memory *mem,off_t pg_start,int type)
for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4),
agp_bridge.mask_memory(mem->memory[i], mem->type));
agp_bridge->mask_memory(mem->memory[i], mem->type));
CACHE_FLUSH();
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return(0);
}
......@@ -473,11 +473,11 @@ static int intel_i830_remove_entries(agp_memory *mem,off_t pg_start,int type)
}
for (i = pg_start; i < (mem->page_count + pg_start); i++)
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page);
CACHE_FLUSH();
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return (0);
}
......@@ -504,7 +504,7 @@ static agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
if (nw == NULL) return(NULL);
addr = agp_bridge.agp_alloc_page();
addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
/* free this structure */
agp_free_memory(nw);
......@@ -526,35 +526,35 @@ static int __init intel_i830_setup(struct pci_dev *i830_dev)
{
intel_i830_private.i830_dev = i830_dev;
agp_bridge.masks = intel_i810_masks;
agp_bridge.aperture_sizes = (void *) intel_i830_sizes;
agp_bridge.size_type = FIXED_APER_SIZE;
agp_bridge.num_aperture_sizes = 2;
agp_bridge->masks = intel_i810_masks;
agp_bridge->aperture_sizes = (void *) intel_i830_sizes;
agp_bridge->size_type = FIXED_APER_SIZE;
agp_bridge->num_aperture_sizes = 2;
agp_bridge.dev_private_data = (void *) &intel_i830_private;
agp_bridge.needs_scratch_page = TRUE;
agp_bridge->dev_private_data = (void *) &intel_i830_private;
agp_bridge->needs_scratch_page = TRUE;
agp_bridge.configure = intel_i830_configure;
agp_bridge.fetch_size = intel_i830_fetch_size;
agp_bridge.cleanup = intel_i830_cleanup;
agp_bridge.tlb_flush = intel_i810_tlbflush;
agp_bridge.mask_memory = intel_i810_mask_memory;
agp_bridge.agp_enable = intel_i810_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge->configure = intel_i830_configure;
agp_bridge->fetch_size = intel_i830_fetch_size;
agp_bridge->cleanup = intel_i830_cleanup;
agp_bridge->tlb_flush = intel_i810_tlbflush;
agp_bridge->mask_memory = intel_i810_mask_memory;
agp_bridge->agp_enable = intel_i810_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = intel_i830_create_gatt_table;
agp_bridge.free_gatt_table = intel_i830_free_gatt_table;
agp_bridge->create_gatt_table = intel_i830_create_gatt_table;
agp_bridge->free_gatt_table = intel_i830_free_gatt_table;
agp_bridge.insert_memory = intel_i830_insert_entries;
agp_bridge.remove_memory = intel_i830_remove_entries;
agp_bridge.alloc_by_type = intel_i830_alloc_by_type;
agp_bridge.free_by_type = intel_i810_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge->insert_memory = intel_i830_insert_entries;
agp_bridge->remove_memory = intel_i830_remove_entries;
agp_bridge->alloc_by_type = intel_i830_alloc_by_type;
agp_bridge->free_by_type = intel_i810_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return(0);
}
......@@ -564,13 +564,13 @@ static int intel_fetch_size(void)
u16 temp;
struct aper_size_info_16 *values;
pci_read_config_word(agp_bridge.dev, INTEL_APSIZE, &temp);
values = A_SIZE_16(agp_bridge.aperture_sizes);
pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
values = A_SIZE_16(agp_bridge->aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -584,20 +584,20 @@ static int intel_8xx_fetch_size(void)
u8 temp;
struct aper_size_info_8 *values;
pci_read_config_byte(agp_bridge.dev, INTEL_APSIZE, &temp);
pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
/* Intel 815 chipsets have a _weird_ APSIZE register with only
* one non-reserved bit, so mask the others out ... */
if (agp_bridge.type == INTEL_I815)
if (agp_bridge->type == INTEL_I815)
temp &= (1 << 3);
values = A_SIZE_8(agp_bridge.aperture_sizes);
values = A_SIZE_8(agp_bridge->aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -607,18 +607,18 @@ static int intel_8xx_fetch_size(void)
static void intel_tlbflush(agp_memory * mem)
{
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2200);
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
}
static void intel_8xx_tlbflush(agp_memory * mem)
{
u32 temp;
pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp & ~(1 << 7));
pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp | (1 << 7));
pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
}
......@@ -627,10 +627,10 @@ static void intel_cleanup(void)
u16 temp;
struct aper_size_info_16 *previous_size;
previous_size = A_SIZE_16(agp_bridge.previous_size);
pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value);
previous_size = A_SIZE_16(agp_bridge->previous_size);
pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
}
......@@ -639,10 +639,10 @@ static void intel_8xx_cleanup(void)
u16 temp;
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value);
previous_size = A_SIZE_8(agp_bridge->previous_size);
pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
}
......@@ -652,27 +652,27 @@ static int intel_configure(void)
u16 temp2;
struct aper_size_info_16 *current_size;
current_size = A_SIZE_16(agp_bridge.current_size);
current_size = A_SIZE_16(agp_bridge->current_size);
/* aperture size */
pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
/* paccfg/nbxcfg */
pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG,
pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
(temp2 & ~(1 << 10)) | (1 << 9));
/* clear any possible error conditions */
pci_write_config_byte(agp_bridge.dev, INTEL_ERRSTS + 1, 7);
pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
return 0;
}
......@@ -682,32 +682,32 @@ static int intel_815_configure(void)
u8 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
/* the Intel 815 chipset spec. says that bits 29-31 in the
* ATTBASE register are reserved -> try not to write them */
if (agp_bridge.gatt_bus_addr & INTEL_815_ATTBASE_MASK)
if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK)
panic("gatt bus addr too high");
pci_read_config_dword(agp_bridge.dev, INTEL_ATTBASE, &addr);
pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
addr &= INTEL_815_ATTBASE_MASK;
addr |= agp_bridge.gatt_bus_addr;
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, addr);
addr |= agp_bridge->gatt_bus_addr;
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* apcont */
pci_read_config_byte(agp_bridge.dev, INTEL_815_APCONT, &temp2);
pci_write_config_byte(agp_bridge.dev, INTEL_815_APCONT, temp2 | (1 << 1));
pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
/* clear any possible error conditions */
/* Oddness : this chipset seems to have no ERRSTS register ! */
......@@ -724,11 +724,11 @@ static void intel_820_cleanup(void)
u8 temp;
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp);
pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR,
previous_size = A_SIZE_8(agp_bridge->previous_size);
pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
temp & ~(1 << 1));
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
previous_size->size_value);
}
......@@ -739,28 +739,28 @@ static int intel_820_configure(void)
u8 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* global enable aperture access */
/* This flag is not accessed through MCHCFG register as in */
/* i850 chipset. */
pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp2);
pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR, temp2 | (1 << 1));
pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
/* clear any possible AGP-related error conditions */
pci_write_config_word(agp_bridge.dev, INTEL_I820_ERRSTS, 0x001c);
pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
return 0;
}
......@@ -770,26 +770,26 @@ static int intel_840_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
pci_read_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, &temp2);
pci_write_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
/* clear any possible error conditions */
pci_write_config_word(agp_bridge.dev, INTEL_I840_ERRSTS, 0xc000);
pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
return 0;
}
......@@ -799,26 +799,26 @@ static int intel_845_configure(void)
u8 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* agpm */
pci_read_config_byte(agp_bridge.dev, INTEL_I845_AGPM, &temp2);
pci_write_config_byte(agp_bridge.dev, INTEL_I845_AGPM, temp2 | (1 << 1));
pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
/* clear any possible error conditions */
pci_write_config_word(agp_bridge.dev, INTEL_I845_ERRSTS, 0x001c);
pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
return 0;
}
......@@ -833,26 +833,26 @@ static int intel_850_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
pci_read_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, &temp2);
pci_write_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
pci_write_config_word(agp_bridge.dev, INTEL_I850_ERRSTS, 0x001c);
pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
return 0;
}
......@@ -862,26 +862,26 @@ static int intel_860_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
pci_read_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, &temp2);
pci_write_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
pci_write_config_word(agp_bridge.dev, INTEL_I860_ERRSTS, 0xf700);
pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
return 0;
}
......@@ -891,33 +891,33 @@ static int intel_830mp_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* gmch */
pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp2 | (1 << 9));
pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
pci_write_config_word(agp_bridge.dev, INTEL_I830_ERRSTS, 0x1c);
pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
return 0;
}
static unsigned long intel_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
static void intel_resume(void)
......@@ -969,234 +969,234 @@ static struct aper_size_info_8 intel_830mp_sizes[4] =
static int __init intel_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_generic_sizes;
agp_bridge.size_type = U16_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_configure;
agp_bridge.fetch_size = intel_fetch_size;
agp_bridge.cleanup = intel_cleanup;
agp_bridge.tlb_flush = intel_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = intel_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_generic_sizes;
agp_bridge->size_type = U16_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_configure;
agp_bridge->fetch_size = intel_fetch_size;
agp_bridge->cleanup = intel_cleanup;
agp_bridge->tlb_flush = intel_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = intel_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_815_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_815_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 2;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_815_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_8xx_cleanup;
agp_bridge.tlb_flush = intel_8xx_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_815_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 2;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_815_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_8xx_cleanup;
agp_bridge->tlb_flush = intel_8xx_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_820_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_820_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_820_cleanup;
agp_bridge.tlb_flush = intel_820_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_820_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_820_cleanup;
agp_bridge->tlb_flush = intel_820_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_830mp_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_830mp_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 4;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_830mp_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_8xx_cleanup;
agp_bridge.tlb_flush = intel_8xx_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_830mp_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 4;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_830mp_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_8xx_cleanup;
agp_bridge->tlb_flush = intel_8xx_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_840_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_840_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_8xx_cleanup;
agp_bridge.tlb_flush = intel_8xx_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_840_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_8xx_cleanup;
agp_bridge->tlb_flush = intel_8xx_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_845_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_845_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_8xx_cleanup;
agp_bridge.tlb_flush = intel_8xx_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = intel_845_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_845_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_8xx_cleanup;
agp_bridge->tlb_flush = intel_8xx_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = intel_845_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_850_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_850_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_8xx_cleanup;
agp_bridge.tlb_flush = intel_8xx_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_850_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_8xx_cleanup;
agp_bridge->tlb_flush = intel_8xx_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_860_setup (struct pci_dev *pdev)
{
agp_bridge.masks = intel_generic_masks;
agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = intel_860_configure;
agp_bridge.fetch_size = intel_8xx_fetch_size;
agp_bridge.cleanup = intel_8xx_cleanup;
agp_bridge.tlb_flush = intel_8xx_tlbflush;
agp_bridge.mask_memory = intel_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = intel_generic_masks;
agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = intel_860_configure;
agp_bridge->fetch_size = intel_8xx_fetch_size;
agp_bridge->cleanup = intel_8xx_cleanup;
agp_bridge->tlb_flush = intel_8xx_tlbflush;
agp_bridge->mask_memory = intel_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -1287,7 +1287,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected Intel %s chipset\n",
devs[j].chipset_name);
agp_bridge.type = devs[j].chipset;
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
......@@ -1302,7 +1302,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic Intel routines"
" for device id: %04x\n", pdev->device);
agp_bridge.type = INTEL_GENERIC;
agp_bridge->type = INTEL_GENERIC;
return intel_generic_setup(pdev);
}
......@@ -1319,7 +1319,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
struct pci_dev *i810_dev;
u8 cap_ptr = 0;
agp_bridge.dev = dev;
agp_bridge->dev = dev;
/* This shit needs moving into tables/init-routines. */
switch (dev->device) {
......@@ -1331,7 +1331,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 Chipset.\n");
agp_bridge.type = INTEL_I810;
agp_bridge->type = INTEL_I810;
return intel_i810_setup (i810_dev);
case PCI_DEVICE_ID_INTEL_82810_MC3:
......@@ -1342,7 +1342,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 DC100 Chipset.\n");
agp_bridge.type = INTEL_I810;
agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82810E_MC:
......@@ -1353,7 +1353,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 E Chipset.\n");
agp_bridge.type = INTEL_I810;
agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82815_MC:
......@@ -1371,7 +1371,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
break;
}
printk(KERN_INFO PFX "agpgart: Detected an Intel i815 Chipset.\n");
agp_bridge.type = INTEL_I810;
agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82845G_HB:
......@@ -1387,11 +1387,11 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
* We probably have a I845MP chipset with an external graphics
* card. It will be initialized later
*/
agp_bridge.type = INTEL_I845_G;
agp_bridge->type = INTEL_I845_G;
break;
}
printk(KERN_INFO PFX "Detected an Intel 845G Chipset.\n");
agp_bridge.type = INTEL_I810;
agp_bridge->type = INTEL_I810;
return intel_i830_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82830_HB:
......@@ -1402,11 +1402,11 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
if (i810_dev == NULL) {
/* Intel 830MP with external graphic card */
/* It will be initialized later */
agp_bridge.type = INTEL_I830_M;
agp_bridge->type = INTEL_I830_M;
break;
}
printk(KERN_INFO PFX "Detected an Intel 830M Chipset.\n");
agp_bridge.type = INTEL_I810;
agp_bridge->type = INTEL_I810;
return intel_i830_setup(i810_dev);
default:
......@@ -1416,10 +1416,10 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
agp_bridge.capndx = cap_ptr;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
/* probe for known chipsets */
return agp_lookup_host_bridge(dev);
......@@ -1472,7 +1472,7 @@ int __init agp_intel_init(void)
ret_val = pci_module_init(&agp_intel_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/sis-agp.c
View file @ 3d9d6859
......@@ -16,16 +16,16 @@ static int sis_fetch_size(void)
int i;
struct aper_size_info_8 *values;
pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size);
values = A_SIZE_8(agp_bridge.aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
values = A_SIZE_8(agp_bridge->aperture_sizes);
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if ((temp_size == values[i].size_value) ||
((temp_size & ~(0x03)) ==
(values[i].size_value & ~(0x03)))) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -35,7 +35,7 @@ static int sis_fetch_size(void)
static void sis_tlbflush(agp_memory * mem)
{
pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02);
pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
}
static int sis_configure(void)
......@@ -43,13 +43,13 @@ static int sis_configure(void)
u32 temp;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05);
pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE,
agp_bridge.gatt_bus_addr);
pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
current_size = A_SIZE_8(agp_bridge->current_size);
pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
pci_read_config_dword(agp_bridge->dev, SIS_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
agp_bridge->gatt_bus_addr);
pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
current_size->size_value);
return 0;
}
......@@ -58,8 +58,8 @@ static void sis_cleanup(void)
{
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
previous_size = A_SIZE_8(agp_bridge->previous_size);
pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
(previous_size->size_value & ~(0x03)));
}
......@@ -67,7 +67,7 @@ static unsigned long sis_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
static struct aper_size_info_8 sis_generic_sizes[7] =
......@@ -88,30 +88,30 @@ static struct gatt_mask sis_generic_masks[] =
static int __init sis_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = sis_generic_masks;
agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = sis_configure;
agp_bridge.fetch_size = sis_fetch_size;
agp_bridge.cleanup = sis_cleanup;
agp_bridge.tlb_flush = sis_tlbflush;
agp_bridge.mask_memory = sis_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
agp_bridge->masks = sis_generic_masks;
agp_bridge->aperture_sizes = (void *) sis_generic_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = sis_configure;
agp_bridge->fetch_size = sis_fetch_size;
agp_bridge->cleanup = sis_cleanup;
agp_bridge->tlb_flush = sis_tlbflush;
agp_bridge->mask_memory = sis_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
......@@ -198,7 +198,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected SiS %s chipset\n",
devs[j].chipset_name);
agp_bridge.type = devs[j].chipset;
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
......@@ -212,7 +212,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic SiS routines"
" for device id: %04x\n", pdev->device);
agp_bridge.type = SIS_GENERIC;
agp_bridge->type = SIS_GENERIC;
return sis_generic_setup(pdev);
}
......@@ -235,10 +235,10 @@ static int __init agp_sis_probe (struct pci_dev *dev, const struct pci_device_id
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
sis_agp_driver.dev = dev;
agp_register_driver(&sis_agp_driver);
return 0;
......@@ -272,7 +272,7 @@ static int __init agp_sis_init(void)
ret_val = pci_module_init(&agp_sis_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/sworks-agp.c
View file @ 3d9d6859
......@@ -47,7 +47,7 @@ static int serverworks_create_page_map(struct serverworks_page_map *page_map)
CACHE_FLUSH();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
page_map->remapped[i] = agp_bridge.scratch_page;
page_map->remapped[i] = agp_bridge->scratch_page;
}
return 0;
......@@ -120,7 +120,7 @@ static int serverworks_create_gatt_pages(int nr_tables)
#ifndef GET_PAGE_DIR_IDX
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr))
GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#endif
#ifndef GET_GATT_OFF
......@@ -135,7 +135,7 @@ static int serverworks_create_gatt_table(void)
u32 temp;
int i;
value = A_SIZE_LVL2(agp_bridge.current_size);
value = A_SIZE_LVL2(agp_bridge->current_size);
retval = serverworks_create_page_map(&page_dir);
if (retval != 0) {
return retval;
......@@ -147,7 +147,7 @@ static int serverworks_create_gatt_table(void)
}
/* Create a fake scratch directory */
for(i = 0; i < 1024; i++) {
serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge.scratch_page;
serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;
page_dir.remapped[i] =
virt_to_phys(serverworks_private.scratch_dir.real);
page_dir.remapped[i] |= 0x00000001;
......@@ -160,17 +160,17 @@ static int serverworks_create_gatt_table(void)
return retval;
}
agp_bridge.gatt_table_real = (u32 *)page_dir.real;
agp_bridge.gatt_table = (u32 *)page_dir.remapped;
agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real);
agp_bridge->gatt_table_real = (u32 *)page_dir.real;
agp_bridge->gatt_table = (u32 *)page_dir.remapped;
agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
*/
pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* Calculate the agp offset */
......@@ -187,8 +187,8 @@ static int serverworks_free_gatt_table(void)
{
struct serverworks_page_map page_dir;
page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
serverworks_free_gatt_pages();
serverworks_free_page_map(&page_dir);
......@@ -203,20 +203,20 @@ static int serverworks_fetch_size(void)
u32 temp2;
struct aper_size_info_lvl2 *values;
values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,
values = A_SIZE_LVL2(agp_bridge->aperture_sizes);
pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
SVWRKS_SIZE_MASK);
pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp2);
pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,temp);
pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
temp2 &= SVWRKS_SIZE_MASK;
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp2 == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
......@@ -231,17 +231,17 @@ static int serverworks_configure(void)
u8 enable_reg;
u16 cap_reg;
current_size = A_SIZE_LVL2(agp_bridge.current_size);
current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
pci_read_config_dword(agp_bridge.dev, serverworks_private.mm_addr_ofs, &temp);
pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
agp_bridge.gatt_bus_addr);
agp_bridge->gatt_bus_addr);
cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
cap_reg &= ~0x0007;
......@@ -253,21 +253,21 @@ static int serverworks_configure(void)
enable_reg |= 0x1; /* Agp Enable bit */
pci_write_config_byte(serverworks_private.svrwrks_dev,
SVWRKS_AGP_ENABLE, enable_reg);
agp_bridge.tlb_flush(NULL);
agp_bridge->tlb_flush(NULL);
agp_bridge.capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
/* Fill in the mode register */
pci_read_config_dword(serverworks_private.svrwrks_dev,
agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
pci_read_config_byte(agp_bridge.dev, SVWRKS_CACHING, &enable_reg);
pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
enable_reg &= ~0x3;
pci_write_config_byte(agp_bridge.dev, SVWRKS_CACHING, enable_reg);
pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
pci_read_config_byte(agp_bridge.dev, SVWRKS_FEATURE, &enable_reg);
pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
enable_reg |= (1<<6);
pci_write_config_byte(agp_bridge.dev,SVWRKS_FEATURE, enable_reg);
pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
return 0;
}
......@@ -313,7 +313,7 @@ static unsigned long serverworks_mask_memory(unsigned long addr, int type)
{
/* Only type 0 is supported by the serverworks chipsets */
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
static int serverworks_insert_memory(agp_memory * mem,
......@@ -323,7 +323,7 @@ static int serverworks_insert_memory(agp_memory * mem,
unsigned long *cur_gatt;
unsigned long addr;
num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
if (type != 0 || mem->type != 0) {
return -EINVAL;
......@@ -334,7 +334,7 @@ static int serverworks_insert_memory(agp_memory * mem,
j = pg_start;
while (j < (pg_start + mem->page_count)) {
addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
......@@ -348,12 +348,12 @@ static int serverworks_insert_memory(agp_memory * mem,
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
agp_bridge.mask_memory(mem->memory[i], mem->type);
agp_bridge->mask_memory(mem->memory[i], mem->type);
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -369,16 +369,16 @@ static int serverworks_remove_memory(agp_memory * mem, off_t pg_start,
}
CACHE_FLUSH();
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr;
addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
(unsigned long) agp_bridge.scratch_page;
(unsigned long) agp_bridge->scratch_page;
}
agp_bridge.tlb_flush(mem);
agp_bridge->tlb_flush(mem);
return 0;
}
......@@ -403,7 +403,7 @@ static void serverworks_agp_enable(u32 mode)
u32 command;
pci_read_config_dword(serverworks_private.svrwrks_dev,
agp_bridge.capndx + PCI_AGP_STATUS,
agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
......@@ -414,7 +414,7 @@ static void serverworks_agp_enable(u32 mode)
command |= 0x100;
pci_write_config_dword(serverworks_private.svrwrks_dev,
agp_bridge.capndx + PCI_AGP_COMMAND,
agp_bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
......@@ -427,39 +427,39 @@ static int __init serverworks_setup (struct pci_dev *pdev)
serverworks_private.svrwrks_dev = pdev;
agp_bridge.masks = serverworks_masks;
agp_bridge.aperture_sizes = (void *) serverworks_sizes;
agp_bridge.size_type = LVL2_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = (void *) &serverworks_private;
agp_bridge.needs_scratch_page = TRUE;
agp_bridge.configure = serverworks_configure;
agp_bridge.fetch_size = serverworks_fetch_size;
agp_bridge.cleanup = serverworks_cleanup;
agp_bridge.tlb_flush = serverworks_tlbflush;
agp_bridge.mask_memory = serverworks_mask_memory;
agp_bridge.agp_enable = serverworks_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = serverworks_create_gatt_table;
agp_bridge.free_gatt_table = serverworks_free_gatt_table;
agp_bridge.insert_memory = serverworks_insert_memory;
agp_bridge.remove_memory = serverworks_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
pci_read_config_dword(agp_bridge.dev,
agp_bridge->masks = serverworks_masks;
agp_bridge->aperture_sizes = (void *) serverworks_sizes;
agp_bridge->size_type = LVL2_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = (void *) &serverworks_private;
agp_bridge->needs_scratch_page = TRUE;
agp_bridge->configure = serverworks_configure;
agp_bridge->fetch_size = serverworks_fetch_size;
agp_bridge->cleanup = serverworks_cleanup;
agp_bridge->tlb_flush = serverworks_tlbflush;
agp_bridge->mask_memory = serverworks_mask_memory;
agp_bridge->agp_enable = serverworks_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = serverworks_create_gatt_table;
agp_bridge->free_gatt_table = serverworks_free_gatt_table;
agp_bridge->insert_memory = serverworks_insert_memory;
agp_bridge->remove_memory = serverworks_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE,
&temp);
serverworks_private.gart_addr_ofs = 0x10;
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(agp_bridge.dev,
pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE + 4,
&temp2);
if(temp2 != 0) {
......@@ -472,11 +472,11 @@ static int __init serverworks_setup (struct pci_dev *pdev)
serverworks_private.mm_addr_ofs = 0x14;
}
pci_read_config_dword(agp_bridge.dev,
pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs,
&temp);
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(agp_bridge.dev,
pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs + 4,
&temp2);
if(temp2 != 0) {
......@@ -503,21 +503,21 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
return -ENODEV;
}
agp_bridge.dev = dev;
agp_bridge->dev = dev;
switch (dev->device) {
case PCI_DEVICE_ID_SERVERWORKS_HE:
agp_bridge.type = SVWRKS_HE;
agp_bridge->type = SVWRKS_HE;
return serverworks_setup(bridge_dev);
case PCI_DEVICE_ID_SERVERWORKS_LE:
case 0x0007:
agp_bridge.type = SVWRKS_LE;
agp_bridge->type = SVWRKS_LE;
return serverworks_setup(bridge_dev);
default:
if(agp_try_unsupported) {
agp_bridge.type = SVWRKS_GENERIC;
agp_bridge->type = SVWRKS_GENERIC;
return serverworks_setup(bridge_dev);
}
break;
......@@ -565,7 +565,7 @@ static int __init agp_serverworks_init(void)
ret_val = pci_module_init(&agp_serverworks_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
......
drivers/char/agp/via-agp.c
View file @ 3d9d6859
......@@ -11,73 +11,78 @@
static int agp_try_unsupported __initdata = 0;
static int via_fetch_size(void)
{
int i;
u8 temp;
struct aper_size_info_8 *values;
values = A_SIZE_8(agp_bridge.aperture_sizes);
pci_read_config_byte(agp_bridge.dev, VIA_APSIZE, &temp);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
values = A_SIZE_8(agp_bridge->aperture_sizes);
pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
return 0;
}
static int via_configure(void)
{
u32 temp;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
current_size->size_value);
/* address to map too */
pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* GART control register */
pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
/* attbase - aperture GATT base */
pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE,
(agp_bridge.gatt_bus_addr & 0xfffff000) | 3);
pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
(agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
return 0;
}
static void via_cleanup(void)
{
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
previous_size = A_SIZE_8(agp_bridge->previous_size);
pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
previous_size->size_value);
/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
* during reinitialization.
*/
}
static void via_tlbflush(agp_memory * mem)
{
pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000008f);
pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000008f);
pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
}
static unsigned long via_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
return addr | agp_bridge->masks[0].mask;
}
static struct aper_size_info_8 via_generic_sizes[7] =
{
{256, 65536, 6, 0},
......@@ -89,123 +94,327 @@ static struct aper_size_info_8 via_generic_sizes[7] =
{4, 1024, 0, 252}
};
static struct gatt_mask via_generic_masks[] =
{
{.mask = 0x00000000, .type = 0}
};
#ifdef CONFIG_AGP3
static int via_fetch_size_agp3(void)
{
int i;
u16 temp;
struct aper_size_info_16 *values;
values = A_SIZE_16(agp_bridge->aperture_sizes);
pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
temp &= 0xfff;
for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
return 0;
}
static int via_configure_agp3(void)
{
u32 temp;
struct aper_size_info_16 *current_size;
current_size = A_SIZE_16(agp_bridge->current_size);
/* address to map too */
pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp);
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture GATT base */
pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
agp_bridge->gatt_bus_addr & 0xfffff000);
return 0;
}
static void via_cleanup_agp3(void)
{
struct aper_size_info_16 *previous_size;
previous_size = A_SIZE_16(agp_bridge->previous_size);
pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
}
static void via_tlbflush_agp3(agp_memory * mem)
{
u32 temp;
pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
}
static struct aper_size_info_16 via_generic_agp3_sizes[11] =
{
{ 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 },
{ 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1},
{ 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2},
{ 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3},
{ 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4},
{ 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5},
{ 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8},
{ 512, 131072, 7, 1<<11|1<<10|1<<9},
{ 1024, 262144, 8, 1<<11|1<<10},
{ 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */
};
static int __init via_generic_agp3_setup (struct pci_dev *pdev)
{
agp_bridge->dev = pdev;
agp_bridge->type = VIA_GENERIC;
agp_bridge->masks = via_generic_masks;
agp_bridge->aperture_sizes = (void *) via_generic_agp3_sizes;
agp_bridge->size_type = U16_APER_SIZE;
agp_bridge->num_aperture_sizes = 10;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->agp_enable = agp_generic_agp_3_0_enable;
agp_bridge->configure = via_configure_agp3;
agp_bridge->fetch_size = via_fetch_size_agp3;
agp_bridge->cleanup = via_cleanup_agp3;
agp_bridge->tlb_flush = via_tlbflush_agp3;
agp_bridge->mask_memory = via_mask_memory;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
#else
static int __init via_generic_agp3_setup (struct pci_dev *pdev)
{
printk (KERN_INFO PFX "Bridge in AGP3 mode, but CONFIG_AGP3=n\n");
return -ENODEV;
}
#endif /* CONFIG_AGP3 */
static int __init via_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = via_generic_masks;
agp_bridge.aperture_sizes = (void *) via_generic_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = via_configure;
agp_bridge.fetch_size = via_fetch_size;
agp_bridge.cleanup = via_cleanup;
agp_bridge.tlb_flush = via_tlbflush;
agp_bridge.mask_memory = via_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
#ifdef CONFIG_AGP3
/* Garg, there are KT400s with KT266 IDs. */
if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
/* Is there a KT400 subsystem ? */
if (pdev->subsystem_device==PCI_DEVICE_ID_VIA_8377_0) {
u8 reg;
printk (KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
/* Check AGP compatability mode. */
pci_read_config_byte(pdev, VIA_AGPSEL, &reg);
if ((reg & (1<<1))==0)
return via_generic_agp3_setup(pdev);
/* Its in 2.0 mode, drop through. */
}
}
#endif
agp_bridge->masks = via_generic_masks;
agp_bridge->aperture_sizes = (void *) via_generic_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = via_configure;
agp_bridge->fetch_size = via_fetch_size;
agp_bridge->cleanup = via_cleanup;
agp_bridge->tlb_flush = via_tlbflush;
agp_bridge->mask_memory = via_mask_memory;
agp_bridge->agp_enable = agp_generic_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
/*
* The KT400 does magick to put the AGP bridge compliant with the same
* standards version as the graphics card. If we haven't fallen into
* 2.0 compatability mode, we abort, as this gets picked up by
* via-agp3.o
*/
/* The KT400 does magick to put the AGP bridge compliant with the same
* standards version as the graphics card. */
static int __init via_kt400_setup(struct pci_dev *pdev)
{
u8 reg;
pci_read_config_byte(pdev, VIA_AGPSEL, &reg);
/* Check AGP 2.0 compatability mode. */
if ((reg & (1<<1))==1) {
via_generic_setup(pdev);
return 0;
}
return -ENODEV;
if ((reg & (1<<1))==0)
return via_generic_agp3_setup(pdev);
return via_generic_setup(pdev);
}
static struct agp_device_ids via_agp_device_ids[] __initdata =
{
{
.device_id = PCI_DEVICE_ID_VIA_82C597_0,
.chipset = VIA_VP3,
.chipset_name = "VP3",
},
{
.device_id = PCI_DEVICE_ID_VIA_82C598_0,
.chipset = VIA_MVP3,
.chipset_name = "MVP3",
},
{
.device_id = PCI_DEVICE_ID_VIA_8501_0,
.chipset = VIA_MVP4,
.chipset_name = "MVP4",
},
/* VT8601 */
{
.device_id = PCI_DEVICE_ID_VIA_8601_0,
.chipset_name = "PLE133 ProMedia",
},
/* VT82C693A / VT28C694T */
{
.device_id = PCI_DEVICE_ID_VIA_82C691,
.chipset = VIA_APOLLO_PRO,
.chipset_name = "Apollo Pro",
.chipset_name = "Apollo Pro 133",
},
{
.device_id = PCI_DEVICE_ID_VIA_8371_0,
.chipset = VIA_APOLLO_KX133,
.chipset_name = "Apollo Pro KX133",
},
/* VT8633 */
{
.device_id = PCI_DEVICE_ID_VIA_8633_0,
.chipset = VIA_APOLLO_PRO_266,
.chipset_name = "Apollo Pro 266",
},
/* VT8361 */
/* {
.device_id = PCI_DEVICE_ID_VIA_8361, // 0x3112
.chipset_name = "Apollo KLE133",
}, */
/* VT8365 / VT8362 */
{
.device_id = PCI_DEVICE_ID_VIA_8363_0,
.chipset = VIA_APOLLO_KT133,
.chipset_name = "Apollo Pro KT133",
.chipset_name = "Apollo Pro KT133/KM133/TwisterK",
},
/* VT8753A */
/* {
.device_id = PCI_DEVICE_ID_VIA_8753_0, // 0x3128
.chipset_name = "P4X266",
}, */
/* VT8366 */
{
.device_id = PCI_DEVICE_ID_VIA_8367_0,
.chipset = VIA_APOLLO_KT133,
.chipset_name = "Apollo Pro KT266",
.chipset_name = "Apollo Pro KT266/KT333",
},
/* VT8633 (for CuMine/ Celeron) */
{
.device_id = PCI_DEVICE_ID_VIA_8653_0,
.chipset = VIA_APOLLO_PRO,
.chipset_name = "Apollo Pro 266T",
},
/* KM266 / PM266 */
/* {
.device_id = PCI_DEVICE_ID_VIA_KM266, // 0x3116
.chipset_name = "KM266/PM266",
}, */
/* CLE266 */
/* {
.device_id = PCI_DEVICE_ID_VIA_CLE266, // 0x3123
.chipset_name = "CLE266",
}, */
{
.device_id = PCI_DEVICE_ID_VIA_8377_0,
.chipset = VIA_APOLLO_KT400,
.chipset_name = "Apollo Pro KT400",
.chipset_setup = via_kt400_setup,
},
/* VT8604 / VT8605 / VT8603 / TwisterT
* (Apollo Pro133A chipset with S3 Savage4) */
{
/* VIA ProSavage PM133 (Apollo Pro133A chipset with S3 Savage4) */
.device_id = PCI_DEVICE_ID_VIA_82C694X_0,
.chipset = VIA_VT8605,
.chipset_name = "Apollo ProSavage PM133"
.chipset_name = "Apollo ProSavage PM133/PL133/PN133/Twister"
},
/* VT8752*/
/* {
.device_id = PCI_DEVICE_ID_VIA_8752, // 0x3148
.chipset_name = "ProSavage DDR P4M266",
}, */
/* KN266/PN266 */
/* {
.device_id = PCI_DEVICE_ID_KN266, // 0x3156
.chipset_name = "KN266/PN266",
}, */
/* VT8754 */
{
.device_id = PCI_DEVICE_ID_VIA_8754,
.chipset = VIA_P4X,
.chipset_name = "Apollo P4X333/P4X400"
},
/* P4N333 */
/* {
.device_id = PCI_DEVICE_ID_VIA_P4N333, // 0x3178
.chipset_name = "P4N333",
}, */
/* P4X600 */
/* {
.device_id = PCI_DEVICE_ID_VIA_P4X600, // 0x0198
.chipset_name = "P4X600",
}, */
/* KM400 */
/* {
.device_id = PCI_DEVICE_ID_VIA_KM400, // 0x3205
.chipset_name = "KM400",
}, */
/* P4M400 */
/* {
.device_id = PCI_DEVICE_ID_VIA_P4M400, // 0x3209
.chipset_name = "PM400",
}, */
{ }, /* dummy final entry, always present */
};
......@@ -221,7 +430,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
while (devs[j].chipset_name != NULL) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
agp_bridge.type = devs[j].chipset;
agp_bridge->type = VIA_GENERIC;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
......@@ -235,7 +444,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic VIA routines"
" for device id: %04x\n", pdev->device);
agp_bridge.type = VIA_GENERIC;
agp_bridge->type = VIA_GENERIC;
return via_generic_setup(pdev);
}
......@@ -244,10 +453,12 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
return -ENODEV;
}
static struct agp_driver via_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
u8 cap_ptr = 0;
......@@ -258,10 +469,10 @@ static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id
/* probe for known chipsets */
if (agp_lookup_host_bridge (dev) != -ENODEV) {
agp_bridge.dev = dev;
agp_bridge.capndx = cap_ptr;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
via_agp_driver.dev = dev;
agp_register_driver(&via_agp_driver);
return 0;
......@@ -269,6 +480,7 @@ static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id
return -ENODEV;
}
static struct pci_device_id agp_via_pci_table[] __initdata = {
{
.class = (PCI_CLASS_BRIDGE_HOST << 8),
......@@ -283,31 +495,36 @@ static struct pci_device_id agp_via_pci_table[] __initdata = {
MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
static struct __initdata pci_driver agp_via_pci_driver = {
.name = "agpgart-via",
.id_table = agp_via_pci_table,
.probe = agp_via_probe,
};
static int __init agp_via_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_via_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
static void __exit agp_via_cleanup(void)
{
agp_unregister_driver(&via_agp_driver);
pci_unregister_driver(&agp_via_pci_driver);
}
module_init(agp_via_init);
module_exit(agp_via_cleanup);
MODULE_PARM(agp_try_unsupported, "1i");
MODULE_LICENSE("GPL and additional rights");
MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
drivers/char/agp/via-kt400.c deleted 100644 → 0
View file @ f2478c00
/*
* VIA KT400 AGPGART routines.
*
* The KT400 does magick to put the AGP bridge compliant with the same
* standards version as the graphics card. If we haven't fallen into
* 2.0 compatability mode, we run this code. Otherwise, we run the
* code in via-agp.c
*/
#include <linux/types.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"
static int via_fetch_size(void)
{
int i;
u8 temp;
struct aper_size_info_16 *values;
values = A_SIZE_16(agp_bridge.aperture_sizes);
pci_read_config_byte(agp_bridge.dev, VIA_AGP3_APSIZE, &temp);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
return values[i].size;
}
}
return 0;
}
static int via_configure(void)
{
u32 temp;
struct aper_size_info_16 *current_size;
current_size = A_SIZE_16(agp_bridge.current_size);
/* address to map too */
pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture GATT base */
pci_write_config_dword(agp_bridge.dev, VIA_AGP3_ATTBASE,
agp_bridge.gatt_bus_addr & 0xfffff000);
return 0;
}
static void via_cleanup(void)
{
struct aper_size_info_16 *previous_size;
previous_size = A_SIZE_16(agp_bridge.previous_size);
pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, previous_size->size_value);
}
static void via_tlbflush(agp_memory * mem)
{
u32 temp;
pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp);
pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp);
}
static unsigned long via_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
}
static struct aper_size_info_16 via_generic_sizes[11] =
{
{ 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 },
{ 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1},
{ 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2},
{ 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3},
{ 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4},
{ 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5},
{ 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8},
{ 512, 131072, 7, 1<<11|1<<10|1<<9},
{ 1024, 262144, 8, 1<<11|1<<10},
{ 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */
};
static struct gatt_mask via_generic_masks[] =
{
{.mask = 0x00000000, .type = 0}
};
static void __init via_kt400_enable(u32 mode)
{
if ((agp_generic_agp_3_0_enable(mode))==FALSE)
printk (KERN_INFO PFX "agp_generic_agp_3_0_enable() failed\n");
}
static struct agp_driver via_kt400_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
u8 reg;
u8 cap_ptr = 0;
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
pci_read_config_byte(dev, VIA_AGPSEL, &reg);
/* Check if we are in AGP 2.0 compatability mode, if so it
* will be picked up by via-agp.o */
if ((reg & (1<<1))==1)
return -ENODEV;
printk (KERN_INFO PFX "Detected VIA KT400 AGP3 chipset\n");
agp_bridge.dev = dev;
agp_bridge.type = VIA_APOLLO_KT400_3;
agp_bridge.capndx = cap_ptr;
agp_bridge.masks = via_generic_masks;
agp_bridge.aperture_sizes = (void *) via_generic_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.agp_enable = via_kt400_enable;
agp_bridge.configure = via_configure;
agp_bridge.fetch_size = via_fetch_size;
agp_bridge.cleanup = via_cleanup;
agp_bridge.tlb_flush = via_tlbflush;
agp_bridge.mask_memory = via_mask_memory;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
via_kt400_agp_driver.dev = dev;
agp_register_driver(&via_kt400_agp_driver);
return 0;
}
static struct pci_device_id agp_via_pci_table[] __initdata = {
{
.class = (PCI_CLASS_BRIDGE_HOST << 8),
.class_mask = ~0,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8377_0,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{ }
};
MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
static struct __initdata pci_driver agp_via_pci_driver = {
.name = "agpgart-via",
.id_table = agp_via_pci_table,
.probe = agp_via_probe,
};
static int __init agp_via_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_via_pci_driver);
if (ret_val)
agp_bridge.type = NOT_SUPPORTED;
return ret_val;
}
static void __exit agp_via_cleanup(void)
{
agp_unregister_driver(&via_kt400_agp_driver);
pci_unregister_driver(&agp_via_pci_driver);
}
module_init(agp_via_init);
module_exit(agp_via_cleanup);
MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
MODULE_LICENSE("GPL and additional rights");
include/linux/agp_backend.h
View file @ 3d9d6859
......@@ -53,17 +53,6 @@ enum chipset_type {
INTEL_460GX,
INTEL_I7505,
VIA_GENERIC,
VIA_VP3,
VIA_MVP3,
VIA_MVP4,
VIA_APOLLO_PRO,
VIA_APOLLO_KX133,
VIA_APOLLO_KT133,
VIA_APOLLO_KT400,
VIA_APOLLO_KT400_3,
VIA_APOLLO_PRO_266,
VIA_VT8605,
VIA_P4X,
SIS_GENERIC,
AMD_GENERIC,
AMD_IRONGATE,
......@@ -84,6 +73,7 @@ enum chipset_type {
SVWRKS_LE,
SVWRKS_GENERIC,
HP_ZX1,
ALPHA_CORE_AGP,
};
struct agp_version {
......@@ -102,6 +92,7 @@ typedef struct _agp_kern_info {
int current_memory;
int cant_use_aperture;
unsigned long page_mask;
struct vm_operations_struct *vm_ops;
} agp_kern_info;
/*
......
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