Commit 40fc95d5 authored by Winkler, Tomas's avatar Winkler, Tomas Committed by John W. Linville

iwlwifi: TX update chicken bits

This instructs FH to increment the retry count of a packet when
it is brought from the memory to TX-FIFO to save transactions
during aggregation flow.
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 31a73fe4
...@@ -695,6 +695,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv) ...@@ -695,6 +695,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
unsigned long flags; unsigned long flags;
int ret; int ret;
int i, chan; int i, chan;
u32 reg_val;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
...@@ -724,6 +725,11 @@ static int iwl4965_alive_notify(struct iwl_priv *priv) ...@@ -724,6 +725,11 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
/* Update FH chicken bits */
reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
/* Disable chain mode for all queues */ /* Disable chain mode for all queues */
iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0); iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
......
...@@ -703,6 +703,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv) ...@@ -703,6 +703,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
unsigned long flags; unsigned long flags;
int ret; int ret;
int i, chan; int i, chan;
u32 reg_val;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
...@@ -732,6 +733,11 @@ static int iwl5000_alive_notify(struct iwl_priv *priv) ...@@ -732,6 +733,11 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
/* Update FH chicken bits */
reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
......
...@@ -396,6 +396,11 @@ ...@@ -396,6 +396,11 @@
#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
(FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
/* Instruct FH to increment the retry count of a packet when
* it is brought from the memory to TX-FIFO
*/
#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
/** /**
* struct iwl_rb_status - reseve buffer status * struct iwl_rb_status - reseve buffer status
......
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