Commit 422dcafe authored by Charles Keepax's avatar Charles Keepax Committed by Lee Jones

mfd: lochnagar: Add support for the Cirrus Logic Lochnagar

Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the board
controller chip on the Lochnagar board. Audio system topology,
clocking and power can all be controlled through the Lochnagar
controller chip, allowing the device under test to be used in
a variety of possible use cases.

As the Lochnagar is a fairly complex device this MFD driver
allows the drivers for the various features to be bound
in. Initially clocking, regulator and pinctrl will be added as
these are necessary to configure the system. But in time at least
audio and voltage/current monitoring will also be added.
Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
parent fdc98f07
...@@ -3700,6 +3700,23 @@ L: netdev@vger.kernel.org ...@@ -3700,6 +3700,23 @@ L: netdev@vger.kernel.org
S: Maintained S: Maintained
F: drivers/net/ethernet/cirrus/ep93xx_eth.c F: drivers/net/ethernet/cirrus/ep93xx_eth.c
CIRRUS LOGIC LOCHNAGAR DRIVER
M: Charles Keepax <ckeepax@opensource.cirrus.com>
M: Richard Fitzgerald <rf@opensource.cirrus.com>
L: patches@opensource.cirrus.com
S: Supported
F: drivers/clk/clk-lochnagar.c
F: drivers/mfd/lochnagar-i2c.c
F: drivers/pinctrl/cirrus/pinctrl-lochnagar.c
F: drivers/regulator/lochnagar-regulator.c
F: include/dt-bindings/clk/lochnagar.h
F: include/dt-bindings/pinctrl/lochnagar.h
F: include/linux/mfd/lochnagar*
F: Documentation/devicetree/bindings/mfd/cirrus,lochnagar.txt
F: Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt
F: Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt
F: Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt
CISCO FCOE HBA DRIVER CISCO FCOE HBA DRIVER
M: Satish Kharat <satishkh@cisco.com> M: Satish Kharat <satishkh@cisco.com>
M: Sesidhar Baddela <sebaddel@cisco.com> M: Sesidhar Baddela <sebaddel@cisco.com>
......
...@@ -1686,6 +1686,14 @@ config MFD_VX855 ...@@ -1686,6 +1686,14 @@ config MFD_VX855
VIA VX855/VX875 south bridge. You will need to enable the vx855_spi VIA VX855/VX875 south bridge. You will need to enable the vx855_spi
and/or vx855_gpio drivers for this to do anything useful. and/or vx855_gpio drivers for this to do anything useful.
config MFD_LOCHNAGAR
bool "Cirrus Logic Lochnagar Audio Development Board"
select MFD_CORE
select REGMAP_I2C
depends on I2C=y && OF
help
Support for Cirrus Logic Lochnagar audio development board.
config MFD_ARIZONA config MFD_ARIZONA
select REGMAP select REGMAP
select REGMAP_IRQ select REGMAP_IRQ
......
...@@ -37,6 +37,8 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o ...@@ -37,6 +37,8 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o
obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o
obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o
obj-$(CONFIG_MFD_LOCHNAGAR) += lochnagar-i2c.o
obj-$(CONFIG_MFD_ARIZONA) += arizona-core.o obj-$(CONFIG_MFD_ARIZONA) += arizona-core.o
obj-$(CONFIG_MFD_ARIZONA) += arizona-irq.o obj-$(CONFIG_MFD_ARIZONA) += arizona-irq.o
obj-$(CONFIG_MFD_ARIZONA_I2C) += arizona-i2c.o obj-$(CONFIG_MFD_ARIZONA_I2C) += arizona-i2c.o
......
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Lochnagar internals
*
* Copyright (c) 2013-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
*/
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#ifndef CIRRUS_LOCHNAGAR_H
#define CIRRUS_LOCHNAGAR_H
enum lochnagar_type {
LOCHNAGAR1,
LOCHNAGAR2,
};
/**
* struct lochnagar - Core data for the Lochnagar audio board driver.
*
* @type: The type of Lochnagar device connected.
* @dev: A pointer to the struct device for the main MFD.
* @regmap: The devices main register map.
* @analogue_config_lock: Lock used to protect updates in the analogue
* configuration as these must not be changed whilst the hardware is processing
* the last update.
*/
struct lochnagar {
enum lochnagar_type type;
struct device *dev;
struct regmap *regmap;
/* Lock to protect updates to the analogue configuration */
struct mutex analogue_config_lock;
};
/* Register Addresses */
#define LOCHNAGAR_SOFTWARE_RESET 0x00
#define LOCHNAGAR_FIRMWARE_ID1 0x01
#define LOCHNAGAR_FIRMWARE_ID2 0x02
/* (0x0000) Software Reset */
#define LOCHNAGAR_DEVICE_ID_MASK 0xFFFC
#define LOCHNAGAR_DEVICE_ID_SHIFT 2
#define LOCHNAGAR_REV_ID_MASK 0x0003
#define LOCHNAGAR_REV_ID_SHIFT 0
int lochnagar_update_config(struct lochnagar *lochnagar);
#endif
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Lochnagar1 register definitions
*
* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
*/
#ifndef LOCHNAGAR1_REGISTERS_H
#define LOCHNAGAR1_REGISTERS_H
/* Register Addresses */
#define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
#define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
#define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
#define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
#define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
#define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
#define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
#define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
#define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
#define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
#define LOCHNAGAR1_DSP_CLKIN_SEL 0x0012
#define LOCHNAGAR1_DSP_AIF 0x0013
#define LOCHNAGAR1_GF_AIF1 0x0014
#define LOCHNAGAR1_GF_AIF2 0x0015
#define LOCHNAGAR1_PSIA_AIF 0x0016
#define LOCHNAGAR1_PSIA1_SEL 0x0017
#define LOCHNAGAR1_PSIA2_SEL 0x0018
#define LOCHNAGAR1_SPDIF_AIF_SEL 0x0019
#define LOCHNAGAR1_GF_AIF3_SEL 0x001C
#define LOCHNAGAR1_GF_AIF4_SEL 0x001D
#define LOCHNAGAR1_GF_CLKOUT1_SEL 0x001E
#define LOCHNAGAR1_GF_AIF1_SEL 0x001F
#define LOCHNAGAR1_GF_AIF2_SEL 0x0020
#define LOCHNAGAR1_GF_GPIO2 0x0026
#define LOCHNAGAR1_GF_GPIO3 0x0027
#define LOCHNAGAR1_GF_GPIO7 0x0028
#define LOCHNAGAR1_RST 0x0029
#define LOCHNAGAR1_LED1 0x002A
#define LOCHNAGAR1_LED2 0x002B
#define LOCHNAGAR1_I2C_CTRL 0x0046
/*
* (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020)
* CDC_AIF1_SEL - GF_AIF2_SEL
*/
#define LOCHNAGAR1_SRC_MASK 0xFF
#define LOCHNAGAR1_SRC_SHIFT 0
/* (0x000D) CDC_AIF_CTRL1 */
#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_CDC_AIF2_ENA_MASK 0x10
#define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT 4
#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_CDC_AIF1_ENA_MASK 0x01
#define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT 0
/* (0x000E) CDC_AIF_CTRL2 */
#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_CDC_AIF3_ENA_MASK 0x10
#define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT 4
#define LOCHNAGAR1_CDC_MCLK1_ENA_MASK 0x02
#define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT 1
#define LOCHNAGAR1_CDC_MCLK2_ENA_MASK 0x01
#define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT 0
/* (0x000F) EXT_AIF_CTRL */
#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK 0x20
#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT 5
#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK 0x10
#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT 4
#define LOCHNAGAR1_SPDIF_AIF_ENA_MASK 0x08
#define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT 3
/* (0x0013) DSP_AIF */
#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_DSP_AIF2_ENA_MASK 0x10
#define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT 4
#define LOCHNAGAR1_DSP_CLKIN_ENA_MASK 0x08
#define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT 3
#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_DSP_AIF1_ENA_MASK 0x01
#define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT 0
/* (0x0014) GF_AIF1 */
#define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK 0x40
#define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT 6
#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK 0x20
#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT 5
#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK 0x10
#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT 4
#define LOCHNAGAR1_GF_AIF3_ENA_MASK 0x08
#define LOCHNAGAR1_GF_AIF3_ENA_SHIFT 3
#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_GF_AIF1_ENA_MASK 0x01
#define LOCHNAGAR1_GF_AIF1_ENA_SHIFT 0
/* (0x0015) GF_AIF2 */
#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK 0x20
#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT 5
#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK 0x10
#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT 4
#define LOCHNAGAR1_GF_AIF4_ENA_MASK 0x08
#define LOCHNAGAR1_GF_AIF4_ENA_SHIFT 3
#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_GF_AIF2_ENA_MASK 0x01
#define LOCHNAGAR1_GF_AIF2_ENA_SHIFT 0
/* (0x0016) PSIA_AIF */
#define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK 0x40
#define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT 6
#define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK 0x20
#define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT 5
#define LOCHNAGAR1_PSIA2_ENA_MASK 0x10
#define LOCHNAGAR1_PSIA2_ENA_SHIFT 4
#define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK 0x04
#define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT 2
#define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK 0x02
#define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT 1
#define LOCHNAGAR1_PSIA1_ENA_MASK 0x01
#define LOCHNAGAR1_PSIA1_ENA_SHIFT 0
/* (0x0029) RST */
#define LOCHNAGAR1_DSP_RESET_MASK 0x02
#define LOCHNAGAR1_DSP_RESET_SHIFT 1
#define LOCHNAGAR1_CDC_RESET_MASK 0x01
#define LOCHNAGAR1_CDC_RESET_SHIFT 0
/* (0x0046) I2C_CTRL */
#define LOCHNAGAR1_CDC_CIF_MODE_MASK 0x01
#define LOCHNAGAR1_CDC_CIF_MODE_SHIFT 0
#endif
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