Commit 44f73dc4 authored by Antoine Tenart's avatar Antoine Tenart Committed by Gregory CLEMENT

arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes

The cryptographic engine nodes have an interrupt which is configured as
both edge and level, which makes no sense at all. Fix this by
configuring it the right way (level).
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 08332893
...@@ -231,8 +231,7 @@ cpm_sdhci0: sdhci@780000 { ...@@ -231,8 +231,7 @@ cpm_sdhci0: sdhci@780000 {
cpm_crypto: crypto@800000 { cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197"; compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>; reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
| IRQ_TYPE_LEVEL_HIGH)>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
......
...@@ -221,8 +221,7 @@ cps_trng: trng@760000 { ...@@ -221,8 +221,7 @@ cps_trng: trng@760000 {
cps_crypto: crypto@800000 { cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197"; compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>; reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
| IRQ_TYPE_LEVEL_HIGH)>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
......
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