Commit 4898dc48 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher

drm/amd/display: Add DCN3 MMHUBHUB

Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent db7b0216
...@@ -848,6 +848,42 @@ enum dwb_stereo_type { ...@@ -848,6 +848,42 @@ enum dwb_stereo_type {
DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */
}; };
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
enum dwb_out_format {
DWB_OUT_FORMAT_32BPP_ARGB = 0,
DWB_OUT_FORMAT_32BPP_RGBA = 1,
DWB_OUT_FORMAT_64BPP_ARGB = 2,
DWB_OUT_FORMAT_64BPP_RGBA = 3
};
enum dwb_out_denorm {
DWB_OUT_DENORM_10BPC = 0,
DWB_OUT_DENORM_8BPC = 1,
DWB_OUT_DENORM_BYPASS = 2
};
enum cm_gamut_remap_select {
CM_GAMUT_REMAP_MODE_BYPASS = 0,
CM_GAMUT_REMAP_MODE_RAMA_COEFF,
CM_GAMUT_REMAP_MODE_RAMB_COEFF,
CM_GAMUT_REMAP_MODE_RESERVED
};
enum cm_gamut_coef_format {
CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0,
CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
};
struct mcif_warmup_params {
union large_integer start_address;
unsigned int address_increment;
unsigned int region_size;
unsigned int p_vmid;
};
#endif
#define MCIF_BUF_COUNT 4 #define MCIF_BUF_COUNT 4
struct mcif_buf_params { struct mcif_buf_params {
......
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...@@ -43,6 +43,9 @@ struct mcif_arb_params { ...@@ -43,6 +43,9 @@ struct mcif_arb_params {
unsigned int arbitration_slice; unsigned int arbitration_slice;
unsigned int slice_lines; unsigned int slice_lines;
unsigned int max_scaled_time; unsigned int max_scaled_time;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
unsigned int dram_speed_change_duration;
#endif
}; };
struct mcif_irq_params { struct mcif_irq_params {
......
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