Commit 48d378a4 authored by Linus Torvalds's avatar Linus Torvalds

Merge http://suncobalt.bkbits.net/nvram-2.5

into penguin.transmeta.com:/home/penguin/torvalds/repositories/kernel/linux
parents 0235b42a ab504df8
...@@ -985,9 +985,10 @@ CONFIG_H8 ...@@ -985,9 +985,10 @@ CONFIG_H8
CONFIG_NVRAM CONFIG_NVRAM
If you say Y here and create a character special file /dev/nvram If you say Y here and create a character special file /dev/nvram
with major number 10 and minor number 144 using mknod ("man mknod"), with major number 10 and minor number 144 using mknod ("man mknod"),
you get read and write access to the 50 bytes of non-volatile memory you get read and write access to the extra bytes of non-volatile
in the real time clock (RTC), which is contained in every PC and memory in the real time clock (RTC), which is contained in every PC
most Ataris. and most Ataris. The actual number of bytes varies, depending on the
nvram in the system, but is usually 114 (128-14 for the RTC).
This memory is conventionally called "CMOS RAM" on PCs and "NVRAM" This memory is conventionally called "CMOS RAM" on PCs and "NVRAM"
on Ataris. /dev/nvram may be used to view settings there, or to on Ataris. /dev/nvram may be used to view settings there, or to
......
...@@ -15,7 +15,7 @@ obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o pty.o misc.o random.o ...@@ -15,7 +15,7 @@ obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o pty.o misc.o random.o
export-objs := busmouse.o console.o keyboard.o sysrq.o \ export-objs := busmouse.o console.o keyboard.o sysrq.o \
misc.o pty.o random.o selection.o \ misc.o pty.o random.o selection.o \
sonypi.o tty_io.o tty_ioctl.o generic_serial.o rtc.o \ sonypi.o tty_io.o tty_ioctl.o generic_serial.o rtc.o \
ip2main.o ip2main.o nvram.o
obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o selection.o keyboard.o obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o selection.o keyboard.o
obj-$(CONFIG_HW_CONSOLE) += console.o defkeymap.o obj-$(CONFIG_HW_CONSOLE) += console.o defkeymap.o
......
This diff is collapsed.
/*
* $Id: cobalt-nvram.h,v 1.20 2001/10/17 23:16:55 thockin Exp $
* cobalt-nvram.h : defines for the various fields in the cobalt NVRAM
*
* Copyright 2001,2002 Sun Microsystems, Inc.
*/
#ifndef COBALT_NVRAM_H
#define COBALT_NVRAM_H
#include <linux/nvram.h>
#define COBT_CMOS_INFO_MAX 0x7f /* top address allowed */
#define COBT_CMOS_BIOS_DRIVE_INFO 0x12 /* drive info would go here */
#define COBT_CMOS_CKS_START NVRAM_OFFSET(0x0e)
#define COBT_CMOS_CKS_END NVRAM_OFFSET(0x7f)
/* flag bytes - 16 flags for now, leave room for more */
#define COBT_CMOS_FLAG_BYTE_0 NVRAM_OFFSET(0x10)
#define COBT_CMOS_FLAG_BYTE_1 NVRAM_OFFSET(0x11)
/* flags in flag bytes - up to 16 */
#define COBT_CMOS_FLAG_MIN 0x0001
#define COBT_CMOS_CONSOLE_FLAG 0x0001 /* console on/off */
#define COBT_CMOS_DEBUG_FLAG 0x0002 /* ROM debug messages */
#define COBT_CMOS_AUTO_PROMPT_FLAG 0x0004 /* boot to ROM prompt? */
#define COBT_CMOS_CLEAN_BOOT_FLAG 0x0008 /* set by a clean shutdown */
#define COBT_CMOS_HW_NOPROBE_FLAG 0x0010 /* go easy on the probing */
#define COBT_CMOS_SYSFAULT_FLAG 0x0020 /* system fault detected */
#define COBT_CMOS_OOPSPANIC_FLAG 0x0040 /* panic on oops */
#define COBT_CMOS_DELAY_CACHE_FLAG 0x0080 /* delay cache initialization */
#define COBT_CMOS_NOLOGO_FLAG 0x0100 /* hide "C" logo @ boot */
#define COBT_CMOS_VERSION_FLAG 0x0200 /* the version field is valid */
#define COBT_CMOS_FLAG_MAX 0x0200
/* leave byte 0x12 blank - Linux looks for drive info here */
/* CMOS structure version, valid if COBT_CMOS_VERSION_FLAG is true */
#define COBT_CMOS_VERSION NVRAM_OFFSET(0x13)
#define COBT_CMOS_VER_BTOCODE 1 /* min. version needed for btocode */
/* index of default boot method */
#define COBT_CMOS_BOOT_METHOD NVRAM_OFFSET(0x20)
#define COBT_CMOS_BOOT_METHOD_DISK 0
#define COBT_CMOS_BOOT_METHOD_ROM 1
#define COBT_CMOS_BOOT_METHOD_NET 2
#define COBT_CMOS_BOOT_DEV_MIN NVRAM_OFFSET(0x21)
/* major #, minor # of first through fourth boot device */
#define COBT_CMOS_BOOT_DEV0_MAJ NVRAM_OFFSET(0x21)
#define COBT_CMOS_BOOT_DEV0_MIN NVRAM_OFFSET(0x22)
#define COBT_CMOS_BOOT_DEV1_MAJ NVRAM_OFFSET(0x23)
#define COBT_CMOS_BOOT_DEV1_MIN NVRAM_OFFSET(0x24)
#define COBT_CMOS_BOOT_DEV2_MAJ NVRAM_OFFSET(0x25)
#define COBT_CMOS_BOOT_DEV2_MIN NVRAM_OFFSET(0x26)
#define COBT_CMOS_BOOT_DEV3_MAJ NVRAM_OFFSET(0x27)
#define COBT_CMOS_BOOT_DEV3_MIN NVRAM_OFFSET(0x28)
#define COBT_CMOS_BOOT_DEV_MAX NVRAM_OFFSET(0x28)
/* checksum of bytes 0xe-0x7f */
#define COBT_CMOS_CHECKSUM NVRAM_OFFSET(0x2e)
/* running uptime counter, units of 5 minutes (32 bits =~ 41000 years) */
#define COBT_CMOS_UPTIME_0 NVRAM_OFFSET(0x30)
#define COBT_CMOS_UPTIME_1 NVRAM_OFFSET(0x31)
#define COBT_CMOS_UPTIME_2 NVRAM_OFFSET(0x32)
#define COBT_CMOS_UPTIME_3 NVRAM_OFFSET(0x33)
/* count of successful boots (32 bits) */
#define COBT_CMOS_BOOTCOUNT_0 NVRAM_OFFSET(0x38)
#define COBT_CMOS_BOOTCOUNT_1 NVRAM_OFFSET(0x39)
#define COBT_CMOS_BOOTCOUNT_2 NVRAM_OFFSET(0x3a)
#define COBT_CMOS_BOOTCOUNT_3 NVRAM_OFFSET(0x3b)
/* 13 bytes: system serial number, same as on the back of the system */
#define COBT_CMOS_SYS_SERNUM_LEN 13
#define COBT_CMOS_SYS_SERNUM_0 NVRAM_OFFSET(0x40)
#define COBT_CMOS_SYS_SERNUM_1 NVRAM_OFFSET(0x41)
#define COBT_CMOS_SYS_SERNUM_2 NVRAM_OFFSET(0x42)
#define COBT_CMOS_SYS_SERNUM_3 NVRAM_OFFSET(0x43)
#define COBT_CMOS_SYS_SERNUM_4 NVRAM_OFFSET(0x44)
#define COBT_CMOS_SYS_SERNUM_5 NVRAM_OFFSET(0x45)
#define COBT_CMOS_SYS_SERNUM_6 NVRAM_OFFSET(0x46)
#define COBT_CMOS_SYS_SERNUM_7 NVRAM_OFFSET(0x47)
#define COBT_CMOS_SYS_SERNUM_8 NVRAM_OFFSET(0x48)
#define COBT_CMOS_SYS_SERNUM_9 NVRAM_OFFSET(0x49)
#define COBT_CMOS_SYS_SERNUM_10 NVRAM_OFFSET(0x4a)
#define COBT_CMOS_SYS_SERNUM_11 NVRAM_OFFSET(0x4b)
#define COBT_CMOS_SYS_SERNUM_12 NVRAM_OFFSET(0x4c)
/* checksum for serial num - 1 byte */
#define COBT_CMOS_SYS_SERNUM_CSUM NVRAM_OFFSET(0x4f)
#define COBT_CMOS_ROM_REV_MAJ NVRAM_OFFSET(0x50)
#define COBT_CMOS_ROM_REV_MIN NVRAM_OFFSET(0x51)
#define COBT_CMOS_ROM_REV_REV NVRAM_OFFSET(0x52)
#define COBT_CMOS_BTO_CODE_0 NVRAM_OFFSET(0x53)
#define COBT_CMOS_BTO_CODE_1 NVRAM_OFFSET(0x54)
#define COBT_CMOS_BTO_CODE_2 NVRAM_OFFSET(0x55)
#define COBT_CMOS_BTO_CODE_3 NVRAM_OFFSET(0x56)
#define COBT_CMOS_BTO_IP_CSUM NVRAM_OFFSET(0x57)
#define COBT_CMOS_BTO_IP_0 NVRAM_OFFSET(0x58)
#define COBT_CMOS_BTO_IP_1 NVRAM_OFFSET(0x59)
#define COBT_CMOS_BTO_IP_2 NVRAM_OFFSET(0x5a)
#define COBT_CMOS_BTO_IP_3 NVRAM_OFFSET(0x5b)
#endif /* COBALT_NVRAM_H */
...@@ -7,11 +7,21 @@ ...@@ -7,11 +7,21 @@
#define NVRAM_INIT _IO('p', 0x40) /* initialize NVRAM and set checksum */ #define NVRAM_INIT _IO('p', 0x40) /* initialize NVRAM and set checksum */
#define NVRAM_SETCKS _IO('p', 0x41) /* recalculate checksum */ #define NVRAM_SETCKS _IO('p', 0x41) /* recalculate checksum */
/* for all current systems, this is where NVRAM starts */
#define NVRAM_FIRST_BYTE 14
/* all these functions expect an NVRAM offset, not an absolute */
#define NVRAM_OFFSET(x) ((x)-NVRAM_FIRST_BYTE)
#ifdef __KERNEL__ #ifdef __KERNEL__
extern unsigned char nvram_read_byte( int i ); /* __foo is foo without grabbing the rtc_lock - get it yourself */
extern void nvram_write_byte( unsigned char c, int i ); extern unsigned char __nvram_read_byte(int i);
extern int nvram_check_checksum( void ); extern unsigned char nvram_read_byte(int i);
extern void nvram_set_checksum( void ); extern void __nvram_write_byte(unsigned char c, int i);
extern void nvram_write_byte(unsigned char c, int i);
extern int __nvram_check_checksum(void);
extern int nvram_check_checksum(void);
extern void __nvram_set_checksum(void);
extern void nvram_set_checksum(void);
#endif #endif
#endif /* _LINUX_NVRAM_H */ #endif /* _LINUX_NVRAM_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment