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Commit 49006bfd authored by Vaibhav Hiremath's avatar Vaibhav Hiremath Committed by Tony Lindgren
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ARM: AM33XX: hwmod data: irq, dma and addr info clean up 

AM33XX only supports DT boot mode and with addition of
extracting module resources like, irq, dma and address space
from DT block, so now we can remove duplicate information from
hwmod data file.

This patch cleanups-up/deletes,

     - All references to "omap_hwmod_irq_info" data.
     - All references to "omap_hwmod_dma_info" data.
     - References to "omap_hwmod_addr_space" of the modules
       for which DT node is available with required address
       space information.
     - For the modules where "sysc" field is not applicable,
       we don't need module address space, so remove them as well.
     - The hwmod like firewall etc which are not useful are also
       deleted.

This cleanup gets us around ~1100 LOC of negative diff.
Patch is boot tested on AM335x-EVM along with below modules -
	- Matrix-keypad
	- Volume up/down keys
	- Ethernet
	- RTC
	- WDT
Signed-off-by: default avatarVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: default avatarSricharan R <r.sricharan@ti.com>
Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent d683b96b
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arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file @ 49006bfd
...@@ -34,29 +34,6 @@ ...@@ -34,29 +34,6 @@
* IP blocks * IP blocks
*/ */
/*
* 'emif_fw' class
* instance(s): emif_fw
*/
static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
.name = "emif_fw",
};
/* emif_fw */
static struct omap_hwmod am33xx_emif_fw_hwmod = {
.name = "emif_fw",
.class = &am33xx_emif_fw_hwmod_class,
.clkdm_name = "l4fw_clkdm",
.main_clk = "l4fw_gclk",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* /*
* 'emif' class * 'emif' class
* instance(s): emif * instance(s): emif
...@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = { ...@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
.sysc = &am33xx_emif_sysc, .sysc = &am33xx_emif_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
{ .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* emif */ /* emif */
static struct omap_hwmod am33xx_emif_hwmod = { static struct omap_hwmod am33xx_emif_hwmod = {
.name = "emif", .name = "emif",
.class = &am33xx_emif_hwmod_class, .class = &am33xx_emif_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_emif_irqs,
.main_clk = "dpll_ddr_m2_div2_ck", .main_clk = "dpll_ddr_m2_div2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = { ...@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
.name = "l3", .name = "l3",
}; };
/* l3_main (l3_fast) */
static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
{ .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
{ .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_l3_main_hwmod = { static struct omap_hwmod am33xx_l3_main_hwmod = {
.name = "l3_main", .name = "l3_main",
.class = &am33xx_l3_hwmod_class, .class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_l3_main_irqs,
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = { ...@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
}, },
}; };
/* l4_fw */
static struct omap_hwmod am33xx_l4_fw_hwmod = {
.name = "l4_fw",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l4fw_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* /*
* 'mpu' class * 'mpu' class
*/ */
...@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = { ...@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
.name = "mpu", .name = "mpu",
}; };
/* mpu */
static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
{ .name = "emuint", .irq = 0 + OMAP_INTC_START, },
{ .name = "commtx", .irq = 1 + OMAP_INTC_START, },
{ .name = "commrx", .irq = 2 + OMAP_INTC_START, },
{ .name = "bench", .irq = 3 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_mpu_hwmod = { static struct omap_hwmod am33xx_mpu_hwmod = {
.name = "mpu", .name = "mpu",
.class = &am33xx_mpu_hwmod_class, .class = &am33xx_mpu_hwmod_class,
.clkdm_name = "mpu_clkdm", .clkdm_name = "mpu_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_mpu_irqs,
.main_clk = "dpll_mpu_m2_ck", .main_clk = "dpll_mpu_m2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { ...@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
}; };
static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
{ .name = "txev", .irq = 78 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* wkup_m3 */ /* wkup_m3 */
static struct omap_hwmod am33xx_wkup_m3_hwmod = { static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3", .name = "wkup_m3",
...@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { ...@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.clkdm_name = "l4_wkup_aon_clkdm", .clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */ /* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.mpu_irqs = am33xx_wkup_m3_irqs,
.main_clk = "dpll_core_m4_div2_ck", .main_clk = "dpll_core_m4_div2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { ...@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
{ .name = "pruss", .rst_shift = 1 }, { .name = "pruss", .rst_shift = 1 },
}; };
static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
{ .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
{ .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
{ .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
{ .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
{ .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
{ .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
{ .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
{ .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* pru-icss */ /* pru-icss */
/* Pseudo hwmod for reset control purpose only */ /* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod am33xx_pruss_hwmod = { static struct omap_hwmod am33xx_pruss_hwmod = {
.name = "pruss", .name = "pruss",
.class = &am33xx_pruss_hwmod_class, .class = &am33xx_pruss_hwmod_class,
.clkdm_name = "pruss_ocp_clkdm", .clkdm_name = "pruss_ocp_clkdm",
.mpu_irqs = am33xx_pruss_irqs,
.main_clk = "pruss_ocp_gclk", .main_clk = "pruss_ocp_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { ...@@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
{ .name = "gfx", .rst_shift = 0 }, { .name = "gfx", .rst_shift = 0 },
}; };
static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
{ .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_gfx_hwmod = { static struct omap_hwmod am33xx_gfx_hwmod = {
.name = "gfx", .name = "gfx",
.class = &am33xx_gfx_hwmod_class, .class = &am33xx_gfx_hwmod_class,
.clkdm_name = "gfx_l3_clkdm", .clkdm_name = "gfx_l3_clkdm",
.mpu_irqs = am33xx_gfx_irqs,
.main_clk = "gfx_fck_div_ck", .main_clk = "gfx_fck_div_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { ...@@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
.sysc = &am33xx_adc_tsc_sysc, .sysc = &am33xx_adc_tsc_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
{ .irq = 16 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_adc_tsc_hwmod = { static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc", .name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class, .class = &am33xx_adc_tsc_hwmod_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_adc_tsc_irqs,
.main_clk = "adc_tsc_fck", .main_clk = "adc_tsc_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = { ...@@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
.sysc = &am33xx_aes0_sysc, .sysc = &am33xx_aes0_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
{ .irq = 103 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
{ .name = "tx", .dma_req = 6, },
{ .name = "rx", .dma_req = 5, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_aes0_hwmod = { static struct omap_hwmod am33xx_aes0_hwmod = {
.name = "aes", .name = "aes",
.class = &am33xx_aes0_hwmod_class, .class = &am33xx_aes0_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_aes0_irqs,
.sdma_reqs = am33xx_aes0_edma_reqs,
.main_clk = "aes0_fck", .main_clk = "aes0_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = { ...@@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
.sysc = &am33xx_sha0_sysc, .sysc = &am33xx_sha0_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
{ .irq = 109 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
{ .name = "rx", .dma_req = 36, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_sha0_hwmod = { static struct omap_hwmod am33xx_sha0_hwmod = {
.name = "sham", .name = "sham",
.class = &am33xx_sha0_hwmod_class, .class = &am33xx_sha0_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_sha0_irqs,
.sdma_reqs = am33xx_sha0_edma_reqs,
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { ...@@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
}; };
/* smartreflex0 */ /* smartreflex0 */
static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
{ .irq = 120 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_smartreflex0_hwmod = { static struct omap_hwmod am33xx_smartreflex0_hwmod = {
.name = "smartreflex0", .name = "smartreflex0",
.class = &am33xx_smartreflex_hwmod_class, .class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_smartreflex0_irqs,
.main_clk = "smartreflex0_fck", .main_clk = "smartreflex0_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = { ...@@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
}; };
/* smartreflex1 */ /* smartreflex1 */
static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
{ .irq = 121 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_smartreflex1_hwmod = { static struct omap_hwmod am33xx_smartreflex1_hwmod = {
.name = "smartreflex1", .name = "smartreflex1",
.class = &am33xx_smartreflex_hwmod_class, .class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_smartreflex1_irqs,
.main_clk = "smartreflex1_fck", .main_clk = "smartreflex1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = { ...@@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
.name = "control", .name = "control",
}; };
static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
{ .irq = 8 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_control_hwmod = { static struct omap_hwmod am33xx_control_hwmod = {
.name = "control", .name = "control",
.class = &am33xx_control_hwmod_class, .class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_control_irqs,
.main_clk = "dpll_core_m4_div2_ck", .main_clk = "dpll_core_m4_div2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { ...@@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
.sysc = &am33xx_cpgmac_sysc, .sysc = &am33xx_cpgmac_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
{ .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
{ .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
{ .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
{ .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_cpgmac0_hwmod = { static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = "cpgmac0", .name = "cpgmac0",
.class = &am33xx_cpgmac0_hwmod_class, .class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm", .clkdm_name = "cpsw_125mhz_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.mpu_irqs = am33xx_cpgmac0_irqs,
.main_clk = "cpsw_125mhz_gclk", .main_clk = "cpsw_125mhz_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = { ...@@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
}; };
/* dcan0 */ /* dcan0 */
static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
{ .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
{ .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_dcan0_hwmod = { static struct omap_hwmod am33xx_dcan0_hwmod = {
.name = "d_can0", .name = "d_can0",
.class = &am33xx_dcan_hwmod_class, .class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_dcan0_irqs,
.main_clk = "dcan0_fck", .main_clk = "dcan0_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = { ...@@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
}; };
/* dcan1 */ /* dcan1 */
static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
{ .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
{ .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_dcan1_hwmod = { static struct omap_hwmod am33xx_dcan1_hwmod = {
.name = "d_can1", .name = "d_can1",
.class = &am33xx_dcan_hwmod_class, .class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_dcan1_irqs,
.main_clk = "dcan1_fck", .main_clk = "dcan1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = { ...@@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
.sysc = &am33xx_elm_sysc, .sysc = &am33xx_elm_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
{ .irq = 4 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_elm_hwmod = { static struct omap_hwmod am33xx_elm_hwmod = {
.name = "elm", .name = "elm",
.class = &am33xx_elm_hwmod_class, .class = &am33xx_elm_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_elm_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = { ...@@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
}; };
/* ecap0 */ /* ecap0 */
static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
{ .irq = 31 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ecap0_hwmod = { static struct omap_hwmod am33xx_ecap0_hwmod = {
.name = "ecap0", .name = "ecap0",
.class = &am33xx_ecap_hwmod_class, .class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap0_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
/* eqep0 */ /* eqep0 */
static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
{ .irq = 79 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep0_hwmod = { static struct omap_hwmod am33xx_eqep0_hwmod = {
.name = "eqep0", .name = "eqep0",
.class = &am33xx_eqep_hwmod_class, .class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep0_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
/* ehrpwm0 */ /* ehrpwm0 */
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
{ .name = "int", .irq = 86 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm0_hwmod = { static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0", .name = "ehrpwm0",
.class = &am33xx_ehrpwm_hwmod_class, .class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
...@@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = { ...@@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
}; };
/* ecap1 */ /* ecap1 */
static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
{ .irq = 47 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ecap1_hwmod = { static struct omap_hwmod am33xx_ecap1_hwmod = {
.name = "ecap1", .name = "ecap1",
.class = &am33xx_ecap_hwmod_class, .class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap1_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
/* eqep1 */ /* eqep1 */
static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
{ .irq = 88 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep1_hwmod = { static struct omap_hwmod am33xx_eqep1_hwmod = {
.name = "eqep1", .name = "eqep1",
.class = &am33xx_eqep_hwmod_class, .class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep1_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
/* ehrpwm1 */ /* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .name = "int", .irq = 87 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm1_hwmod = { static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1", .name = "ehrpwm1",
.class = &am33xx_ehrpwm_hwmod_class, .class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
...@@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = { ...@@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
}; };
/* ecap2 */ /* ecap2 */
static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
{ .irq = 61 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ecap2_hwmod = { static struct omap_hwmod am33xx_ecap2_hwmod = {
.name = "ecap2", .name = "ecap2",
.class = &am33xx_ecap_hwmod_class, .class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap2_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
/* eqep2 */ /* eqep2 */
static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
{ .irq = 89 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep2_hwmod = { static struct omap_hwmod am33xx_eqep2_hwmod = {
.name = "eqep2", .name = "eqep2",
.class = &am33xx_eqep_hwmod_class, .class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep2_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
/* ehrpwm2 */ /* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .name = "int", .irq = 39 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm2_hwmod = { static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2", .name = "ehrpwm2",
.class = &am33xx_ehrpwm_hwmod_class, .class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
}; };
...@@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { ...@@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio0_dbclk" }, { .role = "dbclk", .clk = "gpio0_dbclk" },
}; };
static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
{ .irq = 96 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_gpio0_hwmod = { static struct omap_hwmod am33xx_gpio0_hwmod = {
.name = "gpio1", .name = "gpio1",
.class = &am33xx_gpio_hwmod_class, .class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio0_irqs,
.main_clk = "dpll_core_m4_div2_ck", .main_clk = "dpll_core_m4_div2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = { ...@@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
}; };
/* gpio1 */ /* gpio1 */
static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
{ .irq = 98 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" }, { .role = "dbclk", .clk = "gpio1_dbclk" },
}; };
...@@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { ...@@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
.class = &am33xx_gpio_hwmod_class, .class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio1_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { ...@@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
}; };
/* gpio2 */ /* gpio2 */
static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
{ .irq = 32 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" }, { .role = "dbclk", .clk = "gpio2_dbclk" },
}; };
...@@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = { ...@@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
.class = &am33xx_gpio_hwmod_class, .class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio2_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = { ...@@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
}; };
/* gpio3 */ /* gpio3 */
static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
{ .irq = 62 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" }, { .role = "dbclk", .clk = "gpio3_dbclk" },
}; };
...@@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = { ...@@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
.class = &am33xx_gpio_hwmod_class, .class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio3_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { ...@@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
.sysc = &gpmc_sysc, .sysc = &gpmc_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
{ .irq = 100 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_gpmc_hwmod = { static struct omap_hwmod am33xx_gpmc_hwmod = {
.name = "gpmc", .name = "gpmc",
.class = &am33xx_gpmc_hwmod_class, .class = &am33xx_gpmc_hwmod_class,
.clkdm_name = "l3s_clkdm", .clkdm_name = "l3s_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_gpmc_irqs,
.main_clk = "l3s_gclk", .main_clk = "l3s_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { ...@@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
}; };
/* i2c1 */ /* i2c1 */
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
{ .irq = 70 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
{ .name = "tx", .dma_req = 0, },
{ .name = "rx", .dma_req = 0, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_i2c1_hwmod = { static struct omap_hwmod am33xx_i2c1_hwmod = {
.name = "i2c1", .name = "i2c1",
.class = &i2c_class, .class = &i2c_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = i2c1_mpu_irqs,
.sdma_reqs = i2c1_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_wkupdm_ck", .main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = { .prcm = {
...@@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = { ...@@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
}; };
/* i2c1 */ /* i2c1 */
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
{ .irq = 71 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
{ .name = "tx", .dma_req = 0, },
{ .name = "rx", .dma_req = 0, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_i2c2_hwmod = { static struct omap_hwmod am33xx_i2c2_hwmod = {
.name = "i2c2", .name = "i2c2",
.class = &i2c_class, .class = &i2c_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = i2c2_mpu_irqs,
.sdma_reqs = i2c2_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
...@@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = { ...@@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
}; };
/* i2c3 */ /* i2c3 */
static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
{ .name = "tx", .dma_req = 0, },
{ .name = "rx", .dma_req = 0, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
{ .irq = 30 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_i2c3_hwmod = { static struct omap_hwmod am33xx_i2c3_hwmod = {
.name = "i2c3", .name = "i2c3",
.class = &i2c_class, .class = &i2c_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = i2c3_mpu_irqs,
.sdma_reqs = i2c3_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
...@@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { ...@@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
.sysc = &lcdc_sysc, .sysc = &lcdc_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
{ .irq = 36 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_lcdc_hwmod = { static struct omap_hwmod am33xx_lcdc_hwmod = {
.name = "lcdc", .name = "lcdc",
.class = &am33xx_lcdc_hwmod_class, .class = &am33xx_lcdc_hwmod_class,
.clkdm_name = "lcdc_clkdm", .clkdm_name = "lcdc_clkdm",
.mpu_irqs = am33xx_lcdc_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "lcd_gclk", .main_clk = "lcd_gclk",
.prcm = { .prcm = {
...@@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { ...@@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
.sysc = &am33xx_mailbox_sysc, .sysc = &am33xx_mailbox_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
{ .irq = 77 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_mailbox_hwmod = { static struct omap_hwmod am33xx_mailbox_hwmod = {
.name = "mailbox", .name = "mailbox",
.class = &am33xx_mailbox_hwmod_class, .class = &am33xx_mailbox_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_mailbox_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { ...@@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
}; };
/* mcasp0 */ /* mcasp0 */
static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
{ .name = "ax", .irq = 80 + OMAP_INTC_START, },
{ .name = "ar", .irq = 81 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
{ .name = "tx", .dma_req = 8, },
{ .name = "rx", .dma_req = 9, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_mcasp0_hwmod = { static struct omap_hwmod am33xx_mcasp0_hwmod = {
.name = "mcasp0", .name = "mcasp0",
.class = &am33xx_mcasp_hwmod_class, .class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm", .clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mcasp0_irqs,
.sdma_reqs = am33xx_mcasp0_edma_reqs,
.main_clk = "mcasp0_fck", .main_clk = "mcasp0_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = { ...@@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
}; };
/* mcasp1 */ /* mcasp1 */
static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
{ .name = "ax", .irq = 82 + OMAP_INTC_START, },
{ .name = "ar", .irq = 83 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
{ .name = "tx", .dma_req = 10, },
{ .name = "rx", .dma_req = 11, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_mcasp1_hwmod = { static struct omap_hwmod am33xx_mcasp1_hwmod = {
.name = "mcasp1", .name = "mcasp1",
.class = &am33xx_mcasp_hwmod_class, .class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm", .clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mcasp1_irqs,
.sdma_reqs = am33xx_mcasp1_edma_reqs,
.main_clk = "mcasp1_fck", .main_clk = "mcasp1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = { ...@@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
}; };
/* mmc0 */ /* mmc0 */
static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
{ .irq = 64 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
{ .name = "tx", .dma_req = 24, },
{ .name = "rx", .dma_req = 25, },
{ .dma_req = -1 }
};
static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
}; };
...@@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = { ...@@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
.name = "mmc1", .name = "mmc1",
.class = &am33xx_mmc_hwmod_class, .class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_mmc0_irqs,
.sdma_reqs = am33xx_mmc0_edma_reqs,
.main_clk = "mmc_clk", .main_clk = "mmc_clk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = { ...@@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
}; };
/* mmc1 */ /* mmc1 */
static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
{ .irq = 28 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
{ .name = "tx", .dma_req = 2, },
{ .name = "rx", .dma_req = 3, },
{ .dma_req = -1 }
};
static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
}; };
...@@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = { ...@@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
.name = "mmc2", .name = "mmc2",
.class = &am33xx_mmc_hwmod_class, .class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_mmc1_irqs,
.sdma_reqs = am33xx_mmc1_edma_reqs,
.main_clk = "mmc_clk", .main_clk = "mmc_clk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = { ...@@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
}; };
/* mmc2 */ /* mmc2 */
static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
{ .irq = 29 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
{ .name = "tx", .dma_req = 64, },
{ .name = "rx", .dma_req = 65, },
{ .dma_req = -1 }
};
static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
}; };
...@@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = { ...@@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
.name = "mmc3", .name = "mmc3",
.class = &am33xx_mmc_hwmod_class, .class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l3s_clkdm", .clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mmc2_irqs,
.sdma_reqs = am33xx_mmc2_edma_reqs,
.main_clk = "mmc_clk", .main_clk = "mmc_clk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = { ...@@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
.sysc = &am33xx_rtc_sysc, .sysc = &am33xx_rtc_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
{ .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
{ .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_rtc_hwmod = { static struct omap_hwmod am33xx_rtc_hwmod = {
.name = "rtc", .name = "rtc",
.class = &am33xx_rtc_hwmod_class, .class = &am33xx_rtc_hwmod_class,
.clkdm_name = "l4_rtc_clkdm", .clkdm_name = "l4_rtc_clkdm",
.mpu_irqs = am33xx_rtc_irqs,
.main_clk = "clk_32768_ck", .main_clk = "clk_32768_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = { ...@@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
}; };
/* spi0 */ /* spi0 */
static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
{ .irq = 65 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
{ .name = "rx0", .dma_req = 17 },
{ .name = "tx0", .dma_req = 16 },
{ .name = "rx1", .dma_req = 19 },
{ .name = "tx1", .dma_req = 18 },
{ .dma_req = -1 }
};
static struct omap2_mcspi_dev_attr mcspi_attrib = { static struct omap2_mcspi_dev_attr mcspi_attrib = {
.num_chipselect = 2, .num_chipselect = 2,
}; };
...@@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = { ...@@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
.name = "spi0", .name = "spi0",
.class = &am33xx_spi_hwmod_class, .class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_spi0_irqs,
.sdma_reqs = am33xx_mcspi0_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = { ...@@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
}; };
/* spi1 */ /* spi1 */
static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
{ .irq = 125 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
{ .name = "rx0", .dma_req = 43 },
{ .name = "tx0", .dma_req = 42 },
{ .name = "rx1", .dma_req = 45 },
{ .name = "tx1", .dma_req = 44 },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_spi1_hwmod = { static struct omap_hwmod am33xx_spi1_hwmod = {
.name = "spi1", .name = "spi1",
.class = &am33xx_spi_hwmod_class, .class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_spi1_irqs,
.sdma_reqs = am33xx_mcspi1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { ...@@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
.sysc = &am33xx_timer1ms_sysc, .sysc = &am33xx_timer1ms_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
{ .irq = 67 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer1_hwmod = { static struct omap_hwmod am33xx_timer1_hwmod = {
.name = "timer1", .name = "timer1",
.class = &am33xx_timer1ms_hwmod_class, .class = &am33xx_timer1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_timer1_irqs,
.main_clk = "timer1_fck", .main_clk = "timer1_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = { ...@@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
{ .irq = 68 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer2_hwmod = { static struct omap_hwmod am33xx_timer2_hwmod = {
.name = "timer2", .name = "timer2",
.class = &am33xx_timer_hwmod_class, .class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer2_irqs,
.main_clk = "timer2_fck", .main_clk = "timer2_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = { ...@@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
{ .irq = 69 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer3_hwmod = { static struct omap_hwmod am33xx_timer3_hwmod = {
.name = "timer3", .name = "timer3",
.class = &am33xx_timer_hwmod_class, .class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer3_irqs,
.main_clk = "timer3_fck", .main_clk = "timer3_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = { ...@@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
{ .irq = 92 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer4_hwmod = { static struct omap_hwmod am33xx_timer4_hwmod = {
.name = "timer4", .name = "timer4",
.class = &am33xx_timer_hwmod_class, .class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer4_irqs,
.main_clk = "timer4_fck", .main_clk = "timer4_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = { ...@@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
{ .irq = 93 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer5_hwmod = { static struct omap_hwmod am33xx_timer5_hwmod = {
.name = "timer5", .name = "timer5",
.class = &am33xx_timer_hwmod_class, .class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer5_irqs,
.main_clk = "timer5_fck", .main_clk = "timer5_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = { ...@@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
{ .irq = 94 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer6_hwmod = { static struct omap_hwmod am33xx_timer6_hwmod = {
.name = "timer6", .name = "timer6",
.class = &am33xx_timer_hwmod_class, .class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer6_irqs,
.main_clk = "timer6_fck", .main_clk = "timer6_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = { ...@@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
{ .irq = 95 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer7_hwmod = { static struct omap_hwmod am33xx_timer7_hwmod = {
.name = "timer7", .name = "timer7",
.class = &am33xx_timer_hwmod_class, .class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer7_irqs,
.main_clk = "timer7_fck", .main_clk = "timer7_fck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { ...@@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
.name = "tpcc", .name = "tpcc",
}; };
static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
{ .name = "edma0", .irq = 12 + OMAP_INTC_START, },
{ .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
{ .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tpcc_hwmod = { static struct omap_hwmod am33xx_tpcc_hwmod = {
.name = "tpcc", .name = "tpcc",
.class = &am33xx_tpcc_hwmod_class, .class = &am33xx_tpcc_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tpcc_irqs,
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = { ...@@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
}; };
/* tptc0 */ /* tptc0 */
static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
{ .irq = 112 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tptc0_hwmod = { static struct omap_hwmod am33xx_tptc0_hwmod = {
.name = "tptc0", .name = "tptc0",
.class = &am33xx_tptc_hwmod_class, .class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc0_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
...@@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = { ...@@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
}; };
/* tptc1 */ /* tptc1 */
static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
{ .irq = 113 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tptc1_hwmod = { static struct omap_hwmod am33xx_tptc1_hwmod = {
.name = "tptc1", .name = "tptc1",
.class = &am33xx_tptc_hwmod_class, .class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc1_irqs,
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
...@@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = { ...@@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
}; };
/* tptc2 */ /* tptc2 */
static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
{ .irq = 114 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tptc2_hwmod = { static struct omap_hwmod am33xx_tptc2_hwmod = {
.name = "tptc2", .name = "tptc2",
.class = &am33xx_tptc_hwmod_class, .class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc2_irqs,
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
...@@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = { ...@@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = {
}; };
/* uart1 */ /* uart1 */
static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
{ .name = "tx", .dma_req = 26, },
{ .name = "rx", .dma_req = 27, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
{ .irq = 72 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart1_hwmod = { static struct omap_hwmod am33xx_uart1_hwmod = {
.name = "uart1", .name = "uart1",
.class = &uart_class, .class = &uart_class,
.clkdm_name = "l4_wkup_clkdm", .clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT, .flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart1_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_wkupdm_ck", .main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2007,18 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = { ...@@ -2007,18 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
{ .irq = 73 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart2_hwmod = { static struct omap_hwmod am33xx_uart2_hwmod = {
.name = "uart2", .name = "uart2",
.class = &uart_class, .class = &uart_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT, .flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart2_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2029,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = { ...@@ -2029,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
}; };
/* uart3 */ /* uart3 */
static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
{ .name = "tx", .dma_req = 30, },
{ .name = "rx", .dma_req = 31, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
{ .irq = 74 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart3_hwmod = { static struct omap_hwmod am33xx_uart3_hwmod = {
.name = "uart3", .name = "uart3",
.class = &uart_class, .class = &uart_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT, .flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart3_irqs,
.sdma_reqs = uart3_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2056,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = { ...@@ -2056,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
{ .irq = 44 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart4_hwmod = { static struct omap_hwmod am33xx_uart4_hwmod = {
.name = "uart4", .name = "uart4",
.class = &uart_class, .class = &uart_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT, .flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart4_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2077,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = { ...@@ -2077,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
{ .irq = 45 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart5_hwmod = { static struct omap_hwmod am33xx_uart5_hwmod = {
.name = "uart5", .name = "uart5",
.class = &uart_class, .class = &uart_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT, .flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart5_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2098,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = { ...@@ -2098,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
}, },
}; };
static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
{ .irq = 46 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart6_hwmod = { static struct omap_hwmod am33xx_uart6_hwmod = {
.name = "uart6", .name = "uart6",
.class = &uart_class, .class = &uart_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT, .flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart6_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck", .main_clk = "dpll_per_m2_div4_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
...@@ -2173,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = { ...@@ -2173,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
.sysc = &am33xx_usbhsotg_sysc, .sysc = &am33xx_usbhsotg_sysc,
}; };
static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
{ .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
{ .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
{ .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
{ .irq = -1, },
};
static struct omap_hwmod am33xx_usbss_hwmod = { static struct omap_hwmod am33xx_usbss_hwmod = {
.name = "usb_otg_hs", .name = "usb_otg_hs",
.class = &am33xx_usbotg_class, .class = &am33xx_usbotg_class,
.clkdm_name = "l3s_clkdm", .clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_usbss_mpu_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "usbotg_fck", .main_clk = "usbotg_fck",
.prcm = { .prcm = {
...@@ -2200,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = { ...@@ -2200,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
* Interfaces * Interfaces
*/ */
/* l4 fw -> emif fw */
static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
.master = &am33xx_l4_fw_hwmod,
.slave = &am33xx_emif_fw_hwmod,
.clk = "l4fw_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
{ {
.pa_start = 0x4c000000, .pa_start = 0x4c000000,
...@@ -2265,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { ...@@ -2265,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3 s -> l4 fw */
static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_l4_fw_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> l3 instr */ /* l3 main -> l3 instr */
static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
...@@ -2322,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { ...@@ -2322,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
}; };
/* l4 wkup -> wkup m3 */ /* l4 wkup -> wkup m3 */
static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
{
.name = "umem",
.pa_start = 0x44d00000,
.pa_end = 0x44d00000 + SZ_16K - 1,
.flags = ADDR_TYPE_RT
},
{
.name = "dmem",
.pa_start = 0x44d80000,
.pa_end = 0x44d80000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wkup_m3_hwmod, .slave = &am33xx_wkup_m3_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_wkup_m3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 hs -> pru-icss */ /* l4 hs -> pru-icss */
static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
{
.pa_start = 0x4a300000,
.pa_end = 0x4a300000 + SZ_512K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
.master = &am33xx_l4_hs_hwmod, .master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_pruss_hwmod, .slave = &am33xx_pruss_hwmod,
.clk = "dpll_core_m4_ck", .clk = "dpll_core_m4_ck",
.addr = am33xx_pruss_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3 main -> gfx */ /* l3 main -> gfx */
static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
{
.pa_start = 0x56000000,
.pa_end = 0x56000000 + SZ_16M - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
.slave = &am33xx_gfx_hwmod, .slave = &am33xx_gfx_hwmod,
.clk = "dpll_core_m4_ck", .clk = "dpll_core_m4_ck",
.addr = am33xx_gfx_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 wkup -> smartreflex0 */ /* l4 wkup -> smartreflex0 */
static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
{
.pa_start = 0x44e37000,
.pa_end = 0x44e37000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod, .slave = &am33xx_smartreflex0_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_smartreflex0_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 wkup -> smartreflex1 */ /* l4 wkup -> smartreflex1 */
static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
{
.pa_start = 0x44e39000,
.pa_end = 0x44e39000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex1_hwmod, .slave = &am33xx_smartreflex1_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_smartreflex1_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 wkup -> control */ /* l4 wkup -> control */
static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
{
.pa_start = 0x44e10000,
.pa_end = 0x44e10000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_control_hwmod, .slave = &am33xx_control_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_control_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 wkup -> rtc */ /* l4 wkup -> rtc */
static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
{
.pa_start = 0x44e3e000,
.pa_end = 0x44e3e000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_rtc_hwmod, .slave = &am33xx_rtc_hwmod,
.clk = "clkdiv32k_ick", .clk = "clkdiv32k_ick",
.addr = am33xx_rtc_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per/ls -> DCAN0 */ /* l4 per/ls -> DCAN0 */
static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
{
.pa_start = 0x481CC000,
.pa_end = 0x481CC000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan0_hwmod, .slave = &am33xx_dcan0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_dcan0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 per/ls -> DCAN1 */ /* l4 per/ls -> DCAN1 */
static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
{
.pa_start = 0x481D0000,
.pa_end = 0x481D0000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan1_hwmod, .slave = &am33xx_dcan1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_dcan1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 per/ls -> GPIO2 */ /* l4 per/ls -> GPIO2 */
static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
{
.pa_start = 0x4804C000,
.pa_end = 0x4804C000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio1_hwmod, .slave = &am33xx_gpio1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_gpio1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 per/ls -> gpio3 */ /* l4 per/ls -> gpio3 */
static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
{
.pa_start = 0x481AC000,
.pa_end = 0x481AC000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio2_hwmod, .slave = &am33xx_gpio2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_gpio2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 per/ls -> gpio4 */ /* l4 per/ls -> gpio4 */
static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
{
.pa_start = 0x481AE000,
.pa_end = 0x481AE000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio3_hwmod, .slave = &am33xx_gpio3_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_gpio3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 WKUP -> I2C1 */ /* L4 WKUP -> I2C1 */
static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
{
.pa_start = 0x44E0B000,
.pa_end = 0x44E0B000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_i2c1_hwmod, .slave = &am33xx_i2c1_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_i2c1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* L4 WKUP -> GPIO1 */ /* L4 WKUP -> GPIO1 */
static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
{
.pa_start = 0x44E07000,
.pa_end = 0x44E07000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_gpio0_hwmod, .slave = &am33xx_gpio0_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_gpio0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2598,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { ...@@ -2598,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
/* cpsw ss */
{
.pa_start = 0x4a100000,
.pa_end = 0x4a100000 + SZ_2K - 1,
},
/* cpsw wr */
{
.pa_start = 0x4a101200,
.pa_end = 0x4a101200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.master = &am33xx_l4_hs_hwmod, .master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod, .slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk", .clk = "cpsw_125mhz_gclk",
.addr = am33xx_cpgmac0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
{
.pa_start = 0x4A101000,
.pa_end = 0x4A101000 + SZ_256 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.master = &am33xx_cpgmac0_hwmod, .master = &am33xx_cpgmac0_hwmod,
.slave = &am33xx_mdio_hwmod, .slave = &am33xx_mdio_hwmod,
.addr = am33xx_mdio_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2670,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { ...@@ -2670,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
{
.pa_start = 0x48300100,
.pa_end = 0x48300100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
.master = &am33xx_epwmss0_hwmod, .master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ecap0_hwmod, .slave = &am33xx_ecap0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ecap0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
{
.pa_start = 0x48300180,
.pa_end = 0x48300180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
.master = &am33xx_epwmss0_hwmod, .master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_eqep0_hwmod, .slave = &am33xx_eqep0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_eqep0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
{
.pa_start = 0x48300200,
.pa_end = 0x48300200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
.master = &am33xx_epwmss0_hwmod, .master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ehrpwm0_hwmod, .slave = &am33xx_ehrpwm0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ehrpwm0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2736,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { ...@@ -2736,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
{
.pa_start = 0x48302100,
.pa_end = 0x48302100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
.master = &am33xx_epwmss1_hwmod, .master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ecap1_hwmod, .slave = &am33xx_ecap1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ecap1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
{
.pa_start = 0x48302180,
.pa_end = 0x48302180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
.master = &am33xx_epwmss1_hwmod, .master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_eqep1_hwmod, .slave = &am33xx_eqep1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_eqep1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
{
.pa_start = 0x48302200,
.pa_end = 0x48302200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
.master = &am33xx_epwmss1_hwmod, .master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ehrpwm1_hwmod, .slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2801,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { ...@@ -2801,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
{
.pa_start = 0x48304100,
.pa_end = 0x48304100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
.master = &am33xx_epwmss2_hwmod, .master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ecap2_hwmod, .slave = &am33xx_ecap2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ecap2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
{
.pa_start = 0x48304180,
.pa_end = 0x48304180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
.master = &am33xx_epwmss2_hwmod, .master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_eqep2_hwmod, .slave = &am33xx_eqep2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_eqep2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
{
.pa_start = 0x48304200,
.pa_end = 0x48304200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
.master = &am33xx_epwmss2_hwmod, .master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ehrpwm2_hwmod, .slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2868,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { ...@@ -2868,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
}; };
/* i2c2 */ /* i2c2 */
static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
{
.pa_start = 0x4802A000,
.pa_end = 0x4802A000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_i2c2_hwmod, .slave = &am33xx_i2c2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_i2c2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
{
.pa_start = 0x4819C000,
.pa_end = 0x4819C000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_i2c3_hwmod, .slave = &am33xx_i2c3_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_i2c3_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2938,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { ...@@ -2938,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
}; };
/* l4 ls -> spinlock */ /* l4 ls -> spinlock */
static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
{
.pa_start = 0x480Ca000,
.pa_end = 0x480Ca000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spinlock_hwmod, .slave = &am33xx_spinlock_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_spinlock_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2973,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { ...@@ -2973,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l3 s -> mcasp0 data */
static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
{
.pa_start = 0x46000000,
.pa_end = 0x46000000 + SZ_4M - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_mcasp0_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_mcasp0_data_addr_space,
.user = OCP_USER_SDMA,
};
/* l4 ls -> mcasp1 */ /* l4 ls -> mcasp1 */
static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
{ {
...@@ -3009,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { ...@@ -3009,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l3 s -> mcasp1 data */
static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
{
.pa_start = 0x46400000,
.pa_end = 0x46400000 + SZ_4M - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_mcasp1_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_mcasp1_data_addr_space,
.user = OCP_USER_SDMA,
};
/* l4 ls -> mmc0 */ /* l4 ls -> mmc0 */
static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
{ {
...@@ -3082,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { ...@@ -3082,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
}; };
/* l4 ls -> mcspi0 */ /* l4 ls -> mcspi0 */
static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
{
.pa_start = 0x48030000,
.pa_end = 0x48030000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi0_hwmod, .slave = &am33xx_spi0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_mcspi0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 ls -> mcspi1 */ /* l4 ls -> mcspi1 */
static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
{
.pa_start = 0x481A0000,
.pa_end = 0x481A0000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi1_hwmod, .slave = &am33xx_spi1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_mcspi1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 wkup -> timer1 */ /* l4 wkup -> timer1 */
static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
{
.pa_start = 0x44E31000,
.pa_end = 0x44E31000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod, .slave = &am33xx_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_timer1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per -> timer2 */ /* l4 per -> timer2 */
static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
{
.pa_start = 0x48040000,
.pa_end = 0x48040000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer2_hwmod, .slave = &am33xx_timer2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_timer2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per -> timer3 */ /* l4 per -> timer3 */
static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
{
.pa_start = 0x48042000,
.pa_end = 0x48042000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer3_hwmod, .slave = &am33xx_timer3_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_timer3_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per -> timer4 */ /* l4 per -> timer4 */
static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
{
.pa_start = 0x48044000,
.pa_end = 0x48044000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer4_hwmod, .slave = &am33xx_timer4_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_timer4_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per -> timer5 */ /* l4 per -> timer5 */
static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
{
.pa_start = 0x48046000,
.pa_end = 0x48046000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer5_hwmod, .slave = &am33xx_timer5_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_timer5_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per -> timer6 */ /* l4 per -> timer6 */
static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
{
.pa_start = 0x48048000,
.pa_end = 0x48048000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer6_hwmod, .slave = &am33xx_timer6_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_timer6_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 per -> timer7 */ /* l4 per -> timer7 */
static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
{
.pa_start = 0x4804A000,
.pa_end = 0x4804A000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer7_hwmod, .slave = &am33xx_timer7_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_timer7_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l3 main -> tpcc */ /* l3 main -> tpcc */
static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
{
.pa_start = 0x49000000,
.pa_end = 0x49000000 + SZ_32K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tpcc_hwmod, .slave = &am33xx_tpcc_hwmod,
.clk = "l3_gclk", .clk = "l3_gclk",
.addr = am33xx_tpcc_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -3316,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { ...@@ -3316,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
}; };
/* l4 wkup -> uart1 */ /* l4 wkup -> uart1 */
static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
{
.pa_start = 0x44E09000,
.pa_end = 0x44E09000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_uart1_hwmod, .slave = &am33xx_uart1_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_uart1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 ls -> uart2 */ /* l4 ls -> uart2 */
static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
{
.pa_start = 0x48022000,
.pa_end = 0x48022000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart2_hwmod, .slave = &am33xx_uart2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_uart2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 ls -> uart3 */ /* l4 ls -> uart3 */
static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
{
.pa_start = 0x48024000,
.pa_end = 0x48024000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart3_hwmod, .slave = &am33xx_uart3_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_uart3_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 ls -> uart4 */ /* l4 ls -> uart4 */
static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
{
.pa_start = 0x481A6000,
.pa_end = 0x481A6000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart4_hwmod, .slave = &am33xx_uart4_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_uart4_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 ls -> uart5 */ /* l4 ls -> uart5 */
static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
{
.pa_start = 0x481A8000,
.pa_end = 0x481A8000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart5_hwmod, .slave = &am33xx_uart5_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_uart5_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 ls -> uart6 */ /* l4 ls -> uart6 */
static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
{
.pa_start = 0x481aa000,
.pa_end = 0x481aa000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart6_hwmod, .slave = &am33xx_uart6_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_uart6_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* l4 wkup -> wd_timer1 */ /* l4 wkup -> wd_timer1 */
static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
{
.pa_start = 0x44e35000,
.pa_end = 0x44e35000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wd_timer1_hwmod, .slave = &am33xx_wd_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck", .clk = "dpll_core_m4_div2_ck",
.addr = am33xx_wd_timer1_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* usbss */ /* usbss */
/* l3 s -> USBSS interface */ /* l3 s -> USBSS interface */
static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
{
.name = "usbss",
.pa_start = 0x47400000,
.pa_end = 0x47400000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{
.name = "musb0",
.pa_start = 0x47401000,
.pa_end = 0x47401000 + SZ_2K - 1,
.flags = ADDR_TYPE_RT
},
{
.name = "musb1",
.pa_start = 0x47401800,
.pa_end = 0x47401800 + SZ_2K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.master = &am33xx_l3_s_hwmod, .master = &am33xx_l3_s_hwmod,
.slave = &am33xx_usbss_hwmod, .slave = &am33xx_usbss_hwmod,
.clk = "l3s_gclk", .clk = "l3s_gclk",
.addr = am33xx_usbss_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
.flags = OCPIF_SWSUP_IDLE, .flags = OCPIF_SWSUP_IDLE,
}; };
...@@ -3518,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { ...@@ -3518,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
}; };
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif, &am33xx_l3_main__emif,
&am33xx_mpu__l3_main, &am33xx_mpu__l3_main,
&am33xx_mpu__prcm, &am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls, &am33xx_l3_s__l4_ls,
&am33xx_l3_s__l4_wkup, &am33xx_l3_s__l4_wkup,
&am33xx_l3_s__l4_fw,
&am33xx_l3_main__l4_hs, &am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s, &am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr, &am33xx_l3_main__l3_instr,
...@@ -3554,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3554,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_per__i2c3, &am33xx_l4_per__i2c3,
&am33xx_l4_per__mailbox, &am33xx_l4_per__mailbox,
&am33xx_l4_ls__mcasp0, &am33xx_l4_ls__mcasp0,
&am33xx_l3_s__mcasp0_data,
&am33xx_l4_ls__mcasp1, &am33xx_l4_ls__mcasp1,
&am33xx_l3_s__mcasp1_data,
&am33xx_l4_ls__mmc0, &am33xx_l4_ls__mmc0,
&am33xx_l4_ls__mmc1, &am33xx_l4_ls__mmc1,
&am33xx_l3_s__mmc2, &am33xx_l3_s__mmc2,
......
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