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Commit 492d2b61 authored by Alex Deucher's avatar Alex Deucher
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drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT 

Avoid confusion with the *REG32_P mask macro.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0363a559
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Showing with 51 additions and 51 deletions
drivers/gpu/drm/radeon/evergreen.c
View file @ 492d2b61
...@@ -4130,7 +4130,7 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -4130,7 +4130,7 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
if (!(mask & DRM_PCIE_SPEED_50)) if (!(mask & DRM_PCIE_SPEED_50))
return; return;
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
if (speed_cntl & LC_CURRENT_DATA_RATE) { if (speed_cntl & LC_CURRENT_DATA_RATE) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n"); DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return; return;
...@@ -4141,33 +4141,33 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -4141,33 +4141,33 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_GEN2_EN_STRAP; speed_cntl |= LC_GEN2_EN_STRAP;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
} else { } else {
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
if (1) if (1)
link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl |= LC_UPCONFIGURE_DIS;
else else
link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} }
} }
drivers/gpu/drm/radeon/r600.c
View file @ 492d2b61
...@@ -4562,7 +4562,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) ...@@ -4562,7 +4562,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
break; break;
} }
link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
...@@ -4577,7 +4577,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) ...@@ -4577,7 +4577,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
link_width_cntl |= mask; link_width_cntl |= mask;
WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
/* some northbridges can renegotiate the link rather than requiring /* some northbridges can renegotiate the link rather than requiring
* a complete re-config. * a complete re-config.
...@@ -4588,7 +4588,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) ...@@ -4588,7 +4588,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
else else
link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
RADEON_PCIE_LC_RECONFIG_NOW)); RADEON_PCIE_LC_RECONFIG_NOW));
if (rdev->family >= CHIP_RV770) if (rdev->family >= CHIP_RV770)
...@@ -4619,7 +4619,7 @@ int r600_get_pcie_lanes(struct radeon_device *rdev) ...@@ -4619,7 +4619,7 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
/* FIXME wait for idle */ /* FIXME wait for idle */
link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
case RADEON_PCIE_LC_LINK_WIDTH_X0: case RADEON_PCIE_LC_LINK_WIDTH_X0:
...@@ -4669,7 +4669,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -4669,7 +4669,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
if (!(mask & DRM_PCIE_SPEED_50)) if (!(mask & DRM_PCIE_SPEED_50))
return; return;
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
if (speed_cntl & LC_CURRENT_DATA_RATE) { if (speed_cntl & LC_CURRENT_DATA_RATE) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n"); DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return; return;
...@@ -4682,23 +4682,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -4682,23 +4682,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
(rdev->family == CHIP_RV620) || (rdev->family == CHIP_RV620) ||
(rdev->family == CHIP_RV635)) { (rdev->family == CHIP_RV635)) {
/* advertise upconfig capability */ /* advertise upconfig capability */
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
link_width_cntl &= ~(LC_LINK_WIDTH_MASK | link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
LC_RECONFIG_ARC_MISSING_ESCAPE); LC_RECONFIG_ARC_MISSING_ESCAPE);
link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} else { } else {
link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl |= LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} }
} }
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
...@@ -4719,7 +4719,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -4719,7 +4719,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
tmp = RREG32(0x541c); tmp = RREG32(0x541c);
WREG32(0x541c, tmp | 0x8); WREG32(0x541c, tmp | 0x8);
...@@ -4733,27 +4733,27 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -4733,27 +4733,27 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
if ((rdev->family == CHIP_RV670) || if ((rdev->family == CHIP_RV670) ||
(rdev->family == CHIP_RV620) || (rdev->family == CHIP_RV620) ||
(rdev->family == CHIP_RV635)) { (rdev->family == CHIP_RV635)) {
training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
training_cntl &= ~LC_POINT_7_PLUS_EN; training_cntl &= ~LC_POINT_7_PLUS_EN;
WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
} else { } else {
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
} }
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_GEN2_EN_STRAP; speed_cntl |= LC_GEN2_EN_STRAP;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
} else { } else {
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
if (1) if (1)
link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl |= LC_UPCONFIGURE_DIS;
else else
link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} }
} }
......
drivers/gpu/drm/radeon/radeon.h
View file @ 492d2b61
...@@ -1731,8 +1731,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); ...@@ -1731,8 +1731,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
#define WREG32_P(reg, val, mask) \ #define WREG32_P(reg, val, mask) \
do { \ do { \
uint32_t tmp_ = RREG32(reg); \ uint32_t tmp_ = RREG32(reg); \
......
drivers/gpu/drm/radeon/rv770.c
View file @ 492d2b61
...@@ -1557,23 +1557,23 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -1557,23 +1557,23 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
/* advertise upconfig capability */ /* advertise upconfig capability */
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
link_width_cntl &= ~(LC_LINK_WIDTH_MASK | link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
LC_RECONFIG_ARC_MISSING_ESCAPE); LC_RECONFIG_ARC_MISSING_ESCAPE);
link_width_cntl |= lanes | LC_RECONFIG_NOW | link_width_cntl |= lanes | LC_RECONFIG_NOW |
LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} else { } else {
link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl |= LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} }
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
...@@ -1586,29 +1586,29 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) ...@@ -1586,29 +1586,29 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
WREG16(0x4088, link_cntl2); WREG16(0x4088, link_cntl2);
WREG32(MM_CFGREGS_CNTL, 0); WREG32(MM_CFGREGS_CNTL, 0);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_GEN2_EN_STRAP; speed_cntl |= LC_GEN2_EN_STRAP;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
} else { } else {
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
if (1) if (1)
link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl |= LC_UPCONFIGURE_DIS;
else else
link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
} }
} }
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