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Commit 4d34686e authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/pm: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 87c33f4e
Expand all Show whitespace changes
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Showing with 516 additions and 448 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
View file @ 4d34686e
#ifndef __NVKM_PM_H__
#define __NVKM_PM_H__
#include <core/device.h>
#include <core/engine.h>
#include <core/engctx.h>
struct nouveau_perfdom;
struct nouveau_perfctr;
struct nouveau_pm {
struct nouveau_engine base;
struct nvkm_perfdom;
struct nvkm_perfctr;
struct nvkm_pm {
struct nvkm_engine base;
struct nouveau_perfctx *context;
struct nvkm_perfctx *context;
void *profile_data;
struct list_head domains;
......@@ -21,18 +18,17 @@ struct nouveau_pm {
u32 last;
};
static inline struct nouveau_pm *
nouveau_pm(void *obj)
static inline struct nvkm_pm *
nvkm_pm(void *obj)
{
return (void *)nouveau_engine(obj, NVDEV_ENGINE_PM);
return (void *)nvkm_engine(obj, NVDEV_ENGINE_PM);
}
extern struct nouveau_oclass *nv40_pm_oclass;
extern struct nouveau_oclass *nv50_pm_oclass;
extern struct nouveau_oclass *nv84_pm_oclass;
extern struct nouveau_oclass *nva3_pm_oclass;
extern struct nouveau_oclass nvc0_pm_oclass;
extern struct nouveau_oclass nve0_pm_oclass;
extern struct nouveau_oclass nvf0_pm_oclass;
extern struct nvkm_oclass *nv40_pm_oclass;
extern struct nvkm_oclass *nv50_pm_oclass;
extern struct nvkm_oclass *g84_pm_oclass;
extern struct nvkm_oclass *gt215_pm_oclass;
extern struct nvkm_oclass gf100_pm_oclass;
extern struct nvkm_oclass gk104_pm_oclass;
extern struct nvkm_oclass gk110_pm_oclass;
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 4d34686e
......@@ -114,7 +114,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->cname = "G86";
......@@ -143,7 +143,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->cname = "G92";
......@@ -172,7 +172,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->cname = "G94";
......@@ -201,7 +201,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->cname = "G96";
......@@ -230,7 +230,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->cname = "G98";
......@@ -259,7 +259,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->cname = "G200";
......@@ -288,7 +288,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
......@@ -317,7 +317,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->cname = "MCP79/MCP7A";
......@@ -346,7 +346,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->cname = "GT215";
......@@ -377,7 +377,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->cname = "GT216";
......@@ -407,7 +407,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->cname = "GT218";
......@@ -437,7 +437,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->cname = "MCP89";
......@@ -467,7 +467,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
default:
nv_fatal(device, "unknown Tesla chipset\n");
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View file @ 4d34686e
......@@ -90,7 +90,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc4:
device->cname = "GF104";
......@@ -123,7 +123,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc3:
device->cname = "GF106";
......@@ -155,7 +155,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xce:
device->cname = "GF114";
......@@ -188,7 +188,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xcf:
device->cname = "GF116";
......@@ -220,7 +220,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc1:
device->cname = "GF108";
......@@ -252,7 +252,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc8:
device->cname = "GF110";
......@@ -285,7 +285,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xd9:
device->cname = "GF119";
......@@ -317,7 +317,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xd7:
device->cname = "GF117";
......@@ -347,7 +347,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
default:
nv_fatal(device, "unknown Fermi chipset\n");
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View file @ 4d34686e
......@@ -91,7 +91,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
break;
case 0xe7:
device->cname = "GK107";
......@@ -125,7 +125,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
break;
case 0xe6:
device->cname = "GK106";
......@@ -159,7 +159,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
break;
case 0xea:
device->cname = "GK20A";
......@@ -179,7 +179,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
......@@ -215,7 +215,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->cname = "GK110B";
......@@ -249,7 +249,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->cname = "GK208B";
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
View file @ 4d34686e
......@@ -2,8 +2,8 @@ nvkm-y += nvkm/engine/pm/base.o
nvkm-y += nvkm/engine/pm/daemon.o
nvkm-y += nvkm/engine/pm/nv40.o
nvkm-y += nvkm/engine/pm/nv50.o
nvkm-y += nvkm/engine/pm/nv84.o
nvkm-y += nvkm/engine/pm/nva3.o
nvkm-y += nvkm/engine/pm/nvc0.o
nvkm-y += nvkm/engine/pm/nve0.o
nvkm-y += nvkm/engine/pm/nvf0.o
nvkm-y += nvkm/engine/pm/g84.o
nvkm-y += nvkm/engine/pm/gt215.o
nvkm-y += nvkm/engine/pm/gf100.o
nvkm-y += nvkm/engine/pm/gk104.o
nvkm-y += nvkm/engine/pm/gk110.o
drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
View file @ 4d34686e
......@@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
pwr_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
u32 mask = 0x00000000;
u32 ctrl = 0x00000001;
......@@ -41,15 +40,15 @@ pwr_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
pwr_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
ctr->clk = ppm->pwr[ppm->last];
}
static void
pwr_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
int i;
......@@ -59,16 +58,16 @@ pwr_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
}
}
static const struct nouveau_funcdom
static const struct nvkm_funcdom
pwr_perfctr_func = {
.init = pwr_perfctr_init,
.read = pwr_perfctr_read,
.next = pwr_perfctr_next,
};
const struct nouveau_specdom
nva3_pm_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
const struct nvkm_specdom
gt215_pm_pwr[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
......@@ -79,9 +78,9 @@ nva3_pm_pwr[] = {
{}
};
const struct nouveau_specdom
nvc0_pm_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
const struct nvkm_specdom
gf100_pm_pwr[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
......@@ -93,9 +92,9 @@ nvc0_pm_pwr[] = {
{}
};
const struct nouveau_specdom
nve0_pm_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
const struct nvkm_specdom
gk104_pm_pwr[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c → drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
View file @ 4d34686e
......@@ -21,58 +21,45 @@
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv84_pm[] = {
{ 0x20, (const struct nouveau_specsig[]) {
static const struct nvkm_specdom
g84_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv84_pm_oclass = &(struct nv40_pm_oclass) {
struct nvkm_oclass *
g84_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = _nouveau_pm_fini,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = _nvkm_pm_fini,
},
.doms = nv84_pm,
.doms = g84_pm,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
View file @ 4d34686e
......@@ -21,42 +21,29 @@
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nvc0_pm_hub[] = {
static const struct nvkm_specdom
gf100_pm_hub[] = {
{}
};
static const struct nouveau_specdom
nvc0_pm_gpc[] = {
static const struct nvkm_specdom
gf100_pm_gpc[] = {
{}
};
static const struct nouveau_specdom
nvc0_pm_part[] = {
static const struct nvkm_specdom
gf100_pm_part[] = {
{}
};
static void
nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
gf100_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
struct nvc0_pm_priv *priv = (void *)ppm;
struct nvc0_pm_cntr *cntr = (void *)ctr;
struct gf100_pm_priv *priv = (void *)ppm;
struct gf100_pm_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
......@@ -71,11 +58,11 @@ nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
gf100_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
struct nvc0_pm_priv *priv = (void *)ppm;
struct nvc0_pm_cntr *cntr = (void *)ctr;
struct gf100_pm_priv *priv = (void *)ppm;
struct gf100_pm_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
......@@ -87,51 +74,50 @@ nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
nvc0_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
gf100_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
struct nvc0_pm_priv *priv = (void *)ppm;
struct gf100_pm_priv *priv = (void *)ppm;
nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
}
const struct nouveau_funcdom
nvc0_perfctr_func = {
.init = nvc0_perfctr_init,
.read = nvc0_perfctr_read,
.next = nvc0_perfctr_next,
const struct nvkm_funcdom
gf100_perfctr_func = {
.init = gf100_perfctr_init,
.read = gf100_perfctr_read,
.next = gf100_perfctr_next,
};
int
nvc0_pm_fini(struct nouveau_object *object, bool suspend)
gf100_pm_fini(struct nvkm_object *object, bool suspend)
{
struct nvc0_pm_priv *priv = (void *)object;
struct gf100_pm_priv *priv = (void *)object;
nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
return nouveau_pm_fini(&priv->base, suspend);
return nvkm_pm_fini(&priv->base, suspend);
}
static int
nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvc0_pm_priv *priv;
struct gf100_pm_priv *priv;
u32 mask;
int ret;
ret = nouveau_pm_create(parent, engine, oclass, &priv);
ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nvc0_pm_pwr);
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gf100_pm_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nvc0_pm_hub);
ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
gf100_pm_hub);
if (ret)
return ret;
......@@ -140,8 +126,8 @@ nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nvc0_pm_gpc);
ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, gf100_pm_gpc);
if (ret)
return ret;
......@@ -150,24 +136,24 @@ nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nvc0_pm_part);
ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, gf100_pm_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_pm_cclass;
nv_engine(priv)->sclass = nouveau_pm_sclass;
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nvc0_pm_oclass = {
struct nvkm_oclass
gf100_pm_oclass = {
.handle = NV_ENGINE(PM, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = nvc0_pm_fini,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = gf100_pm_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h → drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
View file @ 4d34686e
#ifndef __NVKM_PM_NVC0_H__
#define __NVKM_PM_NVC0_H__
#include "priv.h"
struct nvc0_pm_priv {
struct nouveau_pm base;
struct gf100_pm_priv {
struct nvkm_pm base;
};
struct nvc0_pm_cntr {
struct nouveau_perfctr base;
struct gf100_pm_cntr {
struct nvkm_perfctr base;
};
extern const struct nouveau_funcdom nvc0_perfctr_func;
int nvc0_pm_fini(struct nouveau_object *, bool);
extern const struct nvkm_funcdom gf100_perfctr_func;
int gf100_pm_fini(struct nvkm_object *, bool);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c → drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
View file @ 4d34686e
......@@ -21,106 +21,92 @@
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nve0_pm_hub[] = {
{ 0x60, (const struct nouveau_specsig[]) {
static const struct nvkm_specdom
gk104_pm_hub[] = {
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "hub00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x40, (const struct nvkm_specsig[]) {
{ 0x27, "hub01_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "hub02_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "hub03_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x40, (const struct nvkm_specsig[]) {
{ 0x03, "host_mmio_rd" },
{ 0x27, "hub04_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "hub05_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0xc0, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0xc0, (const struct nvkm_specsig[]) {
{ 0x74, "host_fb_rd3x" },
{ 0x75, "host_fb_rd3x_2" },
{ 0xa7, "hub06_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "hub07_user_0" },
{}
}, &nvc0_perfctr_func },
}, &gf100_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_pm_gpc[] = {
{ 0xe0, (const struct nouveau_specsig[]) {
static const struct nvkm_specdom
gk104_pm_gpc[] = {
{ 0xe0, (const struct nvkm_specsig[]) {
{ 0xc7, "gpc00_user_0" },
{}
}, &nvc0_perfctr_func },
}, &gf100_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_pm_part[] = {
{ 0x60, (const struct nouveau_specsig[]) {
static const struct nvkm_specdom
gk104_pm_part[] = {
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "part00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
}, &gf100_perfctr_func },
{ 0x60, (const struct nvkm_specsig[]) {
{ 0x47, "part01_user_0" },
{}
}, &nvc0_perfctr_func },
}, &gf100_perfctr_func },
{}
};
static int
nve0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvc0_pm_priv *priv;
struct gf100_pm_priv *priv;
u32 mask;
int ret;
ret = nouveau_pm_create(parent, engine, oclass, &priv);
ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
/* PDAEMON */
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_pm_pwr);
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nve0_pm_hub);
ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
gk104_pm_hub);
if (ret)
return ret;
......@@ -129,8 +115,8 @@ nve0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nve0_pm_gpc);
ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, gk104_pm_gpc);
if (ret)
return ret;
......@@ -139,24 +125,24 @@ nve0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nve0_pm_part);
ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, gk104_pm_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_pm_cclass;
nv_engine(priv)->sclass = nouveau_pm_sclass;
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nve0_pm_oclass = {
struct nvkm_oclass
gk104_pm_oclass = {
.handle = NV_ENGINE(PM, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = nvc0_pm_fini,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk104_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = gf100_pm_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c → drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c
View file @ 4d34686e
......@@ -21,51 +21,37 @@
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
#include "gf100.h"
static int
nvf0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvc0_pm_priv *priv;
struct gf100_pm_priv *priv;
int ret;
ret = nouveau_pm_create(parent, engine, oclass, &priv);
ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_pm_pwr);
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_pm_cclass;
nv_engine(priv)->sclass = nouveau_pm_sclass;
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
return 0;
}
struct nouveau_oclass
nvf0_pm_oclass = {
struct nvkm_oclass
gk110_pm_oclass = {
.handle = NV_ENGINE(PM, 0xf0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvf0_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = nvc0_pm_fini,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk110_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = gf100_pm_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c → drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
View file @ 4d34686e
......@@ -21,60 +21,47 @@
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nva3_pm[] = {
{ 0x20, (const struct nouveau_specsig[]) {
static const struct nvkm_specdom
gt215_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
static int
nva3_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **object)
gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **object)
{
int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
struct nv40_pm_priv *priv = (void *)*object;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nva3_pm_pwr);
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
gt215_pm_pwr);
if (ret)
return ret;
......@@ -83,14 +70,14 @@ nva3_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
}
struct nouveau_oclass *
nva3_pm_oclass = &(struct nv40_pm_oclass) {
struct nvkm_oclass *
gt215_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = _nouveau_pm_fini,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gt215_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = _nvkm_pm_fini,
},
.doms = nva3_pm,
.doms = gt215_pm,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
View file @ 4d34686e
......@@ -21,24 +21,11 @@
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static void
nv40_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
nv40_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
struct nv40_pm_priv *priv = (void *)ppm;
struct nv40_pm_cntr *cntr = (void *)ctr;
......@@ -55,8 +42,8 @@ nv40_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
nv40_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
nv40_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
struct nv40_pm_priv *priv = (void *)ppm;
struct nv40_pm_cntr *cntr = (void *)ctr;
......@@ -71,7 +58,7 @@ nv40_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
nv40_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
nv40_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
struct nv40_pm_priv *priv = (void *)ppm;
if (priv->sequence != ppm->sequence) {
......@@ -80,64 +67,64 @@ nv40_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
}
}
const struct nouveau_funcdom
const struct nvkm_funcdom
nv40_perfctr_func = {
.init = nv40_perfctr_init,
.read = nv40_perfctr_read,
.next = nv40_perfctr_next,
};
static const struct nouveau_specdom
static const struct nvkm_specdom
nv40_pm[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
int
nv40_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv40_pm_oclass *mclass = (void *)oclass;
struct nv40_pm_priv *priv;
int ret;
ret = nouveau_pm_create(parent, engine, oclass, &priv);
ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
ret = nvkm_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_pm_cclass;
nv_engine(priv)->sclass = nouveau_pm_sclass;
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
return 0;
}
struct nouveau_oclass *
struct nvkm_oclass *
nv40_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0x40),
.base.ofuncs = &(struct nouveau_ofuncs) {
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = _nouveau_pm_fini,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = _nvkm_pm_fini,
},
.doms = nv40_pm,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
View file @ 4d34686e
#ifndef __NVKM_PM_NV40_H__
#define __NVKM_PM_NV40_H__
#include "priv.h"
struct nv40_pm_oclass {
struct nouveau_oclass base;
const struct nouveau_specdom *doms;
struct nvkm_oclass base;
const struct nvkm_specdom *doms;
};
struct nv40_pm_priv {
struct nouveau_pm base;
struct nvkm_pm base;
u32 sequence;
};
int nv40_pm_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *data, u32 size,
struct nouveau_object **pobject);
int nv40_pm_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **pobject);
struct nv40_pm_cntr {
struct nouveau_perfctr base;
struct nvkm_perfctr base;
};
extern const struct nouveau_funcdom nv40_perfctr_func;
extern const struct nvkm_funcdom nv40_perfctr_func;
#endif
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
View file @ 4d34686e
......@@ -21,50 +21,37 @@
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
static const struct nvkm_specdom
nv50_pm[] = {
{ 0x040, (const struct nouveau_specsig[]) {
{ 0x040, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{ 0x100, (const struct nvkm_specsig[]) {
{ 0xc8, "gr_idle" },
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{ 0x100, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x020, (const struct nouveau_specsig[]) {
{ 0x020, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x040, (const struct nouveau_specsig[]) {
{ 0x040, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
struct nvkm_oclass *
nv50_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
.dtor = _nouveau_pm_dtor,
.init = _nouveau_pm_init,
.fini = _nouveau_pm_fini,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = _nvkm_pm_fini,
},
.doms = nv50_pm,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
View file @ 4d34686e
#ifndef __NVKM_PM_PRIV_H__
#define __NVKM_PM_PRIV_H__
#include <engine/pm.h>
struct nouveau_perfctr {
struct nouveau_object base;
struct nvkm_perfctr {
struct nvkm_object base;
struct list_head head;
struct nouveau_perfsig *signal[4];
struct nvkm_perfsig *signal[4];
int slot;
u32 logic_op;
u32 clk;
u32 ctr;
};
extern struct nouveau_oclass nouveau_pm_sclass[];
extern struct nvkm_oclass nvkm_pm_sclass[];
#include <core/engctx.h>
struct nouveau_perfctx {
struct nouveau_engctx base;
struct nvkm_perfctx {
struct nvkm_engctx base;
};
extern struct nouveau_oclass nouveau_pm_cclass;
extern struct nvkm_oclass nvkm_pm_cclass;
struct nouveau_specsig {
struct nvkm_specsig {
u8 signal;
const char *name;
};
struct nouveau_perfsig {
struct nvkm_perfsig {
const char *name;
};
struct nouveau_perfdom;
struct nouveau_perfctr *
nouveau_perfsig_wrap(struct nouveau_pm *, const char *,
struct nouveau_perfdom **);
struct nvkm_perfdom;
struct nvkm_perfctr *
nvkm_perfsig_wrap(struct nvkm_pm *, const char *, struct nvkm_perfdom **);
struct nouveau_specdom {
struct nvkm_specdom {
u16 signal_nr;
const struct nouveau_specsig *signal;
const struct nouveau_funcdom *func;
const struct nvkm_specsig *signal;
const struct nvkm_funcdom *func;
};
extern const struct nouveau_specdom nva3_pm_pwr[];
extern const struct nouveau_specdom nvc0_pm_pwr[];
extern const struct nouveau_specdom nve0_pm_pwr[];
extern const struct nvkm_specdom gt215_pm_pwr[];
extern const struct nvkm_specdom gf100_pm_pwr[];
extern const struct nvkm_specdom gk104_pm_pwr[];
struct nouveau_perfdom {
struct nvkm_perfdom {
struct list_head head;
struct list_head list;
const struct nouveau_funcdom *func;
const struct nvkm_funcdom *func;
char name[32];
u32 addr;
u8 quad;
u32 signal_nr;
struct nouveau_perfsig signal[];
struct nvkm_perfsig signal[];
};
struct nouveau_funcdom {
void (*init)(struct nouveau_pm *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*read)(struct nouveau_pm *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*next)(struct nouveau_pm *, struct nouveau_perfdom *);
struct nvkm_funcdom {
void (*init)(struct nvkm_pm *, struct nvkm_perfdom *,
struct nvkm_perfctr *);
void (*read)(struct nvkm_pm *, struct nvkm_perfdom *,
struct nvkm_perfctr *);
void (*next)(struct nvkm_pm *, struct nvkm_perfdom *);
};
int nouveau_perfdom_new(struct nouveau_pm *, const char *, u32,
u32, u32, u32, const struct nouveau_specdom *);
int nvkm_perfdom_new(struct nvkm_pm *, const char *, u32, u32, u32, u32,
const struct nvkm_specdom *);
#define nouveau_pm_create(p,e,o,d) \
nouveau_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_pm_dtor(p) ({ \
struct nouveau_pm *c = (p); \
_nouveau_pm_dtor(nv_object(c)); \
#define nvkm_pm_create(p,e,o,d) \
nvkm_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_pm_dtor(p) ({ \
struct nvkm_pm *c = (p); \
_nvkm_pm_dtor(nv_object(c)); \
})
#define nouveau_pm_init(p) ({ \
struct nouveau_pm *c = (p); \
_nouveau_pm_init(nv_object(c)); \
#define nvkm_pm_init(p) ({ \
struct nvkm_pm *c = (p); \
_nvkm_pm_init(nv_object(c)); \
})
#define nouveau_pm_fini(p,s) ({ \
struct nouveau_pm *c = (p); \
_nouveau_pm_fini(nv_object(c), (s)); \
#define nvkm_pm_fini(p,s) ({ \
struct nvkm_pm *c = (p); \
_nvkm_pm_fini(nv_object(c), (s)); \
})
int nouveau_pm_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_pm_dtor(struct nouveau_object *);
int _nouveau_pm_init(struct nouveau_object *);
int _nouveau_pm_fini(struct nouveau_object *, bool);
int nvkm_pm_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_pm_dtor(struct nvkm_object *);
int _nvkm_pm_init(struct nvkm_object *);
int _nvkm_pm_fini(struct nvkm_object *, bool);
#endif
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