Commit 4dd04172 authored by Jarkko Nikula's avatar Jarkko Nikula Committed by Mark Brown

ASoC: omap-mcbsp: Prepare for init time DAI format setting

Before commit 75d9ac46 ("ASoC: Allow DAI formats to be specified in the
dai_link") expectation for omap-mcbsp was that snd_soc_dai_set_fmt is to be
called first in machine hw_params callback before other CPU DAI functions.
Thus it was enough that only omap_mcbsp_dai_set_dai_fmt cleared the
mcbsp->regs structure.  [Note that this was pure convention, it's always
been OK to set things on init -- broonie]

Now this doesn't hold anymore since machine drivers can set the DAI format
only once on init time and thus mcbsp->regs may get out of sync when other
CPU DAI functions are modifying them dynamically with different values
between the calls. Therefore clear the accessed mcbsp->regs bits and
bitfields in other functions too.
Signed-off-by: default avatarJarkko Nikula <jarkko.nikula@bitmer.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 177fdd89
...@@ -317,6 +317,10 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, ...@@ -317,6 +317,10 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
return 0; return 0;
} }
regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK; format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
wpf = channels = params_channels(params); wpf = channels = params_channels(params);
if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
...@@ -369,6 +373,8 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, ...@@ -369,6 +373,8 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
framesize = wlen * channels; framesize = wlen * channels;
/* Set FS period and length in terms of bit clock periods */ /* Set FS period and length in terms of bit clock periods */
regs->srgr2 &= ~FPER(0xfff);
regs->srgr1 &= ~FWID(0xff);
switch (format) { switch (format) {
case SND_SOC_DAIFMT_I2S: case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J: case SND_SOC_DAIFMT_LEFT_J:
...@@ -505,6 +511,7 @@ static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, ...@@ -505,6 +511,7 @@ static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
return -ENODEV; return -ENODEV;
mcbsp_data->clk_div = div; mcbsp_data->clk_div = div;
regs->srgr1 &= ~CLKGDV(0xff);
regs->srgr1 |= CLKGDV(div - 1); regs->srgr1 |= CLKGDV(div - 1);
return 0; return 0;
...@@ -534,6 +541,8 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, ...@@ -534,6 +541,8 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
return -EINVAL; return -EINVAL;
mcbsp_data->in_freq = freq; mcbsp_data->in_freq = freq;
regs->srgr2 &= ~CLKSM;
regs->pcr0 &= ~SCLKME;
switch (clk_id) { switch (clk_id) {
case OMAP_MCBSP_SYSCLK_CLK: case OMAP_MCBSP_SYSCLK_CLK:
......
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