Commit 4e738e2f authored by Yinghai Lu's avatar Yinghai Lu Committed by Ingo Molnar

x86: unify mask_IO_APIC_irq

use MACRO for 32 bit too
Signed-off-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent bcd56260
...@@ -610,18 +610,7 @@ static void __init replace_pin_at_irq(unsigned int irq, ...@@ -610,18 +610,7 @@ static void __init replace_pin_at_irq(unsigned int irq,
add_pin_to_irq(irq, newapic, newpin); add_pin_to_irq(irq, newapic, newpin);
} }
#ifdef CONFIG_X86_64 #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
/*
* Synchronize the IO-APIC and the CPU by doing
* a dummy read from the IO-APIC
*/
static inline void io_apic_sync(unsigned int apic)
{
struct io_apic __iomem *io_apic = io_apic_base(apic);
readl(&io_apic->data);
}
#define __DO_ACTION(R, ACTION, FINAL) \
\ \
{ \ { \
int pin; \ int pin; \
...@@ -636,7 +625,8 @@ static inline void io_apic_sync(unsigned int apic) ...@@ -636,7 +625,8 @@ static inline void io_apic_sync(unsigned int apic)
break; \ break; \
pin = entry->pin; \ pin = entry->pin; \
reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
reg ACTION; \ reg ACTION_DISABLE; \
reg ACTION_ENABLE; \
io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \ io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
FINAL; \ FINAL; \
if (!entry->next) \ if (!entry->next) \
...@@ -645,66 +635,38 @@ static inline void io_apic_sync(unsigned int apic) ...@@ -645,66 +635,38 @@ static inline void io_apic_sync(unsigned int apic)
} \ } \
} }
#define DO_ACTION(name,R,ACTION, FINAL) \ #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
\ \
static void name##_IO_APIC_irq (unsigned int irq) \ static void name##_IO_APIC_irq (unsigned int irq) \
__DO_ACTION(R, ACTION, FINAL) __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
/* mask = 1 */
DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
/* mask = 0 */ /* mask = 0 */
DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, ) DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, )
#else #ifdef CONFIG_X86_64
/*
static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) * Synchronize the IO-APIC and the CPU by doing
* a dummy read from the IO-APIC
*/
static inline void io_apic_sync(unsigned int apic)
{ {
struct irq_cfg *cfg; struct io_apic __iomem *io_apic = io_apic_base(apic);
struct irq_pin_list *entry; readl(&io_apic->data);
unsigned int pin, reg;
cfg = irq_cfg(irq);
entry = cfg->irq_2_pin;
for (;;) {
if (!entry)
break;
pin = entry->pin;
reg = io_apic_read(entry->apic, 0x10 + pin*2);
reg &= ~disable;
reg |= enable;
io_apic_modify(entry->apic, 0x10 + pin*2, reg);
if (!entry->next)
break;
entry = entry->next;
}
} }
/* mask = 1 */ /* mask = 1 */
static void __mask_IO_APIC_irq(unsigned int irq) DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic))
{
__modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
}
/* mask = 0 */ #else
static void __unmask_IO_APIC_irq(unsigned int irq)
{ /* mask = 1 */
__modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, )
}
/* mask = 1, trigger = 0 */ /* mask = 1, trigger = 0 */
static void __mask_and_edge_IO_APIC_irq(unsigned int irq) DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, )
{
__modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
IO_APIC_REDIR_LEVEL_TRIGGER);
}
/* mask = 0, trigger = 1 */ /* mask = 0, trigger = 1 */
static void __unmask_and_level_IO_APIC_irq(unsigned int irq) DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, )
{
__modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
IO_APIC_REDIR_MASKED);
}
#endif #endif
......
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