Commit 4f6046f5 authored by Joao Pinto's avatar Joao Pinto Committed by David S. Miller

net: stmmac: mtl rx queue enabled as dcb or avb

This patch introduces the enabling of RX queues as DCB or as AVB based
on configuration.
Signed-off-by: default avatarJoao Pinto <jpinto@synopsys.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6a3a7193
...@@ -457,7 +457,7 @@ struct stmmac_ops { ...@@ -457,7 +457,7 @@ struct stmmac_ops {
/* Enable and verify that the IPC module is supported */ /* Enable and verify that the IPC module is supported */
int (*rx_ipc)(struct mac_device_info *hw); int (*rx_ipc)(struct mac_device_info *hw);
/* Enable RX Queues */ /* Enable RX Queues */
void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue); void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
/* Program RX Algorithms */ /* Program RX Algorithms */
void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg); void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
/* Program TX Algorithms */ /* Program TX Algorithms */
......
...@@ -59,13 +59,17 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu) ...@@ -59,13 +59,17 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
writel(value, ioaddr + GMAC_INT_EN); writel(value, ioaddr + GMAC_INT_EN);
} }
static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue) static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
u8 mode, u32 queue)
{ {
void __iomem *ioaddr = hw->pcsr; void __iomem *ioaddr = hw->pcsr;
u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
value &= GMAC_RX_QUEUE_CLEAR(queue); value &= GMAC_RX_QUEUE_CLEAR(queue);
value |= GMAC_RX_AV_QUEUE_ENABLE(queue); if (mode == MTL_RX_AVB)
value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
else if (mode == MTL_RX_DCB)
value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
writel(value, ioaddr + GMAC_RXQ_CTRL0); writel(value, ioaddr + GMAC_RXQ_CTRL0);
} }
......
...@@ -1256,19 +1256,14 @@ static void free_dma_desc_resources(struct stmmac_priv *priv) ...@@ -1256,19 +1256,14 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
*/ */
static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
{ {
int rx_count = priv->dma_cap.number_rx_queues; u32 rx_queues_count = priv->plat->rx_queues_to_use;
int queue = 0; int queue;
u8 mode;
/* If GMAC does not have multiple queues, then this is not necessary*/
if (rx_count == 1)
return;
/** for (queue = 0; queue < rx_queues_count; queue++) {
* If the core is synthesized with multiple rx queues / multiple mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
* dma channels, then rx queues will be disabled by default. priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
* For now only rx queue 0 is enabled. }
*/
priv->hw->mac->rx_queue_enable(priv->hw, queue);
} }
/** /**
......
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