mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling

SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably
use high speed enable bit for other purpose. So this bit
shouldn't be changed for high speed enabling for this type of
SD controller.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

drivers/mmc/host/sdhci.c

@@ -1640,7 +1640,8 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 
-	if ((ios->timing == MMC_TIMING_SD_HS ||
+	if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
+		if (ios->timing == MMC_TIMING_SD_HS ||
 		     ios->timing == MMC_TIMING_MMC_HS ||
 		     ios->timing == MMC_TIMING_MMC_HS400 ||
 		     ios->timing == MMC_TIMING_MMC_HS200 ||
@@ -1649,10 +1650,10 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		     ios->timing == MMC_TIMING_UHS_SDR104 ||
 		     ios->timing == MMC_TIMING_UHS_DDR50 ||
 		     ios->timing == MMC_TIMING_UHS_SDR25)
-	    && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
 			ctrl |= SDHCI_CTRL_HISPD;
 		else
 			ctrl &= ~SDHCI_CTRL_HISPD;
+	}
 
 	if (host->version >= SDHCI_SPEC_300) {
 		u16 clk, ctrl_2;