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Commit 5157e5c7 authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents a8588521 d8371fcd
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Showing with 1825 additions and 7 deletions
arch/arm/Kconfig
View file @ 5157e5c7
......@@ -145,6 +145,11 @@ config ARCH_S3C2410
config ARCH_OMAP
bool "TI OMAP"
config ARCH_VERSATILE_PB
bool "Versatile PB"
help
This enables support for ARM Ltd Versatile PB board.
endchoice
source "arch/arm/mach-clps711x/Kconfig"
......@@ -262,7 +267,7 @@ config ICST525
config ARM_AMBA
bool
depends on ARCH_INTEGRATOR
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB
default y
config ISA
......@@ -514,7 +519,7 @@ config CMDLINE
config LEDS
bool "Timer and CPU usage LEDs"
depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP
depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB
help
If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status.
......@@ -527,8 +532,8 @@ config LEDS
system, but the driver will do nothing.
config LEDS_TIMER
bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T)
depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP
bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB)
depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB
default y if ARCH_EBSA110
help
If you say Y here, one of the system LEDs (the green one on the
......@@ -543,7 +548,7 @@ config LEDS_TIMER
config LEDS_CPU
bool "CPU usage LED"
depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T)
depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB)
help
If you say Y here, the red LED will be used to give a good real
time indication of CPU usage, by lighting whenever the idle task
......
arch/arm/Makefile
View file @ 5157e5c7
......@@ -94,6 +94,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
machine-$(CONFIG_ARCH_ADIFCC) := adifcc
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410
machine-$(CONFIG_ARCH_VERSATILE_PB) := versatile
TEXTADDR := $(textaddr-y)
ifeq ($(incdir-y),)
......
arch/arm/boot/Makefile
View file @ 5157e5c7
......@@ -56,6 +56,9 @@ params_phys-$(CONFIG_ARCH_OMAP) := 0x10000100
initrd_phys-$(CONFIG_ARCH_OMAP) := 0x10800000
zreladdr-$(CONFIG_ARCH_S3C2410) := 0x30008000
params_phys-$(CONFIG_ARCH_S3C2410) := 0x30000100
zreladdr-$(CONFIG_ARCH_VERSATILE_PB) := 0x00008000
params_phys-$(CONFIG_ARCH_VERSATILE_PB) := 0x00000100
initrd_phys-$(CONFIG_ARCH_VERSATILE_PB) := 0x00800000
ZRELADDR := $(zreladdr-y)
ZTEXTADDR := $(ztextaddr-y)
......
arch/arm/kernel/debug.S
View file @ 5157e5c7
......@@ -550,6 +550,35 @@
1002: @ exit busyuart
.endm
#elif defined(CONFIG_ARCH_VERSATILE_PB)
#include <asm/hardware/amba_serial.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
movne \rx, #0xf1000000 @ virtual base
orr \rx, \rx, #0x001F0000
orr \rx, \rx, #0x00001000
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #UART01x_DR]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm
#else
#error Unknown architecture
#endif
......
arch/arm/kernel/entry-armv.S
View file @ 5157e5c7
......@@ -463,6 +463,37 @@ ENTRY(soft_irq_mask)
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_VERSATILE_PB)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
mov \irqnr, #0
teq \irqstat, #0
beq 1003f
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
@ clz \irqnr, \irqstat
@1003: /* EQ will be set if we reach MAXIRQNUM */
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_CLPS711X)
#include <asm/hardware/clps7111.h>
......
arch/arm/mach-versatile/Makefile 0 → 100644
View file @ 5157e5c7
#
# Makefile for the linux kernel.
#
obj-y := core.o
arch/arm/mach-versatile/core.c 0 → 100644
View file @ 5157e5c7
/*
* linux/arch/arm/mach-versatile/core.c
*
* Copyright (C) 1999 - 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/amba.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>
/*
* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
* is the (PA >> 12).
*
* Setup a VA for the Versatile Vectored Interrupt Controller.
*/
#define VA_VIC_BASE IO_ADDRESS(VERSATILE_VIC_BASE)
#define VA_SIC_BASE IO_ADDRESS(VERSATILE_SIC_BASE)
static void vic_mask_irq(unsigned int irq)
{
irq -= IRQ_VIC_START;
writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
}
static void vic_unmask_irq(unsigned int irq)
{
irq -= IRQ_VIC_START;
writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
}
static struct irqchip vic_chip = {
.ack = vic_mask_irq,
.mask = vic_mask_irq,
.unmask = vic_unmask_irq,
};
static void sic_mask_irq(unsigned int irq)
{
irq -= IRQ_SIC_START;
writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
}
static void sic_unmask_irq(unsigned int irq)
{
irq -= IRQ_SIC_START;
writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
}
static struct irqchip sic_chip = {
.ack = sic_mask_irq,
.mask = sic_mask_irq,
.unmask = sic_unmask_irq,
};
static void
sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{
unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
if (status == 0) {
do_bad_IRQ(irq, desc, regs);
return;
}
do {
irq = ffs(status) - 1;
status &= ~(1 << irq);
irq += IRQ_SIC_START;
desc = irq_desc + irq;
desc->handle(irq, desc, regs);
} while (status);
}
#if 1
#define IRQ_MMCI0A IRQ_VICSOURCE22
#define IRQ_MMCI1A IRQ_VICSOURCE23
#define IRQ_AACI IRQ_VICSOURCE24
#define IRQ_ETH IRQ_VICSOURCE25
#define PIC_MASK 0xFFD00000
#else
#define IRQ_MMCI0A IRQ_SIC_MMCI0A
#define IRQ_MMCI1A IRQ_SIC_MMCI1A
#define IRQ_AACI IRQ_SIC_AACI
#define IRQ_ETH IRQ_SIC_ETH
#define PIC_MASK 0
#endif
static void __init versatile_init_irq(void)
{
unsigned int i, value;
/* Disable all interrupts initially. */
writel(0, VA_VIC_BASE + VIC_INT_SELECT);
writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
writel(0, VA_VIC_BASE + VIC_ITCR);
writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
/*
* Make sure we clear all existing interrupts
*/
writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
for (i = 0; i < 19; i++) {
value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
}
for (i = 0; i < 16; i++) {
value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
}
writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
if (i != IRQ_VICSOURCE31) {
set_irq_chip(i, &vic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
vic_unmask_irq(IRQ_VICSOURCE31);
/* Do second interrupt controller */
writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
set_irq_chip(i, &sic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
/*
* Interrupts on secondary controller from 0 to 8 are routed to
* source 31 on PIC.
* Interrupts from 21 to 31 are routed directly to the VIC on
* the corresponding number on primary controller. This is controlled
* by setting PIC_ENABLEx.
*/
writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
}
static struct map_desc versatile_io_desc[] __initdata = {
{ IO_ADDRESS(VERSATILE_SYS_BASE), VERSATILE_SYS_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(VERSATILE_SIC_BASE), VERSATILE_SIC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(VERSATILE_VIC_BASE), VERSATILE_VIC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(VERSATILE_SCTL_BASE), VERSATILE_SCTL_BASE, SZ_4K * 9, MT_DEVICE },
#ifdef CONFIG_DEBUG_LL
{ IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K, MT_DEVICE },
#endif
#ifdef FIXME
{ PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M, MT_DEVICE },
{ PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M, MT_DEVICE },
{ PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_512K, MT_DEVICE },
{ PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K, MT_DEVICE },
#endif
};
static void __init versatile_map_io(void)
{
iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
}
#define VERSATILE_REFCOUNTER (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
/*
* This is the VersatilePB sched_clock implementation. This has
* a resolution of 41.7ns, and a maximum value of about 179s.
*/
unsigned long long sched_clock(void)
{
unsigned long long v;
v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
do_div(v, 3);
return v;
}
#define VERSATILE_FLASHCTRL (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
static int versatile_flash_init(void)
{
u32 val;
val = __raw_readl(VERSATILE_FLASHCTRL);
val &= ~VERSATILE_FLASHPROG_FLVPPEN;
__raw_writel(val, VERSATILE_FLASHCTRL);
return 0;
}
static void versatile_flash_exit(void)
{
u32 val;
val = __raw_readl(VERSATILE_FLASHCTRL);
val &= ~VERSATILE_FLASHPROG_FLVPPEN;
__raw_writel(val, VERSATILE_FLASHCTRL);
}
static void versatile_flash_set_vpp(int on)
{
u32 val;
val = __raw_readl(VERSATILE_FLASHCTRL);
if (on)
val |= VERSATILE_FLASHPROG_FLVPPEN;
else
val &= ~VERSATILE_FLASHPROG_FLVPPEN;
__raw_writel(val, VERSATILE_FLASHCTRL);
}
static struct flash_platform_data versatile_flash_data = {
.map_name = "cfi_probe",
.width = 4,
.init = versatile_flash_init,
.exit = versatile_flash_exit,
.set_vpp = versatile_flash_set_vpp,
};
static struct resource versatile_flash_resource = {
.start = VERSATILE_FLASH_BASE,
.end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device versatile_flash_device = {
.name = "armflash",
.id = 0,
.dev = {
.platform_data = &versatile_flash_data,
},
.num_resources = 1,
.resource = &versatile_flash_resource,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = VERSATILE_ETH_BASE,
.end = VERSATILE_ETH_BASE + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_ETH,
.end = IRQ_ETH,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#define VERSATILE_SYSMCI (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
static unsigned int mmc_status(struct device *dev)
{
struct amba_device *adev = container_of(dev, struct amba_device, dev);
u32 mask;
if (adev->res.start == VERSATILE_MMCI0_BASE)
mask = 1;
else
mask = 2;
return readl(VERSATILE_SYSMCI) & mask;
}
static struct mmc_platform_data mmc0_plat_data = {
.mclk = 33000000,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.status = mmc_status,
};
static struct mmc_platform_data mmc1_plat_data = {
.mclk = 33000000,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.status = mmc_status,
};
#define AMBA_DEVICE(name,busid,base,plat) \
static struct amba_device name##_device = { \
.dev = { \
.coherent_dma_mask = ~0, \
.bus_id = busid, \
.platform_data = plat, \
}, \
.res = { \
.start = VERSATILE_##base##_BASE, \
.end = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
.flags = IORESOURCE_MEM, \
}, \
.irq = base##_IRQ, \
.dma = base##_DMA, \
}
#define AACI_IRQ { IRQ_AACI, NO_IRQ }
#define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
#define MMCI0_DMA { 0x84, 0 }
#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
#define KMI0_DMA { 0, 0 }
#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
#define KMI1_DMA { 0, 0 }
#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ }
#define UART3_DMA { 0x86, 0x87 }
#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ }
#define SCI1_DMA { 0x88, 0x89 }
#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
#define MMCI1_DMA { 0x85, 0 }
/*
* These devices are connected directly to the multi-layer AHB switch
*/
#define SMC_IRQ { NO_IRQ, NO_IRQ }
#define SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
#define MPMC_DMA { 0, 0 }
#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
#define CLCD_DMA { 0, 0 }
#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
#define DMAC_DMA { 0, 0 }
/*
* These devices are connected via the core APB bridge
*/
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
#define SCTL_DMA { 0, 0 }
#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
#define WATCHDOG_DMA { 0, 0 }
#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
#define GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
#define GPIO1_DMA { 0, 0 }
#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ }
#define GPIO2_DMA { 0, 0 }
#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ }
#define GPIO3_DMA { 0, 0 }
#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
#define RTC_DMA { 0, 0 }
/*
* These devices are connected via the DMA APB bridge
*/
#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
#define SCI_DMA { 7, 6 }
#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
#define UART0_DMA { 15, 14 }
#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
#define UART1_DMA { 13, 12 }
#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
#define UART2_DMA { 11, 10 }
#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
#define SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
AMBA_DEVICE(uart3, "fpga:09", UART3, NULL);
AMBA_DEVICE(sci1, "fpga:0a", SCI1, NULL);
AMBA_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data);
/* DevChip Primecells */
AMBA_DEVICE(smc, "dev:00", SMC, NULL);
AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
AMBA_DEVICE(clcd, "dev:20", CLCD, NULL);
AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
AMBA_DEVICE(gpio3, "dev:e7", GPIO3, NULL);
AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
static struct amba_device *amba_devs[] __initdata = {
&dmac_device,
&uart0_device,
&uart1_device,
&uart2_device,
&uart3_device,
&smc_device,
&mpmc_device,
&clcd_device,
&sctl_device,
&wdog_device,
&gpio0_device,
&gpio1_device,
&gpio2_device,
&gpio3_device,
&rtc_device,
&sci0_device,
&ssp0_device,
&aaci_device,
&mmc0_device,
&kmi0_device,
&kmi1_device,
&sci1_device,
&mmc1_device,
};
#define VA_LEDS_BASE (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
static void versatile_leds_event(led_event_t ledevt)
{
unsigned long flags;
u32 val;
local_irq_save(flags);
val = readl(VA_LEDS_BASE);
switch (ledevt) {
case led_idle_start:
val = val & ~VERSATILE_SYS_LED0;
break;
case led_idle_end:
val = val | VERSATILE_SYS_LED0;
break;
case led_timer:
val = val ^ VERSATILE_SYS_LED1;
break;
case led_halted:
val = 0;
break;
default:
break;
}
writel(val, VA_LEDS_BASE);
local_irq_restore(flags);
}
static void __init versatile_init(void)
{
int i;
platform_add_device(&versatile_flash_device);
platform_add_device(&smc91x_device);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
leds_event = versatile_leds_event;
}
MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
BOOT_MEM(0x00000000, 0x101f1000, 0xf11f1000)
BOOT_PARAMS(0x00000100)
MAPIO(versatile_map_io)
INITIRQ(versatile_init_irq)
INIT_MACHINE(versatile_init)
MACHINE_END
arch/arm/mm/Kconfig
View file @ 5157e5c7
......@@ -114,8 +114,9 @@ config CPU_ARM925T
# ARM926T
config CPU_ARM926T
bool "Support ARM926T processor"
depends on ARCH_INTEGRATOR || ARCH_OMAP1610
bool "Support ARM926T processor" if ARCH_INTEGRATOR
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_OMAP1610
default y if ARCH_VERSATILE_PB
select CPU_32v5
select CPU_ABRT_EV5TJ
select CPU_COPY_V4WB
......
include/asm-arm/arch-versatile/dma.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/dma.h
*
* Copyright (C) 2003 ARM Limited.
* Copyright (C) 1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 0
#endif /* _ASM_ARCH_DMA_H */
include/asm-arm/arch-versatile/hardware.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/hardware.h
*
* This file contains the hardware definitions of the Versatile PB board.
*
* Copyright (C) 2003 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <asm/arch/platform.h>
// FIXME = PCI settings need to be fixed!!!!!
/*
* Similar to above, but for PCI addresses (memory, IO, Config and the
* V3 chip itself). WARNING: this has to mirror definitions in platform.h
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define PCIO_BASE PCI_IO_VADDR
#define PCIMEM_BASE PCI_MEMORY_VADDR
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
#endif
include/asm-arm/arch-versatile/io.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/io.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffff
#define __io(a) ((a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#endif
include/asm-arm/arch-versatile/irqs.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/irqs.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/arch/platform.h>
/*
* IRQ interrupts definitions are the same the INT definitions
* held within platform.h
*/
#define IRQ_VIC_START 0
#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
#define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx)
#define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1)
#define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3)
#define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0)
#define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1)
#define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2)
#define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3)
#define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT)
#define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT)
#define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0)
#define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1)
#define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2)
#define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT)
#define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT)
#define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT)
#define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT)
#define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT)
#define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT)
#define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21)
#define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22)
#define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23)
#define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24)
#define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25)
#define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26)
#define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27)
#define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28)
#define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29)
#define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30)
#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
#define IRQ_VIC_END (IRQ_VIC_START + 31)
#define IRQMASK_WDOGINT INTMASK_WDOGINT
#define IRQMASK_SOFTINT INTMASK_SOFTINT
#define IRQMASK_COMMRx INTMASK_COMMRx
#define IRQMASK_COMMTx INTMASK_COMMTx
#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
#define IRQMASK_RTCINT INTMASK_RTCINT
#define IRQMASK_SSPINT INTMASK_SSPINT
#define IRQMASK_UARTINT0 INTMASK_UARTINT0
#define IRQMASK_UARTINT1 INTMASK_UARTINT1
#define IRQMASK_UARTINT2 INTMASK_UARTINT2
#define IRQMASK_SCIINT INTMASK_SCIINT
#define IRQMASK_CLCDINT INTMASK_CLCDINT
#define IRQMASK_DMAINT INTMASK_DMAINT
#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
#define IRQMASK_MBXINT INTMASK_MBXINT
#define IRQMASK_GNDINT INTMASK_GNDINT
#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21
#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22
#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23
#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24
#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25
#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26
#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27
#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28
#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29
#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30
#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
/*
* FIQ interrupts definitions are the same the INT definitions.
*/
#define FIQ_WDOGINT INT_WDOGINT
#define FIQ_SOFTINT INT_SOFTINT
#define FIQ_COMMRx INT_COMMRx
#define FIQ_COMMTx INT_COMMTx
#define FIQ_TIMERINT0_1 INT_TIMERINT0_1
#define FIQ_TIMERINT2_3 INT_TIMERINT2_3
#define FIQ_GPIOINT0 INT_GPIOINT0
#define FIQ_GPIOINT1 INT_GPIOINT1
#define FIQ_GPIOINT2 INT_GPIOINT2
#define FIQ_GPIOINT3 INT_GPIOINT3
#define FIQ_RTCINT INT_RTCINT
#define FIQ_SSPINT INT_SSPINT
#define FIQ_UARTINT0 INT_UARTINT0
#define FIQ_UARTINT1 INT_UARTINT1
#define FIQ_UARTINT2 INT_UARTINT2
#define FIQ_SCIINT INT_SCIINT
#define FIQ_CLCDINT INT_CLCDINT
#define FIQ_DMAINT INT_DMAINT
#define FIQ_PWRFAILINT INT_PWRFAILINT
#define FIQ_MBXINT INT_MBXINT
#define FIQ_GNDINT INT_GNDINT
#define FIQ_VICSOURCE21 INT_VICSOURCE21
#define FIQ_VICSOURCE22 INT_VICSOURCE22
#define FIQ_VICSOURCE23 INT_VICSOURCE23
#define FIQ_VICSOURCE24 INT_VICSOURCE24
#define FIQ_VICSOURCE25 INT_VICSOURCE25
#define FIQ_VICSOURCE26 INT_VICSOURCE26
#define FIQ_VICSOURCE27 INT_VICSOURCE27
#define FIQ_VICSOURCE28 INT_VICSOURCE28
#define FIQ_VICSOURCE29 INT_VICSOURCE29
#define FIQ_VICSOURCE30 INT_VICSOURCE30
#define FIQ_VICSOURCE31 INT_VICSOURCE31
#define FIQMASK_WDOGINT INTMASK_WDOGINT
#define FIQMASK_SOFTINT INTMASK_SOFTINT
#define FIQMASK_COMMRx INTMASK_COMMRx
#define FIQMASK_COMMTx INTMASK_COMMTx
#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0
#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1
#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2
#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3
#define FIQMASK_RTCINT INTMASK_RTCINT
#define FIQMASK_SSPINT INTMASK_SSPINT
#define FIQMASK_UARTINT0 INTMASK_UARTINT0
#define FIQMASK_UARTINT1 INTMASK_UARTINT1
#define FIQMASK_UARTINT2 INTMASK_UARTINT2
#define FIQMASK_SCIINT INTMASK_SCIINT
#define FIQMASK_CLCDINT INTMASK_CLCDINT
#define FIQMASK_DMAINT INTMASK_DMAINT
#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT
#define FIQMASK_MBXINT INTMASK_MBXINT
#define FIQMASK_GNDINT INTMASK_GNDINT
#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21
#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22
#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23
#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24
#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25
#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26
#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27
#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28
#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29
#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30
#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31
/*
* Secondary interrupt controller
*/
#define IRQ_SIC_START 32
#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
#define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1)
#define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3)
#define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3)
#define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD)
#define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH)
#define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD)
#define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC)
#define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A)
#define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A)
#define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI)
#define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH)
#define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB)
#define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0)
#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
#define IRQ_SIC_END 63
#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B
#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B
#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0
#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1
#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3
#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3
#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD
#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH
#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD
#define SIC_IRQMASK_DoC SIC_INTMASK_DoC
#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A
#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A
#define SIC_IRQMASK_AACI SIC_INTMASK_AACI
#define SIC_IRQMASK_ETH SIC_INTMASK_ETH
#define SIC_IRQMASK_USB SIC_INTMASK_USB
#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0
#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1
#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2
#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3
#define NR_IRQS 64
include/asm-arm/arch-versatile/memory.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/memory.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MMU_H
#define __ASM_ARCH_MMU_H
/*
* Task size: 3GB
*/
#define TASK_SIZE (0xbf000000UL)
#define TASK_SIZE_26 (0x04000000UL)
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (0x40000000)
/*
* Page offset: 3GB
*/
#define PAGE_OFFSET (0xc0000000UL)
#define PHYS_OFFSET (0x00000000UL)
/*
* On Versatile PB, the dram is contiguous
*/
#define __virt_to_phys__is_a_macro
#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET)
#define __phys_to_virt__is_a_macro
#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus__is_a_macro
#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
#endif
include/asm-arm/arch-versatile/param.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/param.h
*
* Copyright (C) 2002 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
include/asm-arm/arch-versatile/platform.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/platform.h
*
* Copyright (c) ARM Limited 2003. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __address_h
#define __address_h 1
/*
* Memory definitions
*/
#define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
#define VERSATILE_BOOT_ROM_HI 0x30000000
#define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */
#define VERSATILE_BOOT_ROM_SIZE SZ_64M
#define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */
#define VERSATILE_SSRAM_SIZE SZ_2M
#define VERSATILE_FLASH_BASE 0x34000000
#define VERSATILE_FLASH_SIZE SZ_64M
/*
* SDRAM
*/
#define VERSATILE_SDRAM_BASE 0x00000000
/*
* Logic expansion modules
*
*/
/* ------------------------------------------------------------------------
* Versatile PB Registers
* ------------------------------------------------------------------------
*
*/
#define VERSATILE_SYS_ID_OFFSET 0x00
#define VERSATILE_SYS_SW_OFFSET 0x04
#define VERSATILE_SYS_LED_OFFSET 0x08
#define VERSATILE_SYS_OSC0_OFFSET 0x0C
#define VERSATILE_SYS_OSC1_OFFSET 0x10
#define VERSATILE_SYS_OSC2_OFFSET 0x14
#define VERSATILE_SYS_OSC3_OFFSET 0x18
#define VERSATILE_SYS_OSC4_OFFSET 0x1C
#define VERSATILE_SYS_LOCK_OFFSET 0x20
#define VERSATILE_SYS_100HZ_OFFSET 0x24
#define VERSATILE_SYS_CFGDATA1_OFFSET 0x28
#define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C
#define VERSATILE_SYS_FLAGS_OFFSET 0x30
#define VERSATILE_SYS_FLAGSSET_OFFSET 0x30
#define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34
#define VERSATILE_SYS_NVFLAGS_OFFSET 0x38
#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
#define VERSATILE_SYS_RESETCTL_OFFSET 0x40
#define VERSATILE_SYS_PICCTL_OFFSET 0x44
#define VERSATILE_SYS_MCI_OFFSET 0x48
#define VERSATILE_SYS_FLASH_OFFSET 0x4C
#define VERSATILE_SYS_CLCD_OFFSET 0x50
#define VERSATILE_SYS_CLCDSER_OFFSET 0x54
#define VERSATILE_SYS_BOOTCS_OFFSET 0x58
#define VERSATILE_SYS_24MHz_OFFSET 0x5C
#define VERSATILE_SYS_MISC_OFFSET 0x60
#define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80
#define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84
#define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88
#define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C
#define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90
#define VERSATILE_SYS_BASE 0x10000000
#define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
#define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
#define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
#define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
#define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
#define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
#define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
#define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
#define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
#define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
#define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
#define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
#define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
#define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
#define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
#define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
#define VERSATILE_SYS_PICCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET)
#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
#define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
#define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
#define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
#define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
#define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
#define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
#define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
#define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
#define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
/*
* Values for VERSATILE_SYS_RESET_CTRL
*/
#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01
#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02
#define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03
#define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04
#define VERSATILE_SYS_CTRL_RESET_POR 0x05
#define VERSATILE_SYS_CTRL_RESET_DoC 0x06
#define VERSATILE_SYS_CTRL_LED (1 << 0)
/* ------------------------------------------------------------------------
* Versatile PB control registers
* ------------------------------------------------------------------------
*/
/*
* VERSATILE_IDFIELD
*
* 31:24 = manufacturer (0x41 = ARM)
* 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
* 15:12 = FPGA (0x3 = XVC600 or XVC600E)
* 11:4 = build value
* 3:0 = revision number (0x1 = rev B (AHB))
*/
/*
* VERSATILE_SYS_LOCK
* control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
* SYS_CLD, SYS_BOOTCS
*/
#define VERSATILE_SYS_LOCK_LOCKED (1 << 16)
#define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
/*
* VERSATILE_SYS_FLASH
*/
#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
/*
* VERSATILE_INTREG
* - used to acknowledge and control MMCI and UART interrupts
*/
#define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
#define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
#define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */
/* write 1 to acknowledge and clear */
#define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
#define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
/*
* VERSATILE peripheral addresses
*/
#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
#define VERSATILE_AACI_BASE 0x10004000 /* Audio */
#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
#define VERSATILE_SCI1_BASE 0x1000A000
#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
/* 0x1000C000 - 0x1000CFFF = reserved */
#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
#define VERSATILE_USB_BASE 0x10020000 /* USB */
/* 0x10030000 - 0x100FFFFF = reserved */
#define VERSATILE_SMC_BASE 0x10100000 /* SMC */
#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
/* 0x10000000 - 0x100FFFFF */
#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
/* 0x101E9000 - reserved */
#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */
#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */
#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */
#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */
#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */
#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
#define VERSATILE_MBX_BASE 0x40000000 /* MBX */
#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
/*
* Disk on Chip
*/
#define VERSATILE_DOC_BASE 0x2C000000
#define VERSATILE_DOC_SIZE (16 << 20)
#define VERSATILE_DOC_PAGE_SIZE 512
#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
#define ERASE_UNIT_PAGES 32
#define START_PAGE 0x80
/*
* LED settings, bits [7:0]
*/
#define VERSATILE_SYS_LED0 (1 << 0)
#define VERSATILE_SYS_LED1 (1 << 1)
#define VERSATILE_SYS_LED2 (1 << 2)
#define VERSATILE_SYS_LED3 (1 << 3)
#define VERSATILE_SYS_LED4 (1 << 4)
#define VERSATILE_SYS_LED5 (1 << 5)
#define VERSATILE_SYS_LED6 (1 << 6)
#define VERSATILE_SYS_LED7 (1 << 7)
#define ALL_LEDS 0xFF
#define LED_BANK VERSATILE_SYS_LED
/*
* Control registers
*/
#define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */
#define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */
#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */
#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */
/* ------------------------------------------------------------------------
* Versatile PB Interrupt Controller - control registers
* ------------------------------------------------------------------------
*
* Offsets from interrupt controller base
*
* System Controller interrupt controller base is
*
* VERSATILE_IC_BASE
*
* Core Module interrupt controller base is
*
* VERSATILE_SYS_IC
*
*/
#define VIC_IRQ_STATUS 0
#define VIC_FIQ_STATUS 0x04
#define VIC_IRQ_RAW_STATUS 0x08
#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */
#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
#define VIC_IRQ_ENABLE_CLEAR 0x14
#define VIC_IRQ_SOFT 0x18
#define VIC_IRQ_SOFT_CLEAR 0x1C
#define VIC_PROTECT 0x20
#define VIC_VECT_ADDR 0x30
#define VIC_DEF_VECT_ADDR 0x34
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
#define VIC_ITCR 0x300 /* VIC test control register */
#define VIC_FIQ_RAW_STATUS 0x08
#define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
#define VIC_FIQ_ENABLE_CLEAR 0x14
#define VIC_FIQ_SOFT 0x18
#define VIC_FIQ_SOFT_CLEAR 0x1C
#define SIC_IRQ_STATUS 0
#define SIC_IRQ_RAW_STATUS 0x04
#define SIC_IRQ_ENABLE 0x08
#define SIC_IRQ_ENABLE_SET 0x08
#define SIC_IRQ_ENABLE_CLEAR 0x0C
#define SIC_INT_SOFT_SET 0x10
#define SIC_INT_SOFT_CLEAR 0x14
#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
#define VICVectCntl_Enable (1 << 5)
/* ------------------------------------------------------------------------
* Interrupts - bit assignment (primary)
* ------------------------------------------------------------------------
*/
#define INT_WDOGINT 0 /* Watchdog timer */
#define INT_SOFTINT 1 /* Software interrupt */
#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
#define INT_GPIOINT0 6 /* GPIO 0 */
#define INT_GPIOINT1 7 /* GPIO 1 */
#define INT_GPIOINT2 8 /* GPIO 2 */
#define INT_GPIOINT3 9 /* GPIO 3 */
#define INT_RTCINT 10 /* Real Time Clock */
#define INT_SSPINT 11 /* Synchronous Serial Port */
#define INT_UARTINT0 12 /* UART 0 on development chip */
#define INT_UARTINT1 13 /* UART 1 on development chip */
#define INT_UARTINT2 14 /* UART 2 on development chip */
#define INT_SCIINT 15 /* Smart Card Interface */
#define INT_CLCDINT 16 /* CLCD controller */
#define INT_DMAINT 17 /* DMA controller */
#define INT_PWRFAILINT 18 /* Power failure */
#define INT_MBXINT 19 /* Graphics processor */
#define INT_GNDINT 20 /* Reserved */
/* External interrupt signals from logic tiles or secondary controller */
#define INT_VICSOURCE21 21 /* Disk on Chip */
#define INT_VICSOURCE22 22 /* MCI0A */
#define INT_VICSOURCE23 23 /* MCI1A */
#define INT_VICSOURCE24 24 /* AACI */
#define INT_VICSOURCE25 25 /* Ethernet */
#define INT_VICSOURCE26 26 /* USB */
#define INT_VICSOURCE27 27 /* PCI 0 */
#define INT_VICSOURCE28 28 /* PCI 1 */
#define INT_VICSOURCE29 29 /* PCI 2 */
#define INT_VICSOURCE30 30 /* PCI 3 */
#define INT_VICSOURCE31 31 /* SIC source */
/*
* Interrupt bit positions
*
*/
#define INTMASK_WDOGINT (1 << INT_WDOGINT)
#define INTMASK_SOFTINT (1 << INT_SOFTINT)
#define INTMASK_COMMRx (1 << INT_COMMRx)
#define INTMASK_COMMTx (1 << INT_COMMTx)
#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
#define INTMASK_RTCINT (1 << INT_RTCINT)
#define INTMASK_SSPINT (1 << INT_SSPINT)
#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
#define INTMASK_SCIINT (1 << INT_SCIINT)
#define INTMASK_CLCDINT (1 << INT_CLCDINT)
#define INTMASK_DMAINT (1 << INT_DMAINT)
#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
#define INTMASK_MBXINT (1 << INT_MBXINT)
#define INTMASK_GNDINT (1 << INT_GNDINT)
#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
#define VERSATILE_SC_VALID_INT 0x003FFFFF
#define MAXIRQNUM 31
#define MAXFIQNUM 31
#define MAXSWINUM 31
/* ------------------------------------------------------------------------
* Interrupts - bit assignment (secondary)
* ------------------------------------------------------------------------
*/
#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */
#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */
#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */
#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */
#define SIC_INT_SCI3 5 /* Smart Card interface */
#define SIC_INT_UART3 6 /* UART 3 empty or data available */
#define SIC_INT_CLCD 7 /* Character LCD */
#define SIC_INT_TOUCH 8 /* Touchscreen */
#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */
/* 10:20 - reserved */
#define SIC_INT_DoC 21 /* Disk on Chip memory controller */
#define SIC_INT_MMCI0A 22 /* MMC 0A */
#define SIC_INT_MMCI1A 23 /* MMC 1A */
#define SIC_INT_AACI 24 /* Audio Codec */
#define SIC_INT_ETH 25 /* Ethernet controller */
#define SIC_INT_USB 26 /* USB controller */
#define SIC_INT_PCI0 27
#define SIC_INT_PCI1 28
#define SIC_INT_PCI2 29
#define SIC_INT_PCI3 30
#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
#define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
#define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
#define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
#define SIC_INTMASK_USB (1 << SIC_INT_USB)
#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
/*
* Application Flash
*
*/
#define FLASH_BASE VERSATILE_FLASH_BASE
#define FLASH_SIZE VERSATILE_FLASH_SIZE
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
#define FLASH_BLOCK_SIZE SZ_128K
/*
* Boot Flash
*
*/
#define EPROM_BASE VERSATILE_BOOT_ROM_HI
#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE
#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
/*
* Clean base - dummy
*
*/
#define CLEAN_BASE EPROM_BASE
/*
* System controller bit assignment
*/
#define VERSATILE_REFCLK 0
#define VERSATILE_TIMCLK 1
#define VERSATILE_TIMER1_EnSel 15
#define VERSATILE_TIMER2_EnSel 17
#define VERSATILE_TIMER3_EnSel 19
#define VERSATILE_TIMER4_EnSel 21
#define MAX_TIMER 2
#define MAX_PERIOD 699050
#define TICKS_PER_uSEC 1
/*
* These are useconds NOT ticks.
*
*/
#define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
#define mSEC_10 (mSEC_1 * 10)
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
#define VERSATILE_CSR_BASE 0x10000000
#define VERSATILE_CSR_SIZE 0x10000000
#endif
/* END */
include/asm-arm/arch-versatile/serial.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/serial.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
/*
* This assumes you have a 14.7456 MHz clock UART.
*/
#define BASE_BAUD 115200
/* UART CLK PORT IRQ FLAGS */
#define STD_SERIAL_PORT_DEFNS \
{ 0, BASE_BAUD, 0, 0, ASYNC_SKIP_TEST }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0, 0, ASYNC_SKIP_TEST }, /* ttyS1 */ \
{ 0, BASE_BAUD, 0, 0, ASYNC_SKIP_TEST }, /* ttyS2 */ \
{ 0, BASE_BAUD, 0, 0, ASYNC_SKIP_TEST }, /* ttyS3 */
#define EXTRA_SERIAL_PORT_DEFNS
#endif
include/asm-arm/arch-versatile/system.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/system.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/platform.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
unsigned int hdr_ctrl = (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_RESETCTL_OFFSET);
unsigned int val;
/*
* To reset, we hit the on-board reset register
* in the system FPGA
*/
val = __raw_readl(hdr_ctrl);
val |= VERSATILE_SYS_CTRL_RESET_CONFIGCLR;
__raw_writel(val, hdr_ctrl);
}
#endif
include/asm-arm/arch-versatile/time.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/time.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/system.h>
#include <asm/leds.h>
/*
* Where is the timer (VA)?
*/
#define TIMER0_VA_BASE IO_ADDRESS(VERSATILE_TIMER0_1_BASE)
#define TIMER1_VA_BASE (IO_ADDRESS(VERSATILE_TIMER0_1_BASE) + 0x20)
#define TIMER2_VA_BASE IO_ADDRESS(VERSATILE_TIMER2_3_BASE)
#define TIMER3_VA_BASE (IO_ADDRESS(VERSATILE_TIMER2_3_BASE) + 0x20)
#define VA_IC_BASE IO_ADDRESS(VERSATILE_VIC_BASE)
/*
* How long is the timer interval?
*/
#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
#if TIMER_INTERVAL >= 0x100000
#define TIMER_RELOAD (TIMER_INTERVAL >> 8) /* Divide by 256 */
#define TIMER_CTRL 0x88 /* Enable, Clock / 256 */
#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
#elif TIMER_INTERVAL >= 0x10000
#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
#define TIMER_CTRL 0x84 /* Enable, Clock / 16 */
#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
#else
#define TIMER_RELOAD (TIMER_INTERVAL)
#define TIMER_CTRL 0x80 /* Enable */
#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
#endif
#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
/*
* What does it look like?
*/
typedef struct TimerStruct {
unsigned long TimerLoad;
unsigned long TimerValue;
unsigned long TimerControl;
unsigned long TimerClear;
} TimerStruct_t;
extern unsigned long (*gettimeoffset)(void);
/*
* Returns number of ms since last clock interrupt. Note that interrupts
* will have been disabled by do_gettimeoffset()
*/
static unsigned long versatile_gettimeoffset(void)
{
volatile TimerStruct_t *timer0 = (TimerStruct_t *)TIMER0_VA_BASE;
unsigned long ticks1, ticks2, status;
/*
* Get the current number of ticks. Note that there is a race
* condition between us reading the timer and checking for
* an interrupt. We get around this by ensuring that the
* counter has not reloaded between our two reads.
*/
ticks2 = timer0->TimerValue & 0xffff;
do {
ticks1 = ticks2;
status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
ticks2 = timer0->TimerValue & 0xffff;
} while (ticks2 > ticks1);
/*
* Number of ticks since last interrupt.
*/
ticks1 = TIMER_RELOAD - ticks2;
/*
* Interrupt pending? If so, we've reloaded once already.
*
* FIXME: Need to check this is effectively timer 0 that expires
*/
if (status & IRQMASK_TIMERINT0_1)
ticks1 += TIMER_RELOAD;
/*
* Convert the ticks to usecs
*/
return TICKS2USECS(ticks1);
}
/*
* IRQ handler for the timer
*/
static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
// ...clear the interrupt
timer0->TimerClear = 1;
do_leds();
do_timer(regs);
do_profile(regs);
return IRQ_HANDLED;
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void __init time_init(void)
{
volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
volatile TimerStruct_t *timer3 = (volatile TimerStruct_t *)TIMER3_VA_BASE;
/*
* set clock frequency:
* VERSATILE_REFCLK is 32KHz
* VERSATILE_TIMCLK is 1MHz
*/
*(volatile unsigned int *)IO_ADDRESS(VERSATILE_SCTL_BASE) |=
((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
timer_irq.handler = versatile_timer_interrupt;
/*
* Initialise to a known state (all timers off)
*/
timer0->TimerControl = 0;
timer1->TimerControl = 0;
timer2->TimerControl = 0;
timer3->TimerControl = 0;
timer0->TimerLoad = TIMER_RELOAD;
timer0->TimerValue = TIMER_RELOAD;
timer0->TimerControl = TIMER_CTRL | 0x40 | TIMER_CTRL_IE; /* periodic + IE */
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMERINT0_1, &timer_irq);
gettimeoffset = versatile_gettimeoffset;
}
include/asm-arm/arch-versatile/timex.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/timex.h
*
* Versatile PB architecture timex specifications
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define CLOCK_TICK_RATE (50000000 / 16)
include/asm-arm/arch-versatile/uncompress.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/uncompress.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#define AMBA_UART_DR (*(volatile unsigned char *)0x101F1000)
#define AMBA_UART_LCRH (*(volatile unsigned char *)0x101F102C)
#define AMBA_UART_CR (*(volatile unsigned char *)0x101F1030)
#define AMBA_UART_FR (*(volatile unsigned char *)0x101F1018)
/*
* This does not append a newline
*/
static void puts(const char *s)
{
while (*s) {
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = *s;
if (*s == '\n') {
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = '\r';
}
s++;
}
while (AMBA_UART_FR & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
include/asm-arm/arch-versatile/vmalloc.h 0 → 100644
View file @ 5157e5c7
/*
* linux/include/asm-arm/arch-versatile/vmalloc.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
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