ASoC: pcm512x: Fix clocking calculations when not using the PLL

The rationale behind the current calculation is somewhat obscure [1]
and can yield slightly wrong dividers in certain cases, which the
machine drivers for some boards (like the HiFiBerry DAC+ Pro)
seemingly try to circumvent, by updating the rate fraction so as to
suit this calculation.

The updated calculation should correctly yield the smallest bit clock
rate that would fit the frame.

[1] http://mailman.alsa-project.org/pipermail/alsa-devel/2019-January/144219.htmlSigned-off-by: Dimitris Papavasiliou <dpapavas@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

sound/soc/codecs/pcm512x.c

@@ -929,8 +929,8 @@ static int pcm512x_set_dividers(struct snd_soc_dai *dai,
 
 	if (!pcm512x->pll_out) {
 		sck_rate = clk_get_rate(pcm512x->sclk);
-		bclk_div = params->rate_den * 64 / lrclk_div;
-		bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
+		bclk_rate = params_rate(params) * lrclk_div;
+		bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
 
 		mck_rate = sck_rate;
 	} else {