Commit 53966977 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

Merge tag 'phy-for-4.4' of...

Merge tag 'phy-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

Kishon writes:

phy: for 4.4

*) Add new PHY driver for Broadcom's cygnus PCIe PHY
*) Add USB3 PHY driver for mediatek's SoCs
*) Add VBUS regulator support for Samsung's exynos PHY
*) Misc cleanup
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parents 50bdb123 0f8669e3
Broadcom Cygnus PCIe PHY
Required properties:
- compatible: must be "brcm,cygnus-pcie-phy"
- reg: base address and length of the PCIe PHY block
- #address-cells: must be 1
- #size-cells: must be 0
Each PCIe PHY should be represented by a child node
Required properties For the child node:
- reg: the PHY ID
0 - PCIe RC 0
1 - PCIe RC 1
- #phy-cells: must be 0
Example:
pcie_phy: phy@0301d0a0 {
compatible = "brcm,cygnus-pcie-phy";
reg = <0x0301d0a0 0x14>;
pcie0_phy: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
pcie1_phy: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
/* users of the PCIe phy */
pcie0: pcie@18012000 {
...
...
phys = <&pcie0_phy>;
phy-names = "pcie-phy";
};
pcie1: pcie@18013000 {
...
...
phys = <pcie1_phy>;
phy-names = "pcie-phy";
};
mt65xx USB3.0 PHY binding
--------------------------
This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
Required properties (controller (parent) node):
- compatible : should be "mediatek,mt8173-u3phy"
- reg : offset and length of register for phy, exclude port's
register.
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- clock-names : must contain
"u3phya_ref": for reference clock of usb3.0 analog phy.
Required nodes : a sub-node is required for each port the controller
provides. Address range information including the usual
'reg' property is used inside these nodes to describe
the controller's topology.
Required properties (port (child) node):
- reg : address and length of the register set for the port.
- #phy-cells : should be 1 (See second example)
cell after port phandle is phy type from:
- PHY_TYPE_USB2
- PHY_TYPE_USB3
Example:
u3phy: usb-phy@11290000 {
compatible = "mediatek,mt8173-u3phy";
reg = <0 0x11290000 0 0x800>;
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
phy_port0: port@11290800 {
reg = <0 0x11290800 0 0x800>;
#phy-cells = <1>;
status = "okay";
};
phy_port1: port@11291000 {
reg = <0 0x11291000 0 0x800>;
#phy-cells = <1>;
status = "okay";
};
};
Specifying phy control of devices
---------------------------------
Device nodes should specify the configuration required in their "phys"
property, containing a phandle to the phy port node and a device type;
phy-names for each port are optional.
Example:
#include <dt-bindings/phy/phy.h>
usb30: usb@11270000 {
...
phys = <&phy_port0 PHY_TYPE_USB3>;
phy-names = "usb3-0";
...
};
...@@ -44,6 +44,9 @@ Required properties: ...@@ -44,6 +44,9 @@ Required properties:
- the "ref" clock is used to get the rate of the clock provided to the - the "ref" clock is used to get the rate of the clock provided to the
PHY module PHY module
Optional properties:
- vbus-supply: power-supply phandle for vbus power source
The first phandle argument in the PHY specifier identifies the PHY, its The first phandle argument in the PHY specifier identifies the PHY, its
meaning is compatible dependent. For the currently supported SoCs (Exynos 4210 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
and Exynos 4212) it is as follows: and Exynos 4212) it is as follows:
......
...@@ -1297,6 +1297,13 @@ F: arch/arm/mach-mediatek/ ...@@ -1297,6 +1297,13 @@ F: arch/arm/mach-mediatek/
N: mtk N: mtk
K: mediatek K: mediatek
ARM/Mediatek USB3 PHY DRIVER
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/phy/phy-mt65xx-usb3.c
ARM/MICREL KS8695 ARCHITECTURE ARM/MICREL KS8695 ARCHITECTURE
M: Greg Ungerer <gerg@uclinux.org> M: Greg Ungerer <gerg@uclinux.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......
...@@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA ...@@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA
help help
Support for SATA PHY on Hisilicon hix5hd2 Soc. Support for SATA PHY on Hisilicon hix5hd2 Soc.
config PHY_MT65XX_USB3
tristate "Mediatek USB3.0 PHY Driver"
depends on ARCH_MEDIATEK && OF
select GENERIC_PHY
help
Say 'Y' here to add support for Mediatek USB3.0 PHY driver
for mt65xx SoCs. it supports two usb2.0 ports and
one usb3.0 port.
config PHY_SUN4I_USB config PHY_SUN4I_USB
tristate "Allwinner sunxi SoC USB PHY driver" tristate "Allwinner sunxi SoC USB PHY driver"
depends on ARCH_SUNXI && HAS_IOMEM && OF depends on ARCH_SUNXI && HAS_IOMEM && OF
...@@ -371,4 +380,13 @@ config PHY_BRCMSTB_SATA ...@@ -371,4 +380,13 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs. Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled. Likely useful only with CONFIG_SATA_BRCMSTB enabled.
config PHY_CYGNUS_PCIE
tristate "Broadcom Cygnus PCIe PHY driver"
depends on OF && (ARCH_BCM_CYGNUS || COMPILE_TEST)
select GENERIC_PHY
default ARCH_BCM_CYGNUS
help
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
endmenu endmenu
...@@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o ...@@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
...@@ -46,3 +47,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o ...@@ -46,3 +47,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#define PCIE_CFG_OFFSET 0x00
#define PCIE1_PHY_IDDQ_SHIFT 10
#define PCIE0_PHY_IDDQ_SHIFT 2
enum cygnus_pcie_phy_id {
CYGNUS_PHY_PCIE0 = 0,
CYGNUS_PHY_PCIE1,
MAX_NUM_PHYS,
};
struct cygnus_pcie_phy_core;
/**
* struct cygnus_pcie_phy - Cygnus PCIe PHY device
* @core: pointer to the Cygnus PCIe PHY core control
* @id: internal ID to identify the Cygnus PCIe PHY
* @phy: pointer to the kernel PHY device
*/
struct cygnus_pcie_phy {
struct cygnus_pcie_phy_core *core;
enum cygnus_pcie_phy_id id;
struct phy *phy;
};
/**
* struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
* @dev: pointer to device
* @base: base register
* @lock: mutex to protect access to individual PHYs
* @phys: pointer to Cygnus PHY device
*/
struct cygnus_pcie_phy_core {
struct device *dev;
void __iomem *base;
struct mutex lock;
struct cygnus_pcie_phy phys[MAX_NUM_PHYS];
};
static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)
{
struct cygnus_pcie_phy_core *core = phy->core;
unsigned shift;
u32 val;
mutex_lock(&core->lock);
switch (phy->id) {
case CYGNUS_PHY_PCIE0:
shift = PCIE0_PHY_IDDQ_SHIFT;
break;
case CYGNUS_PHY_PCIE1:
shift = PCIE1_PHY_IDDQ_SHIFT;
break;
default:
mutex_unlock(&core->lock);
dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);
return -EINVAL;
}
if (enable) {
val = readl(core->base + PCIE_CFG_OFFSET);
val &= ~BIT(shift);
writel(val, core->base + PCIE_CFG_OFFSET);
/*
* Wait 50 ms for the PCIe Serdes to stabilize after the analog
* front end is brought up
*/
msleep(50);
} else {
val = readl(core->base + PCIE_CFG_OFFSET);
val |= BIT(shift);
writel(val, core->base + PCIE_CFG_OFFSET);
}
mutex_unlock(&core->lock);
dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,
enable ? "enabled" : "disabled");
return 0;
}
static int cygnus_pcie_phy_power_on(struct phy *p)
{
struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
return cygnus_pcie_power_config(phy, true);
}
static int cygnus_pcie_phy_power_off(struct phy *p)
{
struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
return cygnus_pcie_power_config(phy, false);
}
static struct phy_ops cygnus_pcie_phy_ops = {
.power_on = cygnus_pcie_phy_power_on,
.power_off = cygnus_pcie_phy_power_off,
.owner = THIS_MODULE,
};
static int cygnus_pcie_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node, *child;
struct cygnus_pcie_phy_core *core;
struct phy_provider *provider;
struct resource *res;
unsigned cnt = 0;
if (of_get_child_count(node) == 0) {
dev_err(dev, "PHY no child node\n");
return -ENODEV;
}
core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
if (!core)
return -ENOMEM;
core->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
core->base = devm_ioremap_resource(dev, res);
if (IS_ERR(core->base))
return PTR_ERR(core->base);
mutex_init(&core->lock);
for_each_available_child_of_node(node, child) {
unsigned int id;
struct cygnus_pcie_phy *p;
if (of_property_read_u32(child, "reg", &id)) {
dev_err(dev, "missing reg property for %s\n",
child->name);
return -EINVAL;
}
if (id >= MAX_NUM_PHYS) {
dev_err(dev, "invalid PHY id: %u\n", id);
return -EINVAL;
}
if (core->phys[id].phy) {
dev_err(dev, "duplicated PHY id: %u\n", id);
return -EINVAL;
}
p = &core->phys[id];
p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);
if (IS_ERR(p->phy)) {
dev_err(dev, "failed to create PHY\n");
return PTR_ERR(p->phy);
}
p->core = core;
p->id = id;
phy_set_drvdata(p->phy, p);
cnt++;
}
dev_set_drvdata(dev, core);
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (IS_ERR(provider)) {
dev_err(dev, "failed to register PHY provider\n");
return PTR_ERR(provider);
}
dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);
return 0;
}
static const struct of_device_id cygnus_pcie_phy_match_table[] = {
{ .compatible = "brcm,cygnus-pcie-phy" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);
static struct platform_driver cygnus_pcie_phy_driver = {
.driver = {
.name = "cygnus-pcie-phy",
.of_match_table = cygnus_pcie_phy_match_table,
},
.probe = cygnus_pcie_phy_probe,
};
module_platform_driver(cygnus_pcie_phy_driver);
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");
MODULE_LICENSE("GPL v2");
This diff is collapsed.
...@@ -27,6 +27,13 @@ static int samsung_usb2_phy_power_on(struct phy *phy) ...@@ -27,6 +27,13 @@ static int samsung_usb2_phy_power_on(struct phy *phy)
dev_dbg(drv->dev, "Request to power_on \"%s\" usb phy\n", dev_dbg(drv->dev, "Request to power_on \"%s\" usb phy\n",
inst->cfg->label); inst->cfg->label);
if (drv->vbus) {
ret = regulator_enable(drv->vbus);
if (ret)
goto err_regulator;
}
ret = clk_prepare_enable(drv->clk); ret = clk_prepare_enable(drv->clk);
if (ret) if (ret)
goto err_main_clk; goto err_main_clk;
...@@ -48,6 +55,9 @@ static int samsung_usb2_phy_power_on(struct phy *phy) ...@@ -48,6 +55,9 @@ static int samsung_usb2_phy_power_on(struct phy *phy)
err_instance_clk: err_instance_clk:
clk_disable_unprepare(drv->clk); clk_disable_unprepare(drv->clk);
err_main_clk: err_main_clk:
if (drv->vbus)
regulator_disable(drv->vbus);
err_regulator:
return ret; return ret;
} }
...@@ -55,7 +65,7 @@ static int samsung_usb2_phy_power_off(struct phy *phy) ...@@ -55,7 +65,7 @@ static int samsung_usb2_phy_power_off(struct phy *phy)
{ {
struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy); struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
struct samsung_usb2_phy_driver *drv = inst->drv; struct samsung_usb2_phy_driver *drv = inst->drv;
int ret; int ret = 0;
dev_dbg(drv->dev, "Request to power_off \"%s\" usb phy\n", dev_dbg(drv->dev, "Request to power_off \"%s\" usb phy\n",
inst->cfg->label); inst->cfg->label);
...@@ -68,7 +78,10 @@ static int samsung_usb2_phy_power_off(struct phy *phy) ...@@ -68,7 +78,10 @@ static int samsung_usb2_phy_power_off(struct phy *phy)
} }
clk_disable_unprepare(drv->ref_clk); clk_disable_unprepare(drv->ref_clk);
clk_disable_unprepare(drv->clk); clk_disable_unprepare(drv->clk);
return 0; if (drv->vbus)
ret = regulator_disable(drv->vbus);
return ret;
} }
static const struct phy_ops samsung_usb2_phy_ops = { static const struct phy_ops samsung_usb2_phy_ops = {
...@@ -203,6 +216,14 @@ static int samsung_usb2_phy_probe(struct platform_device *pdev) ...@@ -203,6 +216,14 @@ static int samsung_usb2_phy_probe(struct platform_device *pdev)
return ret; return ret;
} }
drv->vbus = devm_regulator_get(dev, "vbus");
if (IS_ERR(drv->vbus)) {
ret = PTR_ERR(drv->vbus);
if (ret == -EPROBE_DEFER)
return ret;
drv->vbus = NULL;
}
for (i = 0; i < drv->cfg->num_phys; i++) { for (i = 0; i < drv->cfg->num_phys; i++) {
char *label = drv->cfg->phys[i].label; char *label = drv->cfg->phys[i].label;
struct samsung_usb2_phy_instance *p = &drv->instances[i]; struct samsung_usb2_phy_instance *p = &drv->instances[i];
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/regulator/consumer.h>
#define KHZ 1000 #define KHZ 1000
#define MHZ (KHZ * KHZ) #define MHZ (KHZ * KHZ)
...@@ -37,6 +38,7 @@ struct samsung_usb2_phy_driver { ...@@ -37,6 +38,7 @@ struct samsung_usb2_phy_driver {
const struct samsung_usb2_phy_config *cfg; const struct samsung_usb2_phy_config *cfg;
struct clk *clk; struct clk *clk;
struct clk *ref_clk; struct clk *ref_clk;
struct regulator *vbus;
unsigned long ref_rate; unsigned long ref_rate;
u32 ref_reg_val; u32 ref_reg_val;
struct device *dev; struct device *dev;
......
...@@ -551,19 +551,15 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) ...@@ -551,19 +551,15 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (IS_ERR(data->base)) if (IS_ERR(data->base))
return PTR_ERR(data->base); return PTR_ERR(data->base);
data->id_det_gpio = devm_gpiod_get(dev, "usb0_id_det", GPIOD_IN); data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
if (IS_ERR(data->id_det_gpio)) { GPIOD_IN);
if (PTR_ERR(data->id_det_gpio) == -EPROBE_DEFER) if (IS_ERR(data->id_det_gpio))
return -EPROBE_DEFER; return PTR_ERR(data->id_det_gpio);
data->id_det_gpio = NULL;
} data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
GPIOD_IN);
data->vbus_det_gpio = devm_gpiod_get(dev, "usb0_vbus_det", GPIOD_IN); if (IS_ERR(data->vbus_det_gpio))
if (IS_ERR(data->vbus_det_gpio)) { return PTR_ERR(data->vbus_det_gpio);
if (PTR_ERR(data->vbus_det_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
data->vbus_det_gpio = NULL;
}
if (of_find_property(np, "usb0_vbus_power-supply", NULL)) { if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
data->vbus_power_supply = devm_power_supply_get_by_phandle(dev, data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
......
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