CLK: HSDK: CGU: add support for 148.5MHz clock

Add support for 148.5MHz clock for HDMI PLL Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

CLK: HSDK: CGU: add support for 148.5MHz clock
Add support for 148.5MHz clock for HDMI PLL Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
56fbeefe · Eugeniy Paltsev · Stephen Boyd · 423f042a · 56fbeefe
Commit 56fbeefe authored Mar 11, 2020 by Eugeniy Paltsev Committed by Stephen Boyd May 28, 2020
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drivers/clk/clk-hsdk-pll.c drivers/clk/clk-hsdk-pll.c +1 -0

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--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {

 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
 	{ 27000000,   0, 0,  0, 0, 1 },
+	{ 148500000,  0, 21, 3, 0, 0 },
 	{ 297000000,  0, 21, 2, 0, 0 },
 	{ 540000000,  0, 19, 1, 0, 0 },
 	{ 594000000,  0, 21, 1, 0, 0 },