drm/amd/pp: implement phm_reset_power_profile_state

mv related code out of force_dpm_level to
phm_reset_power_profile_state
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

@@ -112,10 +112,15 @@ int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level
 
 	PHM_FUNC_CHECK(hwmgr);
 
-	if (hwmgr->hwmgr_func->force_dpm_level != NULL) {
+	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
 		ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-		if (ret)
+
 	return ret;
+}
+
+int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr)
+{
+	int ret = 0;
 
 	if (hwmgr->hwmgr_func->set_power_profile_state) {
 		if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
@@ -127,8 +132,6 @@ int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level
 					hwmgr,
 					&hwmgr->compute_power_profile);
 	}
-	}
-
 	return ret;
 }
 

drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c

@@ -245,6 +245,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
 
 	phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
 	phm_force_dpm_levels(hwmgr, hwmgr->dpm_level);
+	phm_reset_power_profile_state(hwmgr);
 	return 0;
 }
 

drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

@@ -437,5 +437,6 @@ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 
 extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
+extern int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr);
 #endif /* _HARDWARE_MANAGER_H_ */