Commit 59871902 authored by Russell King's avatar Russell King

dmaengine: omap-dma: move barrier to omap_dma_start_desc()

We don't need to issue a barrier for every segment of a DMA transfer;
doing this just once per descriptor will do.
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 965aeb4d
...@@ -195,7 +195,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) ...@@ -195,7 +195,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
val = c->plat->dma_read(CCR, c->dma_ch); val = c->plat->dma_read(CCR, c->dma_ch);
val |= CCR_ENABLE; val |= CCR_ENABLE;
mb();
c->plat->dma_write(val, CCR, c->dma_ch); c->plat->dma_write(val, CCR, c->dma_ch);
} }
...@@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c) ...@@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c)
c->desc = d = to_omap_dma_desc(&vd->tx); c->desc = d = to_omap_dma_desc(&vd->tx);
c->sgidx = 0; c->sgidx = 0;
/*
* This provides the necessary barrier to ensure data held in
* DMA coherent memory is visible to the DMA engine prior to
* the transfer starting.
*/
mb();
c->plat->dma_write(d->ccr, CCR, c->dma_ch); c->plat->dma_write(d->ccr, CCR, c->dma_ch);
if (dma_omap1()) if (dma_omap1())
c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch); c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment