Commit 5bffe1b1 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King

[ARM PATCH] 2220/1: S3C2410 - regs-dsc.h fixes

Patch from Ben Dooks

The following fixes are included:

 - fix the addresses of S3C2440_DSCx (off by 4)
 - SCK0/SCK1 definitions the wrong way around
 - renable ENABLE to DISABLE

Signed-off-by: Ben Dooks 
Signed-off-by: Russell King
parent b26fed8e
...@@ -20,15 +20,15 @@ ...@@ -20,15 +20,15 @@
#ifdef CONFIG_CPU_S3C2440 #ifdef CONFIG_CPU_S3C2440
#define S3C2440_DSC0 S3C2410_GPIOREG(0xc0) #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
#define S3C2440_DSC1 S3C2410_GPIOREG(0xc4) #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
#define S3C2440_SELECT_DSC0 (0) #define S3C2440_SELECT_DSC0 (0)
#define S3C2440_SELECT_DSC1 (1<<31) #define S3C2440_SELECT_DSC1 (1<<31)
#define S3C2440_DSC_GETSHIFT(x) ((x) & 31) #define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
#define S3C2440_DSC0_ENABLE (1<<31) #define S3C2440_DSC0_DISABLE (1<<31)
#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
#define S3C2440_DSC0_ADDR_12mA (0<<8) #define S3C2440_DSC0_ADDR_12mA (0<<8)
...@@ -69,19 +69,19 @@ ...@@ -69,19 +69,19 @@
#define S3C2440_DSC0_DATA0_6mA (3<<0) #define S3C2440_DSC0_DATA0_6mA (3<<0)
#define S3C2440_DSC0_DATA0_MASK (3<<0) #define S3C2440_DSC0_DATA0_MASK (3<<0)
#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 28) #define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28)
#define S3C2440_DSC1_SCK0_12mA (0<<28) #define S3C2440_DSC1_SCK1_12mA (0<<28)
#define S3C2440_DSC1_SCK0_10mA (1<<28) #define S3C2440_DSC1_SCK1_10mA (1<<28)
#define S3C2440_DSC1_SCK0_8mA (2<<28) #define S3C2440_DSC1_SCK1_8mA (2<<28)
#define S3C2440_DSC1_SCK0_6mA (3<<28) #define S3C2440_DSC1_SCK1_6mA (3<<28)
#define S3C2440_DSC1_SCK0_MASK (3<<28) #define S3C2440_DSC1_SCK1_MASK (3<<28)
#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 26) #define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26)
#define S3C2440_DSC1_SCK1_12mA (0<<26) #define S3C2440_DSC1_SCK0_12mA (0<<26)
#define S3C2440_DSC1_SCK1_10mA (1<<26) #define S3C2440_DSC1_SCK0_10mA (1<<26)
#define S3C2440_DSC1_SCK1_8mA (2<<26) #define S3C2440_DSC1_SCK0_8mA (2<<26)
#define S3C2440_DSC1_SCK1_6mA (3<<26) #define S3C2440_DSC1_SCK0_6mA (3<<26)
#define S3C2440_DSC1_SCK1_MASK (3<<26) #define S3C2440_DSC1_SCK0_MASK (3<<26)
#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
#define S3C2440_DSC1_SCKE_10mA (0<<24) #define S3C2440_DSC1_SCKE_10mA (0<<24)
......
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