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Commit 5e5b6527 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
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MIPS: Convert R4600_V1_HIT_CACHEOP into a config option 

Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 802b8362
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Showing with 33 additions and 46 deletions
arch/mips/Kconfig
View file @ 5e5b6527
......@@ -639,6 +639,7 @@ config SGI_IP22
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R4600_V1_INDEX_ICACHEOP
select WAR_R4600_V1_HIT_CACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
......@@ -2615,6 +2616,33 @@ config MIPS_CRC_SUPPORT
config WAR_R4600_V1_INDEX_ICACHEOP
bool
# Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
#
# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
# executed if there is no other dcache activity. If the dcache is
# accessed for another instruction immeidately preceding when these
# cache instructions are executing, it is possible that the dcache
# tag match outputs used by these cache instructions will be
# incorrect. These cache instructions should be preceded by at least
# four instructions that are not any kind of load or store
# instruction.
#
# This is not allowed: lw
# nop
# nop
# nop
# cache Hit_Writeback_Invalidate_D
#
# This is allowed: lw
# nop
# nop
# nop
# nop
# cache Hit_Writeback_Invalidate_D
config WAR_R4600_V1_HIT_CACHEOP
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
......
arch/mips/include/asm/mach-cavium-octeon/war.h
View file @ 5e5b6527
......@@ -9,7 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-generic/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-ip22/war.h
View file @ 5e5b6527
......@@ -12,7 +12,6 @@
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
*/
#define R4600_V1_HIT_CACHEOP_WAR 1
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-ip27/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-ip28/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-ip30/war.h
View file @ 5e5b6527
......@@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-ip32/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-malta/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-rc32434/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-rm/war.h
View file @ 5e5b6527
......@@ -12,7 +12,6 @@
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/mach-sibyte/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
......
arch/mips/include/asm/mach-tx49xx/war.h
View file @ 5e5b6527
......@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
......
arch/mips/include/asm/war.h
View file @ 5e5b6527
......@@ -72,37 +72,6 @@
#define DADDI_WAR 0
#endif
/*
* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
*
* 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
* Hit_Invalidate_D and Create_Dirty_Excl_D should only be
* executed if there is no other dcache activity. If the dcache is
* accessed for another instruction immeidately preceding when these
* cache instructions are executing, it is possible that the dcache
* tag match outputs used by these cache instructions will be
* incorrect. These cache instructions should be preceded by at least
* four instructions that are not any kind of load or store
* instruction.
*
* This is not allowed: lw
* nop
* nop
* nop
* cache Hit_Writeback_Invalidate_D
*
* This is allowed: lw
* nop
* nop
* nop
* nop
* cache Hit_Writeback_Invalidate_D
*/
#ifndef R4600_V1_HIT_CACHEOP_WAR
#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
#endif
/*
* Writeback and invalidate the primary cache dcache before DMA.
*
......
arch/mips/mm/c-r4k.c
View file @ 5e5b6527
......@@ -132,7 +132,7 @@ struct bcache_ops *bcops = &no_sc_ops;
do { \
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
*(volatile unsigned long *)CKSEG1; \
if (R4600_V1_HIT_CACHEOP_WAR) \
if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
__asm__ __volatile__("nop;nop;nop;nop"); \
} while (0)
......
arch/mips/mm/page.c
View file @ 5e5b6527
......@@ -250,7 +250,8 @@ static inline void build_clear_pref(u32 **buf, int off)
if (cpu_has_cache_cdex_s) {
uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
} else if (cpu_has_cache_cdex_p) {
if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
cpu_is_r4600_v1_x()) {
uasm_i_nop(buf);
uasm_i_nop(buf);
uasm_i_nop(buf);
......@@ -402,7 +403,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
if (cpu_has_cache_cdex_s) {
uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
} else if (cpu_has_cache_cdex_p) {
if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
cpu_is_r4600_v1_x()) {
uasm_i_nop(buf);
uasm_i_nop(buf);
uasm_i_nop(buf);
......
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