Commit 632db906 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'arm-soc/for-5.10/soc' of https://github.com/Broadcom/stblinux into arm/soc

This pull request contains Broadcom ARM-based SoCs changes for 5.10,
please pull the following:

- Florian adds debug UART entries for the 72164 and 72165 SoCs and
  updates ARCH_BRCMSTB to select CONFIG_BCM7038_L1_IRQ which is an
  interrupt controller used with the 7211 chip family

* tag 'arm-soc/for-5.10/soc' of https://github.com/Broadcom/stblinux:
  ARM: brcmstb: Add debug UART entry for 72615
  ARM: bcm: Enable BCM7038_L1_IRQ for ARCH_BRCMSTB
  ARM: brcmstb: Add debug UART entry for 72614

Link: https://lore.kernel.org/r/20200912032153.1216354-5-f.fainelli@gmail.comSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0a29f7e4 4e5cafa8
...@@ -32,6 +32,8 @@ ...@@ -32,6 +32,8 @@
#define UARTA_7271 UARTA_7268 #define UARTA_7271 UARTA_7268
#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
#define UARTA_7216 UARTA_7278 #define UARTA_7216 UARTA_7278
#define UARTA_72164 UARTA_7278
#define UARTA_72165 UARTA_7278
#define UARTA_7364 REG_PHYS_ADDR(0x40b000) #define UARTA_7364 REG_PHYS_ADDR(0x40b000)
#define UARTA_7366 UARTA_7364 #define UARTA_7366 UARTA_7364
#define UARTA_74371 REG_PHYS_ADDR(0x406b00) #define UARTA_74371 REG_PHYS_ADDR(0x406b00)
...@@ -84,17 +86,19 @@ ARM_BE8( rev \rv, \rv ) ...@@ -84,17 +86,19 @@ ARM_BE8( rev \rv, \rv )
/* Chip specific detection starts here */ /* Chip specific detection starts here */
20: checkuart(\rp, \rv, 0x33900000, 3390) 20: checkuart(\rp, \rv, 0x33900000, 3390)
21: checkuart(\rp, \rv, 0x72160000, 7216) 21: checkuart(\rp, \rv, 0x72160000, 7216)
22: checkuart(\rp, \rv, 0x72500000, 7250) 22: checkuart(\rp, \rv, 0x07216400, 72164)
23: checkuart(\rp, \rv, 0x72550000, 7255) 23: checkuart(\rp, \rv, 0x07216500, 72165)
24: checkuart(\rp, \rv, 0x72600000, 7260) 24: checkuart(\rp, \rv, 0x72500000, 7250)
25: checkuart(\rp, \rv, 0x72680000, 7268) 25: checkuart(\rp, \rv, 0x72550000, 7255)
26: checkuart(\rp, \rv, 0x72710000, 7271) 26: checkuart(\rp, \rv, 0x72600000, 7260)
27: checkuart(\rp, \rv, 0x72780000, 7278) 27: checkuart(\rp, \rv, 0x72680000, 7268)
28: checkuart(\rp, \rv, 0x73640000, 7364) 28: checkuart(\rp, \rv, 0x72710000, 7271)
29: checkuart(\rp, \rv, 0x73660000, 7366) 29: checkuart(\rp, \rv, 0x72780000, 7278)
30: checkuart(\rp, \rv, 0x07437100, 74371) 30: checkuart(\rp, \rv, 0x73640000, 7364)
31: checkuart(\rp, \rv, 0x74390000, 7439) 31: checkuart(\rp, \rv, 0x73660000, 7366)
32: checkuart(\rp, \rv, 0x74450000, 7445) 32: checkuart(\rp, \rv, 0x07437100, 74371)
33: checkuart(\rp, \rv, 0x74390000, 7439)
34: checkuart(\rp, \rv, 0x74450000, 7445)
/* No valid UART found */ /* No valid UART found */
90: mov \rp, #0 90: mov \rp, #0
......
...@@ -208,6 +208,7 @@ config ARCH_BRCMSTB ...@@ -208,6 +208,7 @@ config ARCH_BRCMSTB
select ARM_GIC select ARM_GIC
select ARM_ERRATA_798181 if SMP select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER select HAVE_ARM_ARCH_TIMER
select BCM7038_L1_IRQ
select BRCMSTB_L2_IRQ select BRCMSTB_L2_IRQ
select BCM7120_L2_IRQ select BCM7120_L2_IRQ
select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_HOLES_MEMORYMODEL
......
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