Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
nexedi
linux
Commits
636e37aa
Commit
636e37aa
authored
Aug 20, 2015
by
Ben Skeggs
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/nouveau/mpeg: switch to device pri macros
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
276836d4
Changes
4
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
96 additions
and
84 deletions
+96
-84
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
+36
-32
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
+14
-12
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
+20
-17
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
+26
-23
No files found.
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
View file @
636e37aa
...
@@ -59,8 +59,9 @@ nv31_mpeg_object_ctor(struct nvkm_object *parent,
...
@@ -59,8 +59,9 @@ nv31_mpeg_object_ctor(struct nvkm_object *parent,
static
int
static
int
nv31_mpeg_mthd_dma
(
struct
nvkm_object
*
object
,
u32
mthd
,
void
*
arg
,
u32
len
)
nv31_mpeg_mthd_dma
(
struct
nvkm_object
*
object
,
u32
mthd
,
void
*
arg
,
u32
len
)
{
{
struct
nvkm_instmem
*
imem
=
nvkm_instmem
(
object
);
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
object
->
engine
;
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
object
->
engine
;
struct
nvkm_device
*
device
=
mpeg
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_instmem
*
imem
=
device
->
imem
;
u32
inst
=
*
(
u32
*
)
arg
<<
4
;
u32
inst
=
*
(
u32
*
)
arg
<<
4
;
u32
dma0
=
nv_ro32
(
imem
,
inst
+
0
);
u32
dma0
=
nv_ro32
(
imem
,
inst
+
0
);
u32
dma1
=
nv_ro32
(
imem
,
inst
+
4
);
u32
dma1
=
nv_ro32
(
imem
,
inst
+
4
);
...
@@ -74,22 +75,22 @@ nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
...
@@ -74,22 +75,22 @@ nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
if
(
mthd
==
0x0190
)
{
if
(
mthd
==
0x0190
)
{
/* DMA_CMD */
/* DMA_CMD */
nv
_mask
(
mpeg
,
0x00b300
,
0x00010000
,
(
dma0
&
0x00030000
)
?
0x00010000
:
0
);
nv
km_mask
(
device
,
0x00b300
,
0x00010000
,
(
dma0
&
0x00030000
)
?
0x00010000
:
0
);
nv
_wr32
(
mpeg
,
0x00b334
,
base
);
nv
km_wr32
(
device
,
0x00b334
,
base
);
nv
_wr32
(
mpeg
,
0x00b324
,
size
);
nv
km_wr32
(
device
,
0x00b324
,
size
);
}
else
}
else
if
(
mthd
==
0x01a0
)
{
if
(
mthd
==
0x01a0
)
{
/* DMA_DATA */
/* DMA_DATA */
nv
_mask
(
mpeg
,
0x00b300
,
0x00020000
,
(
dma0
&
0x00030000
)
?
0x00020000
:
0
);
nv
km_mask
(
device
,
0x00b300
,
0x00020000
,
(
dma0
&
0x00030000
)
?
0x00020000
:
0
);
nv
_wr32
(
mpeg
,
0x00b360
,
base
);
nv
km_wr32
(
device
,
0x00b360
,
base
);
nv
_wr32
(
mpeg
,
0x00b364
,
size
);
nv
km_wr32
(
device
,
0x00b364
,
size
);
}
else
{
}
else
{
/* DMA_IMAGE, VRAM only */
/* DMA_IMAGE, VRAM only */
if
(
dma0
&
0x00030000
)
if
(
dma0
&
0x00030000
)
return
-
EINVAL
;
return
-
EINVAL
;
nv
_wr32
(
mpeg
,
0x00b370
,
base
);
nv
km_wr32
(
device
,
0x00b370
,
base
);
nv
_wr32
(
mpeg
,
0x00b374
,
size
);
nv
km_wr32
(
device
,
0x00b374
,
size
);
}
}
return
0
;
return
0
;
...
@@ -182,25 +183,27 @@ nv31_mpeg_cclass = {
...
@@ -182,25 +183,27 @@ nv31_mpeg_cclass = {
void
void
nv31_mpeg_tile_prog
(
struct
nvkm_engine
*
engine
,
int
i
)
nv31_mpeg_tile_prog
(
struct
nvkm_engine
*
engine
,
int
i
)
{
{
struct
nvkm_fb_tile
*
tile
=
&
nvkm_fb
(
engine
)
->
tile
.
region
[
i
];
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
engine
;
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
engine
;
struct
nvkm_device
*
device
=
mpeg
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_fb_tile
*
tile
=
&
device
->
fb
->
tile
.
region
[
i
];
nv
_wr32
(
mpeg
,
0x00b008
+
(
i
*
0x10
),
tile
->
pitch
);
nv
km_wr32
(
device
,
0x00b008
+
(
i
*
0x10
),
tile
->
pitch
);
nv
_wr32
(
mpeg
,
0x00b004
+
(
i
*
0x10
),
tile
->
limit
);
nv
km_wr32
(
device
,
0x00b004
+
(
i
*
0x10
),
tile
->
limit
);
nv
_wr32
(
mpeg
,
0x00b000
+
(
i
*
0x10
),
tile
->
addr
);
nv
km_wr32
(
device
,
0x00b000
+
(
i
*
0x10
),
tile
->
addr
);
}
}
void
void
nv31_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
nv31_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
{
{
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_fifo
*
fifo
=
nvkm_fifo
(
subdev
);
struct
nvkm_device
*
device
=
mpeg
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_fifo
*
fifo
=
device
->
fifo
;
struct
nvkm_handle
*
handle
;
struct
nvkm_handle
*
handle
;
struct
nvkm_object
*
engctx
;
struct
nvkm_object
*
engctx
;
u32
stat
=
nv
_rd32
(
mpeg
,
0x00b100
);
u32
stat
=
nv
km_rd32
(
device
,
0x00b100
);
u32
type
=
nv
_rd32
(
mpeg
,
0x00b230
);
u32
type
=
nv
km_rd32
(
device
,
0x00b230
);
u32
mthd
=
nv
_rd32
(
mpeg
,
0x00b234
);
u32
mthd
=
nv
km_rd32
(
device
,
0x00b234
);
u32
data
=
nv
_rd32
(
mpeg
,
0x00b238
);
u32
data
=
nv
km_rd32
(
device
,
0x00b238
);
u32
show
=
stat
;
u32
show
=
stat
;
unsigned
long
flags
;
unsigned
long
flags
;
...
@@ -210,7 +213,7 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
...
@@ -210,7 +213,7 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
if
(
stat
&
0x01000000
)
{
if
(
stat
&
0x01000000
)
{
/* happens on initial binding of the object */
/* happens on initial binding of the object */
if
(
type
==
0x00000020
&&
mthd
==
0x0000
)
{
if
(
type
==
0x00000020
&&
mthd
==
0x0000
)
{
nv
_mask
(
mpeg
,
0x00b308
,
0x00000000
,
0x00000000
);
nv
km_mask
(
device
,
0x00b308
,
0x00000000
,
0x00000000
);
show
&=
~
0x01000000
;
show
&=
~
0x01000000
;
}
}
...
@@ -222,8 +225,8 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
...
@@ -222,8 +225,8 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
}
}
}
}
nv
_wr32
(
mpeg
,
0x00b100
,
stat
);
nv
km_wr32
(
device
,
0x00b100
,
stat
);
nv
_wr32
(
mpeg
,
0x00b230
,
0x00000001
);
nv
km_wr32
(
device
,
0x00b230
,
0x00000001
);
if
(
show
)
{
if
(
show
)
{
nv_error
(
mpeg
,
"ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x
\n
"
,
nv_error
(
mpeg
,
"ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x
\n
"
,
...
@@ -260,7 +263,8 @@ nv31_mpeg_init(struct nvkm_object *object)
...
@@ -260,7 +263,8 @@ nv31_mpeg_init(struct nvkm_object *object)
{
{
struct
nvkm_engine
*
engine
=
nv_engine
(
object
);
struct
nvkm_engine
*
engine
=
nv_engine
(
object
);
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
object
;
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
object
;
struct
nvkm_fb
*
fb
=
nvkm_fb
(
object
);
struct
nvkm_device
*
device
=
mpeg
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_fb
*
fb
=
device
->
fb
;
int
ret
,
i
;
int
ret
,
i
;
ret
=
nvkm_mpeg_init
(
&
mpeg
->
base
);
ret
=
nvkm_mpeg_init
(
&
mpeg
->
base
);
...
@@ -268,24 +272,24 @@ nv31_mpeg_init(struct nvkm_object *object)
...
@@ -268,24 +272,24 @@ nv31_mpeg_init(struct nvkm_object *object)
return
ret
;
return
ret
;
/* VPE init */
/* VPE init */
nv
_wr32
(
mpeg
,
0x00b0e0
,
0x00000020
);
/* nvidia: rd 0x01, wr 0x20 */
nv
km_wr32
(
device
,
0x00b0e0
,
0x00000020
);
/* nvidia: rd 0x01, wr 0x20 */
nv
_wr32
(
mpeg
,
0x00b0e8
,
0x00000020
);
/* nvidia: rd 0x01, wr 0x20 */
nv
km_wr32
(
device
,
0x00b0e8
,
0x00000020
);
/* nvidia: rd 0x01, wr 0x20 */
for
(
i
=
0
;
i
<
fb
->
tile
.
regions
;
i
++
)
for
(
i
=
0
;
i
<
fb
->
tile
.
regions
;
i
++
)
engine
->
tile_prog
(
engine
,
i
);
engine
->
tile_prog
(
engine
,
i
);
/* PMPEG init */
/* PMPEG init */
nv
_wr32
(
mpeg
,
0x00b32c
,
0x00000000
);
nv
km_wr32
(
device
,
0x00b32c
,
0x00000000
);
nv
_wr32
(
mpeg
,
0x00b314
,
0x00000100
);
nv
km_wr32
(
device
,
0x00b314
,
0x00000100
);
nv
_wr32
(
mpeg
,
0x00b220
,
0x00000031
);
nv
km_wr32
(
device
,
0x00b220
,
0x00000031
);
nv
_wr32
(
mpeg
,
0x00b300
,
0x02001ec1
);
nv
km_wr32
(
device
,
0x00b300
,
0x02001ec1
);
nv
_mask
(
mpeg
,
0x00b32c
,
0x00000001
,
0x00000001
);
nv
km_mask
(
device
,
0x00b32c
,
0x00000001
,
0x00000001
);
nv
_wr32
(
mpeg
,
0x00b100
,
0xffffffff
);
nv
km_wr32
(
device
,
0x00b100
,
0xffffffff
);
nv
_wr32
(
mpeg
,
0x00b140
,
0xffffffff
);
nv
km_wr32
(
device
,
0x00b140
,
0xffffffff
);
if
(
!
nv_wait
(
mpeg
,
0x00b200
,
0x00000001
,
0x00000000
))
{
if
(
!
nv_wait
(
mpeg
,
0x00b200
,
0x00000001
,
0x00000000
))
{
nv_error
(
mpeg
,
"timeout 0x%08x
\n
"
,
nv
_rd32
(
mpeg
,
0x00b200
));
nv_error
(
mpeg
,
"timeout 0x%08x
\n
"
,
nv
km_rd32
(
device
,
0x00b200
));
return
-
EBUSY
;
return
-
EBUSY
;
}
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
View file @
636e37aa
...
@@ -32,8 +32,9 @@
...
@@ -32,8 +32,9 @@
static
int
static
int
nv40_mpeg_mthd_dma
(
struct
nvkm_object
*
object
,
u32
mthd
,
void
*
arg
,
u32
len
)
nv40_mpeg_mthd_dma
(
struct
nvkm_object
*
object
,
u32
mthd
,
void
*
arg
,
u32
len
)
{
{
struct
nvkm_instmem
*
imem
=
nvkm_instmem
(
object
);
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
object
->
engine
;
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
object
->
engine
;
struct
nvkm_device
*
device
=
mpeg
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_instmem
*
imem
=
device
->
imem
;
u32
inst
=
*
(
u32
*
)
arg
<<
4
;
u32
inst
=
*
(
u32
*
)
arg
<<
4
;
u32
dma0
=
nv_ro32
(
imem
,
inst
+
0
);
u32
dma0
=
nv_ro32
(
imem
,
inst
+
0
);
u32
dma1
=
nv_ro32
(
imem
,
inst
+
4
);
u32
dma1
=
nv_ro32
(
imem
,
inst
+
4
);
...
@@ -47,22 +48,22 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
...
@@ -47,22 +48,22 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
if
(
mthd
==
0x0190
)
{
if
(
mthd
==
0x0190
)
{
/* DMA_CMD */
/* DMA_CMD */
nv
_mask
(
mpeg
,
0x00b300
,
0x00030000
,
(
dma0
&
0x00030000
));
nv
km_mask
(
device
,
0x00b300
,
0x00030000
,
(
dma0
&
0x00030000
));
nv
_wr32
(
mpeg
,
0x00b334
,
base
);
nv
km_wr32
(
device
,
0x00b334
,
base
);
nv
_wr32
(
mpeg
,
0x00b324
,
size
);
nv
km_wr32
(
device
,
0x00b324
,
size
);
}
else
}
else
if
(
mthd
==
0x01a0
)
{
if
(
mthd
==
0x01a0
)
{
/* DMA_DATA */
/* DMA_DATA */
nv
_mask
(
mpeg
,
0x00b300
,
0x000c0000
,
(
dma0
&
0x00030000
)
<<
2
);
nv
km_mask
(
device
,
0x00b300
,
0x000c0000
,
(
dma0
&
0x00030000
)
<<
2
);
nv
_wr32
(
mpeg
,
0x00b360
,
base
);
nv
km_wr32
(
device
,
0x00b360
,
base
);
nv
_wr32
(
mpeg
,
0x00b364
,
size
);
nv
km_wr32
(
device
,
0x00b364
,
size
);
}
else
{
}
else
{
/* DMA_IMAGE, VRAM only */
/* DMA_IMAGE, VRAM only */
if
(
dma0
&
0x00030000
)
if
(
dma0
&
0x00030000
)
return
-
EINVAL
;
return
-
EINVAL
;
nv
_wr32
(
mpeg
,
0x00b370
,
base
);
nv
km_wr32
(
device
,
0x00b370
,
base
);
nv
_wr32
(
mpeg
,
0x00b374
,
size
);
nv
km_wr32
(
device
,
0x00b374
,
size
);
}
}
return
0
;
return
0
;
...
@@ -90,14 +91,15 @@ static void
...
@@ -90,14 +91,15 @@ static void
nv40_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
nv40_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
{
{
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nv31_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_device
*
device
=
mpeg
->
base
.
engine
.
subdev
.
device
;
u32
stat
;
u32
stat
;
if
((
stat
=
nv
_rd32
(
mpeg
,
0x00b100
)))
if
((
stat
=
nv
km_rd32
(
device
,
0x00b100
)))
nv31_mpeg_intr
(
subdev
);
nv31_mpeg_intr
(
subdev
);
if
((
stat
=
nv
_rd32
(
mpeg
,
0x00b800
)))
{
if
((
stat
=
nv
km_rd32
(
device
,
0x00b800
)))
{
nv_error
(
mpeg
,
"PMSRCH 0x%08x
\n
"
,
stat
);
nv_error
(
mpeg
,
"PMSRCH 0x%08x
\n
"
,
stat
);
nv
_wr32
(
mpeg
,
0x00b800
,
stat
);
nv
km_wr32
(
device
,
0x00b800
,
stat
);
}
}
}
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
View file @
636e37aa
...
@@ -60,12 +60,13 @@ nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend)
...
@@ -60,12 +60,13 @@ nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend)
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
object
->
engine
;
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
object
->
engine
;
struct
nv44_mpeg_chan
*
chan
=
(
void
*
)
object
;
struct
nv44_mpeg_chan
*
chan
=
(
void
*
)
object
;
struct
nvkm_device
*
device
=
mpeg
->
engine
.
subdev
.
device
;
u32
inst
=
0x80000000
|
nv_gpuobj
(
chan
)
->
addr
>>
4
;
u32
inst
=
0x80000000
|
nv_gpuobj
(
chan
)
->
addr
>>
4
;
nv
_mask
(
mpeg
,
0x00b32c
,
0x00000001
,
0x00000000
);
nv
km_mask
(
device
,
0x00b32c
,
0x00000001
,
0x00000000
);
if
(
nv
_rd32
(
mpeg
,
0x00b318
)
==
inst
)
if
(
nv
km_rd32
(
device
,
0x00b318
)
==
inst
)
nv
_mask
(
mpeg
,
0x00b318
,
0x80000000
,
0x00000000
);
nv
km_mask
(
device
,
0x00b318
,
0x80000000
,
0x00000000
);
nv
_mask
(
mpeg
,
0x00b32c
,
0x00000001
,
0x00000001
);
nv
km_mask
(
device
,
0x00b32c
,
0x00000001
,
0x00000001
);
return
0
;
return
0
;
}
}
...
@@ -89,16 +90,17 @@ nv44_mpeg_cclass = {
...
@@ -89,16 +90,17 @@ nv44_mpeg_cclass = {
static
void
static
void
nv44_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
nv44_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
{
{
struct
nvkm_fifo
*
fifo
=
nvkm_fifo
(
subdev
);
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_device
*
device
=
mpeg
->
engine
.
subdev
.
device
;
struct
nvkm_fifo
*
fifo
=
device
->
fifo
;
struct
nvkm_engine
*
engine
=
nv_engine
(
subdev
);
struct
nvkm_engine
*
engine
=
nv_engine
(
subdev
);
struct
nvkm_object
*
engctx
;
struct
nvkm_object
*
engctx
;
struct
nvkm_handle
*
handle
;
struct
nvkm_handle
*
handle
;
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
u32
inst
=
nvkm_rd32
(
device
,
0x00b318
)
&
0x000fffff
;
u32
inst
=
nv_rd32
(
mpeg
,
0x00b318
)
&
0x000fffff
;
u32
stat
=
nvkm_rd32
(
device
,
0x00b100
);
u32
stat
=
nv_rd32
(
mpeg
,
0x00b100
);
u32
type
=
nvkm_rd32
(
device
,
0x00b230
);
u32
type
=
nv_rd32
(
mpeg
,
0x00b230
);
u32
mthd
=
nvkm_rd32
(
device
,
0x00b234
);
u32
mthd
=
nv_rd32
(
mpeg
,
0x00b234
);
u32
data
=
nvkm_rd32
(
device
,
0x00b238
);
u32
data
=
nv_rd32
(
mpeg
,
0x00b238
);
u32
show
=
stat
;
u32
show
=
stat
;
int
chid
;
int
chid
;
...
@@ -108,7 +110,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
...
@@ -108,7 +110,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
if
(
stat
&
0x01000000
)
{
if
(
stat
&
0x01000000
)
{
/* happens on initial binding of the object */
/* happens on initial binding of the object */
if
(
type
==
0x00000020
&&
mthd
==
0x0000
)
{
if
(
type
==
0x00000020
&&
mthd
==
0x0000
)
{
nv
_mask
(
mpeg
,
0x00b308
,
0x00000000
,
0x00000000
);
nv
km_mask
(
device
,
0x00b308
,
0x00000000
,
0x00000000
);
show
&=
~
0x01000000
;
show
&=
~
0x01000000
;
}
}
...
@@ -120,8 +122,8 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
...
@@ -120,8 +122,8 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
}
}
}
}
nv
_wr32
(
mpeg
,
0x00b100
,
stat
);
nv
km_wr32
(
device
,
0x00b100
,
stat
);
nv
_wr32
(
mpeg
,
0x00b230
,
0x00000001
);
nv
km_wr32
(
device
,
0x00b230
,
0x00000001
);
if
(
show
)
{
if
(
show
)
{
nv_error
(
mpeg
,
nv_error
(
mpeg
,
...
@@ -137,14 +139,15 @@ static void
...
@@ -137,14 +139,15 @@ static void
nv44_mpeg_me_intr
(
struct
nvkm_subdev
*
subdev
)
nv44_mpeg_me_intr
(
struct
nvkm_subdev
*
subdev
)
{
{
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_device
*
device
=
mpeg
->
engine
.
subdev
.
device
;
u32
stat
;
u32
stat
;
if
((
stat
=
nv
_rd32
(
mpeg
,
0x00b100
)))
if
((
stat
=
nv
km_rd32
(
device
,
0x00b100
)))
nv44_mpeg_intr
(
subdev
);
nv44_mpeg_intr
(
subdev
);
if
((
stat
=
nv
_rd32
(
mpeg
,
0x00b800
)))
{
if
((
stat
=
nv
km_rd32
(
device
,
0x00b800
)))
{
nv_error
(
mpeg
,
"PMSRCH 0x%08x
\n
"
,
stat
);
nv_error
(
mpeg
,
"PMSRCH 0x%08x
\n
"
,
stat
);
nv
_wr32
(
mpeg
,
0x00b800
,
stat
);
nv
km_wr32
(
device
,
0x00b800
,
stat
);
}
}
}
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
View file @
636e37aa
...
@@ -119,16 +119,17 @@ void
...
@@ -119,16 +119,17 @@ void
nv50_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
nv50_mpeg_intr
(
struct
nvkm_subdev
*
subdev
)
{
{
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
u32
stat
=
nv_rd32
(
mpeg
,
0x00b100
);
struct
nvkm_device
*
device
=
mpeg
->
engine
.
subdev
.
device
;
u32
type
=
nv_rd32
(
mpeg
,
0x00b230
);
u32
stat
=
nvkm_rd32
(
device
,
0x00b100
);
u32
mthd
=
nv_rd32
(
mpeg
,
0x00b234
);
u32
type
=
nvkm_rd32
(
device
,
0x00b230
);
u32
data
=
nv_rd32
(
mpeg
,
0x00b238
);
u32
mthd
=
nvkm_rd32
(
device
,
0x00b234
);
u32
data
=
nvkm_rd32
(
device
,
0x00b238
);
u32
show
=
stat
;
u32
show
=
stat
;
if
(
stat
&
0x01000000
)
{
if
(
stat
&
0x01000000
)
{
/* happens on initial binding of the object */
/* happens on initial binding of the object */
if
(
type
==
0x00000020
&&
mthd
==
0x0000
)
{
if
(
type
==
0x00000020
&&
mthd
==
0x0000
)
{
nv
_wr32
(
mpeg
,
0x00b308
,
0x00000100
);
nv
km_wr32
(
device
,
0x00b308
,
0x00000100
);
show
&=
~
0x01000000
;
show
&=
~
0x01000000
;
}
}
}
}
...
@@ -138,22 +139,23 @@ nv50_mpeg_intr(struct nvkm_subdev *subdev)
...
@@ -138,22 +139,23 @@ nv50_mpeg_intr(struct nvkm_subdev *subdev)
stat
,
type
,
mthd
,
data
);
stat
,
type
,
mthd
,
data
);
}
}
nv
_wr32
(
mpeg
,
0x00b100
,
stat
);
nv
km_wr32
(
device
,
0x00b100
,
stat
);
nv
_wr32
(
mpeg
,
0x00b230
,
0x00000001
);
nv
km_wr32
(
device
,
0x00b230
,
0x00000001
);
}
}
static
void
static
void
nv50_vpe_intr
(
struct
nvkm_subdev
*
subdev
)
nv50_vpe_intr
(
struct
nvkm_subdev
*
subdev
)
{
{
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
subdev
;
struct
nvkm_device
*
device
=
mpeg
->
engine
.
subdev
.
device
;
if
(
nv
_rd32
(
mpeg
,
0x00b100
))
if
(
nv
km_rd32
(
device
,
0x00b100
))
nv50_mpeg_intr
(
subdev
);
nv50_mpeg_intr
(
subdev
);
if
(
nv
_rd32
(
mpeg
,
0x00b800
))
{
if
(
nv
km_rd32
(
device
,
0x00b800
))
{
u32
stat
=
nv
_rd32
(
mpeg
,
0x00b800
);
u32
stat
=
nv
km_rd32
(
device
,
0x00b800
);
nv_info
(
mpeg
,
"PMSRCH: 0x%08x
\n
"
,
stat
);
nv_info
(
mpeg
,
"PMSRCH: 0x%08x
\n
"
,
stat
);
nv
_wr32
(
mpeg
,
0xb800
,
stat
);
nv
km_wr32
(
device
,
0xb800
,
stat
);
}
}
}
}
...
@@ -181,28 +183,29 @@ int
...
@@ -181,28 +183,29 @@ int
nv50_mpeg_init
(
struct
nvkm_object
*
object
)
nv50_mpeg_init
(
struct
nvkm_object
*
object
)
{
{
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
object
;
struct
nvkm_mpeg
*
mpeg
=
(
void
*
)
object
;
struct
nvkm_device
*
device
=
mpeg
->
engine
.
subdev
.
device
;
int
ret
;
int
ret
;
ret
=
nvkm_mpeg_init
(
mpeg
);
ret
=
nvkm_mpeg_init
(
mpeg
);
if
(
ret
)
if
(
ret
)
return
ret
;
return
ret
;
nv
_wr32
(
mpeg
,
0x00b32c
,
0x00000000
);
nv
km_wr32
(
device
,
0x00b32c
,
0x00000000
);
nv
_wr32
(
mpeg
,
0x00b314
,
0x00000100
);
nv
km_wr32
(
device
,
0x00b314
,
0x00000100
);
nv
_wr32
(
mpeg
,
0x00b0e0
,
0x0000001a
);
nv
km_wr32
(
device
,
0x00b0e0
,
0x0000001a
);
nv
_wr32
(
mpeg
,
0x00b220
,
0x00000044
);
nv
km_wr32
(
device
,
0x00b220
,
0x00000044
);
nv
_wr32
(
mpeg
,
0x00b300
,
0x00801ec1
);
nv
km_wr32
(
device
,
0x00b300
,
0x00801ec1
);
nv
_wr32
(
mpeg
,
0x00b390
,
0x00000000
);
nv
km_wr32
(
device
,
0x00b390
,
0x00000000
);
nv
_wr32
(
mpeg
,
0x00b394
,
0x00000000
);
nv
km_wr32
(
device
,
0x00b394
,
0x00000000
);
nv
_wr32
(
mpeg
,
0x00b398
,
0x00000000
);
nv
km_wr32
(
device
,
0x00b398
,
0x00000000
);
nv
_mask
(
mpeg
,
0x00b32c
,
0x00000001
,
0x00000001
);
nv
km_mask
(
device
,
0x00b32c
,
0x00000001
,
0x00000001
);
nv
_wr32
(
mpeg
,
0x00b100
,
0xffffffff
);
nv
km_wr32
(
device
,
0x00b100
,
0xffffffff
);
nv
_wr32
(
mpeg
,
0x00b140
,
0xffffffff
);
nv
km_wr32
(
device
,
0x00b140
,
0xffffffff
);
if
(
!
nv_wait
(
mpeg
,
0x00b200
,
0x00000001
,
0x00000000
))
{
if
(
!
nv_wait
(
mpeg
,
0x00b200
,
0x00000001
,
0x00000000
))
{
nv_error
(
mpeg
,
"timeout 0x%08x
\n
"
,
nv
_rd32
(
mpeg
,
0x00b200
));
nv_error
(
mpeg
,
"timeout 0x%08x
\n
"
,
nv
km_rd32
(
device
,
0x00b200
));
return
-
EBUSY
;
return
-
EBUSY
;
}
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment