Commit 64e7f91e authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher

drm/amd/display: Add DCN3 OPTC

Add support for programming the DCN3 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2a3a0d5d
......@@ -288,8 +288,16 @@ void optc1_program_timing(
if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
h_div = H_TIMING_DIV_BY2;
if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
if (optc1->opp_count == 4)
h_div = H_TIMING_DIV_BY4;
REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_DIV_MODE, h_div);
} else {
REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_DIV_BY2, h_div);
}
}
void optc1_set_vtg_params(struct timing_generator *optc,
......
......@@ -171,6 +171,15 @@ struct dcn_optc_registers {
uint32_t OPTC_DATA_FORMAT_CONTROL;
uint32_t OPTC_BYTES_PER_PIXEL;
uint32_t OPTC_WIDTH_CONTROL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
uint32_t OTG_BLANK_DATA_COLOR;
uint32_t OTG_BLANK_DATA_COLOR_EXT;
uint32_t OTG_DRR_TRIGGER_WINDOW;
uint32_t OTG_M_CONST_DTO0;
uint32_t OTG_M_CONST_DTO1;
uint32_t OTG_DRR_V_TOTAL_CHANGE;
uint32_t OTG_GLOBAL_CONTROL4;
#endif
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
......@@ -296,6 +305,8 @@ struct dcn_optc_registers {
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
......@@ -385,6 +396,13 @@ struct dcn_optc_registers {
type OTG_BLACK_COLOR_B_CB;\
type OTG_BLACK_COLOR_G_Y;\
type OTG_BLACK_COLOR_R_CR;\
type OTG_BLANK_DATA_COLOR_BLUE_CB;\
type OTG_BLANK_DATA_COLOR_GREEN_Y;\
type OTG_BLANK_DATA_COLOR_RED_CR;\
type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\
type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\
type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\
type OTG_VTOTAL_MID_REPLACING_MIN_EN;\
type OTG_TEST_PATTERN_INC0;\
type OTG_TEST_PATTERN_INC1;\
type OTG_TEST_PATTERN_VRES;\
......@@ -456,9 +474,17 @@ struct dcn_optc_registers {
type MANUAL_FLOW_CONTROL;\
type MANUAL_FLOW_CONTROL_SEL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define TG_REG_FIELD_LIST(type) \
TG_REG_FIELD_LIST_DCN1_0(type)\
type OTG_V_SYNC_MODE;\
type OTG_DRR_TRIGGER_WINDOW_START_X;\
type OTG_DRR_TRIGGER_WINDOW_END_X;\
type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\
type OTG_OUT_MUX;\
type OTG_M_CONST_DTO_PHASE;\
type OTG_M_CONST_DTO_MODULO;\
type MASTER_UPDATE_LOCK_DB_X;\
type MASTER_UPDATE_LOCK_DB_Y;\
type MASTER_UPDATE_LOCK_DB_EN;\
......@@ -469,6 +495,8 @@ struct dcn_optc_registers {
type OPTC_NUM_OF_INPUT_SEGMENT;\
type OPTC_SEG0_SRC_SEL;\
type OPTC_SEG1_SRC_SEL;\
type OPTC_SEG2_SRC_SEL;\
type OPTC_SEG3_SRC_SEL;\
type OPTC_MEM_SEL;\
type OPTC_DATA_FORMAT;\
type OPTC_DSC_MODE;\
......@@ -477,11 +505,45 @@ struct dcn_optc_registers {
type OPTC_SEGMENT_WIDTH;\
type OPTC_DWB0_SOURCE_SELECT;\
type OPTC_DWB1_SOURCE_SELECT;\
type MASTER_UPDATE_LOCK_DB_START_X;\
type MASTER_UPDATE_LOCK_DB_END_X;\
type MASTER_UPDATE_LOCK_DB_START_Y;\
type MASTER_UPDATE_LOCK_DB_END_Y;\
type DIG_UPDATE_POSITION_X;\
type DIG_UPDATE_POSITION_Y;\
type OTG_H_TIMING_DIV_MODE;\
type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
type OTG_CRC_DSC_MODE;\
type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
type OTG_CRC_DATA_FORMAT;
#else
#define TG_REG_FIELD_LIST(type) \
TG_REG_FIELD_LIST_DCN1_0(type)\
type MASTER_UPDATE_LOCK_DB_X;\
type MASTER_UPDATE_LOCK_DB_Y;\
type MASTER_UPDATE_LOCK_DB_EN;\
type GLOBAL_UPDATE_LOCK_EN;\
type DIG_UPDATE_LOCATION;\
type OTG_DSC_START_POSITION_X;\
type OTG_DSC_START_POSITION_LINE_NUM;\
type OPTC_NUM_OF_INPUT_SEGMENT;\
type OPTC_SEG0_SRC_SEL;\
type OPTC_SEG1_SRC_SEL;\
type OPTC_MEM_SEL;\
type OPTC_DATA_FORMAT;\
type OPTC_DSC_MODE;\
type OPTC_DSC_BYTES_PER_PIXEL;\
type OPTC_DSC_SLICE_WIDTH;\
type OPTC_SEGMENT_WIDTH;\
type OPTC_DWB0_SOURCE_SELECT;\
type OPTC_DWB1_SOURCE_SELECT;\
type OTG_CRC_DSC_MODE;\
type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
type OTG_CRC_DATA_FORMAT;
#endif
struct dcn_optc_shift {
......
This diff is collapsed.
This diff is collapsed.
......@@ -98,9 +98,19 @@ enum crc_selection {
INTERSECT_WINDOW_NOT_A_NOT_B,
};
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
enum otg_out_mux_dest {
OUT_MUX_DIO = 0,
};
#endif
enum h_timing_div_mode {
H_TIMING_NO_DIV,
H_TIMING_DIV_BY2,
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
H_TIMING_RESERVED,
H_TIMING_DIV_BY4,
#endif
};
struct crc_params {
......@@ -278,6 +288,15 @@ struct timing_generator_funcs {
void (*set_gsl_source_select)(struct timing_generator *optc,
int group_idx,
uint32_t gsl_ready_signal);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
void (*set_vrr_m_const)(struct timing_generator *optc,
double vtotal_avg);
void (*set_drr_trigger_window)(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);
void (*set_vtotal_change_limit)(struct timing_generator *optc,
uint32_t limit);
#endif
};
#endif
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