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Commit 6a7f6ec9 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits)
  m68knommu: fix broken setting of irq_chip and handler
  m68knommu: switch to using -mcpu= flags for ColdFire targets
  m68knommu: arch/m68knommu/Kconfig whitespace cleanup
  m68knommu: create optimal separate instruction and data cache for ColdFire
  m68knommu: support ColdFire caches that do copyback and write-through
  m68knommu: support version 2 ColdFire split cache
  m68knommu: make cache push code ColdFire generic
  m68knommu: clean up ColdFire cache control code
  m68knommu: move inclusion of ColdFire v4 cache registers
  m68knommu: merge bit definitions for version 3 ColdFire cache controller
  m68knommu: create bit definitions for the version 2 ColdFire cache controller
  m68knommu: remove empty __iounmap() it is no used
  m68knommu: remove kernel_map() code, it is not used
  m68knommu: remove do_page_fault(), it is not used
  m68knommu: use user stack pointer hardware on some ColdFire cores
  m68knommu: remove command line printing DEBUG
  m68knommu: remove fasthandler interrupt code
  m68knommu: move UART addressing to part specific includes
  m68knommu: fix clock rate value reported for ColdFire 54xx parts
  m68knommu: move ColdFire CPU names into their headers
  ...
parents c6fa63c6 4c65595e
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Showing with 727 additions and 623 deletions
arch/m68k/include/asm/cacheflush_no.h
View file @ 6a7f6ec9
......@@ -2,21 +2,22 @@
#define _M68KNOMMU_CACHEFLUSH_H
/*
* (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
* (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
*/
#include <linux/mm.h>
#include <asm/mcfsim.h>
#define flush_cache_all() __flush_cache_all()
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) __flush_cache_all()
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr) do { } while (0)
#define flush_dcache_range(start,len) __flush_cache_all()
#define flush_dcache_range(start, len) __flush_dcache_all()
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start,len) __flush_cache_all()
#define flush_icache_range(start, len) __flush_icache_all()
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_vmap(start, end) do { } while (0)
......@@ -27,66 +28,52 @@
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
void mcf_cache_push(void);
static inline void __flush_cache_all(void)
{
#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
/*
* Use cpushl to push and invalidate all cache lines.
* Gas doesn't seem to know how to generate the ColdFire
* cpushl instruction... Oh well, bit stuff it for now.
*/
__asm__ __volatile__ (
"nop\n\t"
"clrl %%d0\n\t"
"1:\n\t"
"movel %%d0,%%a0\n\t"
"2:\n\t"
".word 0xf468\n\t"
"addl #0x10,%%a0\n\t"
"cmpl #0x00000800,%%a0\n\t"
"blt 2b\n\t"
"addql #1,%%d0\n\t"
"cmpil #4,%%d0\n\t"
"bne 1b\n\t"
"movel #0xb6088500,%%d0\n\t"
"movec %%d0,%%CACR\n\t"
: : : "d0", "a0" );
#endif /* CONFIG_M5407 */
#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
__asm__ __volatile__ (
"movel #0x81400100, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M523x || CONFIG_M527x */
#if defined(CONFIG_M528x)
__asm__ __volatile__ (
"movel #0x81000200, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M528x */
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
#ifdef CACHE_PUSH
mcf_cache_push();
#endif
#ifdef CACHE_INVALIDATE
__asm__ __volatile__ (
"movel #0x81000100, %%d0\n\t"
"movel %0, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
#ifdef CONFIG_M5249
: : "i" (CACHE_INVALIDATE) : "d0" );
#endif
}
/*
* Some ColdFire parts implement separate instruction and data caches,
* on those we should just flush the appropriate cache. If we don't need
* to do any specific flushing then this will be optimized away.
*/
static inline void __flush_icache_all(void)
{
#ifdef CACHE_INVALIDATEI
__asm__ __volatile__ (
"movel #0xa1000200, %%d0\n\t"
"movel %0, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M532x
: : "i" (CACHE_INVALIDATEI) : "d0" );
#endif
}
static inline void __flush_dcache_all(void)
{
#ifdef CACHE_PUSH
mcf_cache_push();
#endif
#ifdef CACHE_INVALIDATED
__asm__ __volatile__ (
"movel #0x81000200, %%d0\n\t"
"movel %0, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M532x */
: : "i" (CACHE_INVALIDATED) : "d0" );
#else
/* Flush the wrtite buffer */
__asm__ __volatile__ ( "nop" );
#endif
}
#endif /* _M68KNOMMU_CACHEFLUSH_H */
arch/m68k/include/asm/coldfire.h
View file @ 6a7f6ec9
......@@ -32,7 +32,7 @@
*/
#define MCF_MBAR 0x10000000
#define MCF_MBAR2 0x80000000
#if defined(CONFIG_M548x)
#if defined(CONFIG_M54xx)
#define MCF_IPSBAR MCF_MBAR
#elif defined(CONFIG_M520x)
#define MCF_IPSBAR 0xFC000000
......
arch/m68k/include/asm/entry_no.h
View file @ 6a7f6ec9
......@@ -42,12 +42,16 @@
*/
#ifdef CONFIG_COLDFIRE
#ifdef CONFIG_COLDFIRE_SW_A7
/*
* This is made a little more tricky on the ColdFire. There is no
* separate kernel and user stack pointers. Need to artificially
* This is made a little more tricky on older ColdFires. There is no
* separate supervisor and user stack pointers. Need to artificially
* construct a usp in software... When doing this we need to disable
* interrupts, otherwise bad things could happen.
* interrupts, otherwise bad things will happen.
*/
.globl sw_usp
.globl sw_ksp
.macro SAVE_ALL
move #0x2700,%sr /* disable intrs */
btst #5,%sp@(2) /* from user? */
......@@ -74,9 +78,7 @@
7:
.endm
.macro RESTORE_ALL
btst #5,%sp@(PT_SR) /* going user? */
bnes 8f /* no, skip */
.macro RESTORE_USER
move #0x2700,%sr /* disable intrs */
movel sw_usp,%a0 /* get usp */
movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
......@@ -91,19 +93,22 @@
subql #8,sw_usp /* set exception */
movel sw_usp,%sp /* restore usp */
rte
8:
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
rte
.endm
.macro RDUSP
movel sw_usp,%a2
.endm
.macro WRUSP
movel %a0,sw_usp
.endm
#else /* !CONFIG_COLDFIRE_SW_A7 */
/*
* Quick exception save, use current stack only.
* Modern ColdFire parts have separate supervisor and user stack
* pointers. Simple load and restore macros for this case.
*/
.macro SAVE_LOCAL
.macro SAVE_ALL
move #0x2700,%sr /* disable intrs */
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
......@@ -112,7 +117,7 @@
moveml %d1-%d5/%a0-%a2,%sp@
.endm
.macro RESTORE_LOCAL
.macro RESTORE_USER
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
......@@ -121,6 +126,18 @@
rte
.endm
.macro RDUSP
/*move %usp,%a2*/
.word 0x4e6a
.endm
.macro WRUSP
/*move %a0,%usp*/
.word 0x4e60
.endm
#endif /* !CONFIG_COLDFIRE_SW_A7 */
.macro SAVE_SWITCH_STACK
lea %sp@(-24),%sp /* 6 regs */
moveml %a3-%a6/%d6-%d7,%sp@
......@@ -131,14 +148,6 @@
lea %sp@(24),%sp /* 6 regs */
.endm
/*
* Software copy of the user and kernel stack pointers... Ugh...
* Need these to get around ColdFire not having separate kernel
* and user stack pointers.
*/
.globl sw_usp
.globl sw_ksp
#else /* !CONFIG_COLDFIRE */
/*
......@@ -167,6 +176,6 @@
moveml %sp@+,%a3-%a6/%d6-%d7
.endm
#endif /* !CONFIG_COLDFIRE */
#endif /* !COLDFIRE_SW_A7 */
#endif /* __ASSEMBLY__ */
#endif /* __M68KNOMMU_ENTRY_H */
arch/m68k/include/asm/gpio.h
View file @ 6a7f6ec9
......@@ -37,7 +37,7 @@
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M548x)
defined(CONFIG_M532x) || defined(CONFIG_M54xx)
/* These parts have GPIO organized by 8 bit ports */
......
arch/m68k/include/asm/io_no.h
View file @ 6a7f6ec9
......@@ -145,7 +145,6 @@ static inline void io_insl(unsigned int addr, void *buf, int len)
#define IOMAP_WRITETHROUGH 3
extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
static inline void *ioremap(unsigned long physaddr, unsigned long size)
{
......
arch/m68k/include/asm/m5206sim.h
View file @ 6a7f6ec9
......@@ -12,6 +12,10 @@
#define m5206sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5206)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5206 SIM register set addresses.
......@@ -88,6 +92,14 @@
#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
#endif
/*
* Define system peripheral IRQ usage.
*/
......
arch/m68k/include/asm/m520xsim.h
View file @ 6a7f6ec9
......@@ -11,6 +11,11 @@
#define m520xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 520x SIM register set addresses.
*/
......@@ -54,6 +59,9 @@
#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
/*
* EPORT and GPIO registers.
*/
#define MCFEPORT_EPDDR 0xFC088002
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005
......@@ -97,6 +105,7 @@
#define MCFGPIO_PCLRR_UART 0xFC0A402A
#define MCFGPIO_PCLRR_FECH 0xFC0A402B
#define MCFGPIO_PCLRR_FECL 0xFC0A402C
/*
* Generic GPIO support
*/
......@@ -109,7 +118,6 @@
#define MCFGPIO_PIN_MAX 80
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/****************************************************************************/
#define MCF_GPIO_PAR_UART (0xA4036)
#define MCF_GPIO_PAR_FECI2C (0xA4033)
......@@ -125,6 +133,13 @@
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
/*
* UART module.
*/
#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
/*
* Reset Controll Unit.
*/
......
arch/m68k/include/asm/m523xsim.h
View file @ 6a7f6ec9
......@@ -11,6 +11,10 @@
#define m523xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m523x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 523x SIM register set addresses.
......@@ -50,6 +54,13 @@
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* UART module.
*/
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
......
arch/m68k/include/asm/m5249sim.h
View file @ 6a7f6ec9
......@@ -11,6 +11,11 @@
#define m5249sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5249)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5249 SIM register set addresses.
*/
......@@ -56,6 +61,11 @@
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/*
* UART module.
*/
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
/*
* Some symbol defines for the above...
......
arch/m68k/include/asm/m5272sim.h
View file @ 6a7f6ec9
......@@ -12,6 +12,11 @@
#define m5272sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5272)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5272 SIM register set addresses.
*/
......@@ -62,6 +67,9 @@
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
......
arch/m68k/include/asm/m527xsim.h
View file @ 6a7f6ec9
......@@ -11,6 +11,10 @@
#define m527xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m527x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5270/5271 SIM register set addresses.
......@@ -55,6 +59,12 @@
#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
#endif
/*
* UART module.
*/
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#ifdef CONFIG_M5271
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
......
arch/m68k/include/asm/m528xsim.h
View file @ 6a7f6ec9
......@@ -11,6 +11,10 @@
#define m528xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5280/5282 SIM register set addresses.
......@@ -41,6 +45,13 @@
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
/*
* UART module.
*/
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
/*
* GPIO registers
*/
......
arch/m68k/include/asm/m52xxacr.h 0 → 100644
View file @ 6a7f6ec9
/****************************************************************************/
/*
* m52xxacr.h -- ColdFire version 2 core cache support
*
* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m52xxacr_h
#define m52xxacr_h
/****************************************************************************/
/*
* All varients of the ColdFire using version 2 cores have a similar
* cache setup. Although not absolutely identical the cache register
* definitions are compatible for all of them. Mostly they support a
* configurable cache memory that can be instruction only, data only,
* or split instruction and data. The exception is the very old version 2
* core based parts, like the 5206(e), 5249 and 5272, which are instruction
* cache only. Cache size varies from 2k up to 16k.
*/
/*
* Define the Cache Control register flags.
*/
#define CACR_CENB 0x80000000 /* Enable cache */
#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
#define CACR_CINV 0x01000000 /* Invalidate cache */
#define CACR_DISI 0x00800000 /* Disable instruction cache */
#define CACR_DISD 0x00400000 /* Disable data cache */
#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
#define CACR_INVD 0x00100000 /* Invalidate data cache */
#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
#define CACR_DCM 0x00000200 /* Default cache mode */
#define CACR_DBWE 0x00000100 /* Buffered write enable */
#define CACR_DWP 0x00000020 /* Write protection */
#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
/*
* Define the Access Control register flags.
*/
#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
#define ACR_ENABLE 0x00008000 /* Enable this ACR */
#define ACR_USER 0x00000000 /* Allow only user accesses */
#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
#define ACR_ANY 0x00004000 /* Allow any access type */
#define ACR_CENB 0x00000000 /* Caching of region enabled */
#define ACR_CDIS 0x00000040 /* Caching of region disabled */
#define ACR_BWE 0x00000020 /* Write buffer enabled */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
/*
* Set the cache controller settings we will use. On the cores that support
* a split cache configuration we allow all the combinations at Kconfig
* time. For those cores that only have an instruction cache we just set
* that as on.
*/
#if defined(CONFIG_CACHE_I)
#define CACHE_TYPE (CACR_DISD + CACR_EUSP)
#define CACHE_INVTYPEI 0
#elif defined(CONFIG_CACHE_D)
#define CACHE_TYPE (CACR_DISI + CACR_EUSP)
#define CACHE_INVTYPED 0
#elif defined(CONFIG_CACHE_BOTH)
#define CACHE_TYPE CACR_EUSP
#define CACHE_INVTYPEI CACR_INVI
#define CACHE_INVTYPED CACR_INVD
#else
/* This is the instruction cache only devices (no split cache, no eusp) */
#define CACHE_TYPE 0
#define CACHE_INVTYPEI 0
#endif
#define CACHE_INIT (CACR_CINV + CACHE_TYPE)
#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
#if defined(CACHE_INVTYPEI)
#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
#endif
#if defined(CACHE_INVTYPED)
#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
#endif
#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
(0x000f0000) + \
(ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
#define ACR1_MODE 0
/****************************************************************************/
#endif /* m52xxsim_h */
arch/m68k/include/asm/m5307sim.h
View file @ 6a7f6ec9
......@@ -14,6 +14,11 @@
#define m5307sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5307)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m53xxacr.h>
/*
* Define the 5307 SIM register set addresses.
*/
......@@ -93,6 +98,17 @@
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
* UART module.
*/
#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
/*
* Generic GPIO support
*/
......@@ -146,32 +162,5 @@
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Define the Cache register flags.
*/
#define CACR_EC (1<<31)
#define CACR_ESB (1<<29)
#define CACR_DPI (1<<28)
#define CACR_HLCK (1<<27)
#define CACR_CINVA (1<<24)
#define CACR_DNFB (1<<10)
#define CACR_DCM_WTHRU (0<<8)
#define CACR_DCM_WBACK (1<<8)
#define CACR_DCM_OFF_PRE (2<<8)
#define CACR_DCM_OFF_IMP (3<<8)
#define CACR_DW (1<<5)
#define ACR_BASE_POS 24
#define ACR_MASK_POS 16
#define ACR_ENABLE (1<<15)
#define ACR_USER (0<<13)
#define ACR_SUPER (1<<13)
#define ACR_ANY (2<<13)
#define ACR_CM_WTHRU (0<<5)
#define ACR_CM_WBACK (1<<5)
#define ACR_CM_OFF_PRE (2<<5)
#define ACR_CM_OFF_IMP (3<<5)
#define ACR_WPROTECT (1<<2)
/****************************************************************************/
#endif /* m5307sim_h */
arch/m68k/include/asm/m532xsim.h
View file @ 6a7f6ec9
......@@ -9,6 +9,11 @@
#define m532xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m532x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m53xxacr.h>
#define MCF_REG32(x) (*(volatile unsigned long *)(x))
#define MCF_REG16(x) (*(volatile unsigned short *)(x))
#define MCF_REG08(x) (*(volatile unsigned char *)(x))
......@@ -74,31 +79,11 @@
#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
/*
* Define the Cache register flags.
* UART module.
*/
#define CACR_EC (1<<31)
#define CACR_ESB (1<<29)
#define CACR_DPI (1<<28)
#define CACR_HLCK (1<<27)
#define CACR_CINVA (1<<24)
#define CACR_DNFB (1<<10)
#define CACR_DCM_WTHRU (0<<8)
#define CACR_DCM_WBACK (1<<8)
#define CACR_DCM_OFF_PRE (2<<8)
#define CACR_DCM_OFF_IMP (3<<8)
#define CACR_DW (1<<5)
#define ACR_BASE_POS 24
#define ACR_MASK_POS 16
#define ACR_ENABLE (1<<15)
#define ACR_USER (0<<13)
#define ACR_SUPER (1<<13)
#define ACR_ANY (2<<13)
#define ACR_CM_WTHRU (0<<5)
#define ACR_CM_WBACK (1<<5)
#define ACR_CM_OFF_PRE (2<<5)
#define ACR_CM_OFF_IMP (3<<5)
#define ACR_WPROTECT (1<<2)
#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
/*********************************************************************
*
......
arch/m68k/include/asm/m53xxacr.h 0 → 100644
View file @ 6a7f6ec9
/****************************************************************************/
/*
* m53xxacr.h -- ColdFire version 3 core cache support
*
* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m53xxacr_h
#define m53xxacr_h
/****************************************************************************/
/*
* All varients of the ColdFire using version 3 cores have a similar
* cache setup. They have a unified instruction and data cache, with
* configurable write-through or copy-back operation.
*/
/*
* Define the Cache Control register flags.
*/
#define CACR_EC 0x80000000 /* Enable cache */
#define CACR_ESB 0x20000000 /* Enable store buffer */
#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_HLCK 0x08000000 /* Half cache lock mode */
#define CACR_CINVA 0x01000000 /* Invalidate cache */
#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
#define CACR_WPROTECT 0x00000020 /* Write protect*/
#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
/*
* Define the Access Control register flags.
*/
#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
#define ACR_ENABLE 0x00008000 /* Enable this ACR */
#define ACR_USER 0x00000000 /* Allow only user accesses */
#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
#define ACR_ANY 0x00004000 /* Allow any access type */
#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
/*
* Define the cache type and arrangement (needed for pushes).
*/
#if defined(CONFIG_M5307)
#define CACHE_SIZE 0x2000 /* 8k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#elif defined(CONFIG_M532x)
#define CACHE_SIZE 0x4000 /* 32k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#endif
#define CACHE_LINE_SIZE 16 /* 16 byte line size */
#define CACHE_WAYS 4 /* 4 ways - set associative */
/*
* Set the cache controller settings we will use. This default in the
* CACR is cache inhibited, we use the ACR register to set cacheing
* enabled on the regions we want (eg RAM).
*/
#if defined(CONFIG_CACHE_COPYBACK)
#define CACHE_TYPE ACR_CM_CB
#define CACHE_PUSH
#else
#define CACHE_TYPE ACR_CM_WT
#endif
#ifdef CONFIG_COLDFIRE_SW_A7
#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
#else
#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
#endif
/*
* Unified cache means we will never need to flush for coherency of
* instruction fetch. We will need to flush to maintain memory/DMA
* coherency though in all cases. And for copyback caches we will need
* to push cached data as well.
*/
#define CACHE_INIT CACR_CINVA
#define CACHE_INVALIDATE CACR_CINVA
#define CACHE_INVALIDATED CACR_CINVA
#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
(0x000f0000) + \
(ACR_ENABLE + ACR_ANY + CACHE_TYPE))
#define ACR1_MODE 0
/****************************************************************************/
#endif /* m53xxsim_h */
arch/m68k/include/asm/m5407sim.h
View file @ 6a7f6ec9
......@@ -14,6 +14,11 @@
#define m5407sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5407)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m54xxacr.h>
/*
* Define the 5407 SIM register set addresses.
*/
......@@ -73,6 +78,9 @@
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
......@@ -117,39 +125,5 @@
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Define the Cache register flags.
*/
#define CACR_DEC 0x80000000 /* Enable data cache */
#define CACR_DWP 0x40000000 /* Data write protection */
#define CACR_DESB 0x20000000 /* Enable data store buffer */
#define CACR_DDPI 0x10000000 /* Disable CPUSHL */
#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
#define CACR_DDCM_P 0x04000000 /* No cache, precise */
#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
#define CACR_BEC 0x00080000 /* Enable branch cache */
#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
#define CACR_IEC 0x00008000 /* Enable instruction cache */
#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
#define ACR_BASE_POS 24 /* Address Base */
#define ACR_MASK_POS 16 /* Address Mask */
#define ACR_ENABLE 0x00008000 /* Enable address */
#define ACR_USER 0x00000000 /* User mode access only */
#define ACR_SUPER 0x00002000 /* Supervisor mode only */
#define ACR_ANY 0x00004000 /* Match any access mode */
#define ACR_CM_WT 0x00000000 /* Write through mode */
#define ACR_CM_CP 0x00000020 /* Copyback mode */
#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
#define ACR_WPROTECT 0x00000004 /* Write protect */
/****************************************************************************/
#endif /* m5407sim_h */
arch/m68k/include/asm/m54xxacr.h 0 → 100644
View file @ 6a7f6ec9
/*
* Bit definitions for the MCF54xx ACR and CACR registers.
*/
#ifndef m54xxacr_h
#define m54xxacr_h
/*
* Define the Cache register flags.
*/
#define CACR_DEC 0x80000000 /* Enable data cache */
#define CACR_DWP 0x40000000 /* Data write protection */
#define CACR_DESB 0x20000000 /* Enable data store buffer */
#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
#define CACR_DDCM_P 0x04000000 /* No cache, precise */
#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
#define CACR_BEC 0x00080000 /* Enable branch cache */
#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
#define CACR_IEC 0x00008000 /* Enable instruction cache */
#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
#define ACR_BASE_POS 24 /* Address Base */
#define ACR_MASK_POS 16 /* Address Mask */
#define ACR_ENABLE 0x00008000 /* Enable address */
#define ACR_USER 0x00000000 /* User mode access only */
#define ACR_SUPER 0x00002000 /* Supervisor mode only */
#define ACR_ANY 0x00004000 /* Match any access mode */
#define ACR_CM_WT 0x00000000 /* Write through mode */
#define ACR_CM_CP 0x00000020 /* Copyback mode */
#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
#define ACR_CM 0x00000060 /* Cache mode mask */
#define ACR_WPROTECT 0x00000004 /* Write protect */
#if defined(CONFIG_M5407)
#define ICACHE_SIZE 0x4000 /* instruction - 16k */
#define DCACHE_SIZE 0x2000 /* data - 8k */
#elif defined(CONFIG_M54xx)
#define ICACHE_SIZE 0x8000 /* instruction - 32k */
#define DCACHE_SIZE 0x8000 /* data - 32k */
#endif
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
#define CACHE_WAYS 4 /* 4 ways */
/*
* Version 4 cores have a true harvard style separate instruction
* and data cache. Enable data and instruction caches, also enable write
* buffers and branch accelerator.
*/
/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
/* use '+' instead of '|' for assembler's sake */
/* Enable data cache */
/* Enable data store buffer */
/* outside ACRs : No cache, precise */
/* Enable instruction+branch caches */
#if defined(CONFIG_M5407)
#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
#else
#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
#endif
#if defined(CONFIG_CACHE_COPYBACK)
#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
#else
#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
#endif
#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
#define ACR1_MODE 0
#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
#define ACR3_MODE 0
#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
/* Copyback cache mode must push dirty cache lines first */
#define CACHE_PUSH
#endif
#endif /* m54xxacr_h */
arch/m68k/include/asm/m548xgpt.h → arch/m68k/include/asm/m54xxgpt.h
View file @ 6a7f6ec9
/*
* File: m548xgpt.h
* Purpose: Register and bit definitions for the MCF548X
* File: m54xxgpt.h
* Purpose: Register and bit definitions for the MCF54XX
*
* Notes:
*
*/
#ifndef m548xgpt_h
#define m548xgpt_h
#ifndef m54xxgpt_h
#define m54xxgpt_h
/*********************************************************************
*
......@@ -87,4 +87,4 @@
/********************************************************************/
#endif /* m548xgpt_h */
#endif /* m54xxgpt_h */
arch/m68k/include/asm/m548xsim.h → arch/m68k/include/asm/m54xxsim.h
View file @ 6a7f6ec9
/*
* m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
* m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
*/
#ifndef m548xsim_h
#define m548xsim_h
#ifndef m54xxsim_h
#define m54xxsim_h
#define CPU_NAME "COLDFIRE(m54xx)"
#define CPU_INSTR_PER_JIFFY 2
#include <asm/m54xxacr.h>
#define MCFINT_VECBASE 64
......@@ -21,6 +26,14 @@
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
/*
* UART module.
*/
#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
/*
* Define system peripheral IRQ usage.
*/
......@@ -52,4 +65,4 @@
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
#endif /* m548xsim_h */
#endif /* m54xxsim_h */
arch/m68k/include/asm/mcfcache.h deleted 100644 → 0
View file @ c6fa63c6
/****************************************************************************/
/*
* mcfcache.h -- ColdFire CPU cache support code
*
* (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef __M68KNOMMU_MCFCACHE_H
#define __M68KNOMMU_MCFCACHE_H
/****************************************************************************/
/*
* The different ColdFire families have different cache arrangments.
* Everything from a small instruction only cache, to configurable
* data and/or instruction cache, to unified instruction/data, to
* harvard style separate instruction and data caches.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
/*
* Simple version 2 core cache. These have instruction cache only,
* we just need to invalidate it and enable it.
*/
.macro CACHE_ENABLE
movel #0x01000000,%d0 /* invalidate cache cmd */
movec %d0,%CACR /* do invalidate cache */
movel #0x80000100,%d0 /* setup cache mask */
movec %d0,%CACR /* enable cache */
.endm
#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
/*
* New version 2 cores have a configurable split cache arrangement.
* For now I am just enabling instruction cache - but ultimately I
* think a split instruction/data cache would be better.
*/
.macro CACHE_ENABLE
movel #0x01400000,%d0
movec %d0,%CACR /* invalidate cache */
nop
movel #0x0000c000,%d0 /* set SDRAM cached only */
movec %d0,%ACR0
movel #0x00000000,%d0 /* no other regions cached */
movec %d0,%ACR1
movel #0x80400100,%d0 /* configure cache */
movec %d0,%CACR /* enable cache */
nop
.endm
#endif /* CONFIG_M523x || CONFIG_M527x */
#if defined(CONFIG_M528x)
.macro CACHE_ENABLE
nop
movel #0x01000000, %d0
movec %d0, %CACR /* Invalidate cache */
nop
movel #0x0000c020, %d0 /* Set SDRAM cached only */
movec %d0, %ACR0
movel #0x00000000, %d0 /* No other regions cached */
movec %d0, %ACR1
movel #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
.endm
#endif /* CONFIG_M528x */
#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
/*
* The version 3 core cache. Oddly enough the version 2 core 5249
* has the same SDRAM and cache setup as the version 3 cores.
* This is a single unified instruction/data cache.
*/
.macro CACHE_ENABLE
movel #0x01000000,%d0 /* invalidate whole cache */
movec %d0,%CACR
nop
#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
#else
movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
#endif
movec %d0,%ACR0
movel #0x00000000,%d0 /* no other regions cached */
movec %d0,%ACR1
movel #0xa0000200,%d0 /* enable cache */
movec %d0,%CACR
nop
.endm
#endif /* CONFIG_M5249 || CONFIG_M5307 */
#if defined(CONFIG_M532x)
.macro CACHE_ENABLE
movel #0x01000000,%d0 /* invalidate cache cmd */
movec %d0,%CACR /* do invalidate cache */
nop
movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
movec %d0,%ACR0
movel #0x00000000,%d0 /* no other regions cached */
movec %d0,%ACR1
movel #0x80000200,%d0 /* setup cache mask */
movec %d0,%CACR /* enable cache */
nop
.endm
#endif /* CONFIG_M532x */
#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
/*
* Version 4 cores have a true harvard style separate instruction
* and data cache. Invalidate and enable cache, also enable write
* buffers and branch accelerator.
*/
.macro CACHE_ENABLE
movel #0x01040100,%d0 /* invalidate whole cache */
movec %d0,%CACR
nop
movel #0x000fc000,%d0 /* set SDRAM cached only */
movec %d0, %ACR0
movel #0x00000000,%d0 /* no other regions cached */
movec %d0, %ACR1
movel #0x000fc000,%d0 /* set SDRAM cached only */
movec %d0, %ACR2
movel #0x00000000,%d0 /* no other regions cached */
movec %d0, %ACR3
movel #0xb6088400,%d0 /* enable caches */
movec %d0,%CACR
nop
.endm
#endif /* CONFIG_M5407 */
#if defined(CONFIG_M520x)
.macro CACHE_ENABLE
move.l #0x01000000,%d0 /* invalidate whole cache */
movec %d0,%CACR
nop
move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
movec %d0,%ACR0
move.l #0x00000000,%d0 /* no other regions cached */
movec %d0,%ACR1
move.l #0x80400000,%d0 /* enable 8K instruction cache */
movec %d0,%CACR
nop
.endm
#endif /* CONFIG_M520x */
/****************************************************************************/
#endif /* __M68KNOMMU_MCFCACHE_H */
arch/m68k/include/asm/mcfsim.h
View file @ 6a7f6ec9
......@@ -41,8 +41,8 @@
#elif defined(CONFIG_M5407)
#include <asm/m5407sim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M548x)
#include <asm/m548xsim.h>
#elif defined(CONFIG_M54xx)
#include <asm/m54xxsim.h>
#endif
/****************************************************************************/
......
arch/m68k/include/asm/mcfuart.h
View file @ 6a7f6ec9
......@@ -12,49 +12,6 @@
#define mcfuart_h
/****************************************************************************/
/*
* Define the base address of the UARTS within the MBAR address
* space.
*/
#if defined(CONFIG_M5272)
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M520x)
#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
#elif defined(CONFIG_M532x)
#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
#elif defined(CONFIG_M548x)
#define MCFUART_BASE1 0x8600 /* on M548x */
#define MCFUART_BASE2 0x8700 /* on M548x */
#define MCFUART_BASE3 0x8800 /* on M548x */
#define MCFUART_BASE4 0x8900 /* on M548x */
#endif
#include <linux/serial_core.h>
#include <linux/platform_device.h>
......@@ -217,7 +174,7 @@ struct mcf_platform_uart {
#define MCFUART_URF_RXS 0xc0 /* Receiver status */
#endif
#if defined(CONFIG_M548x)
#if defined(CONFIG_M54xx)
#define MCFUART_TXFIFOSIZE 512
#elif defined(CONFIG_M5272)
#define MCFUART_TXFIFOSIZE 25
......
arch/m68k/include/asm/processor.h
View file @ 6a7f6ec9
......@@ -20,23 +20,26 @@
static inline unsigned long rdusp(void)
{
#ifdef CONFIG_COLDFIRE
#ifdef CONFIG_COLDFIRE_SW_A7
extern unsigned int sw_usp;
return sw_usp;
#else
unsigned long usp;
__asm__ __volatile__("move %/usp,%0" : "=a" (usp));
register unsigned long usp __asm__("a0");
/* move %usp,%a0 */
__asm__ __volatile__(".word 0x4e68" : "=a" (usp));
return usp;
#endif
}
static inline void wrusp(unsigned long usp)
{
#ifdef CONFIG_COLDFIRE
#ifdef CONFIG_COLDFIRE_SW_A7
extern unsigned int sw_usp;
sw_usp = usp;
#else
__asm__ __volatile__("move %0,%/usp" : : "a" (usp));
register unsigned long a0 __asm__("a0") = usp;
/* move %a0,%usp */
__asm__ __volatile__(".word 0x4e60" : : "a" (a0) );
#endif
}
......
arch/m68knommu/Kconfig
View file @ 6a7f6ec9
......@@ -75,6 +75,16 @@ config GENERIC_CLOCKEVENTS
config NO_IOPORT
def_bool y
config COLDFIRE_SW_A7
bool
default n
config HAVE_CACHE_SPLIT
bool
config HAVE_CACHE_CB
bool
source "init/Kconfig"
source "kernel/Kconfig.freezer"
......@@ -107,69 +117,90 @@ config M68360
config M5206
bool "MCF5206"
select COLDFIRE_SW_A7
help
Motorola ColdFire 5206 processor support.
config M5206e
bool "MCF5206e"
select COLDFIRE_SW_A7
help
Motorola ColdFire 5206e processor support.
config M520x
bool "MCF520x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
Freescale Coldfire 5207/5208 processor support.
config M523x
bool "MCF523x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
Freescale Coldfire 5230/1/2/4/5 processor support
config M5249
bool "MCF5249"
select COLDFIRE_SW_A7
help
Motorola ColdFire 5249 processor support.
config M5271
bool "MCF5271"
select HAVE_CACHE_SPLIT
help
Freescale (Motorola) ColdFire 5270/5271 processor support.
config M5272
bool "MCF5272"
select COLDFIRE_SW_A7
help
Motorola ColdFire 5272 processor support.
config M5275
bool "MCF5275"
select HAVE_CACHE_SPLIT
help
Freescale (Motorola) ColdFire 5274/5275 processor support.
config M528x
bool "MCF528x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
Motorola ColdFire 5280/5282 processor support.
config M5307
bool "MCF5307"
select COLDFIRE_SW_A7
select HAVE_CACHE_CB
help
Motorola ColdFire 5307 processor support.
config M532x
bool "MCF532x"
select HAVE_CACHE_CB
help
Freescale (Motorola) ColdFire 532x processor support.
config M5407
bool "MCF5407"
select COLDFIRE_SW_A7
select HAVE_CACHE_CB
help
Motorola ColdFire 5407 processor support.
config M547x
bool "MCF547x"
select HAVE_CACHE_CB
help
Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
config M548x
bool "MCF548x"
select HAVE_CACHE_CB
help
Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
......@@ -181,9 +212,14 @@ config M527x
select GENERIC_CLOCKEVENTS
default y
config M54xx
bool
depends on (M548x || M547x)
default y
config COLDFIRE
bool
depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x)
depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx)
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
default y
......@@ -230,6 +266,46 @@ config OLDMASK
Build support for the older revision ColdFire 5307 silicon.
Specifically this is the 1H55J mask revision.
if HAVE_CACHE_SPLIT
choice
prompt "Split Cache Configuration"
default CACHE_I
config CACHE_I
bool "Instruction"
help
Use all of the ColdFire CPU cache memory as an instruction cache.
config CACHE_D
bool "Data"
help
Use all of the ColdFire CPU cache memory as a data cache.
config CACHE_BOTH
bool "Both"
help
Split the ColdFire CPU cache, and use half as an instruction cache
and half as a data cache.
endchoice
endif
if HAVE_CACHE_CB
choice
prompt "Data cache mode"
default CACHE_WRITETHRU
config CACHE_WRITETHRU
bool "Write-through"
help
The ColdFire CPU cache is set into Write-through mode.
config CACHE_COPYBACK
bool "Copy-back"
help
The ColdFire CPU cache is set into Copy-back mode.
endchoice
endif
comment "Platform"
config PILOT3
......
arch/m68knommu/Makefile
View file @ 6a7f6ec9
......@@ -25,7 +25,7 @@ platform-$(CONFIG_M528x) := 528x
platform-$(CONFIG_M5307) := 5307
platform-$(CONFIG_M532x) := 532x
platform-$(CONFIG_M5407) := 5407
platform-$(CONFIG_M548x) := 548x
platform-$(CONFIG_M54xx) := 54xx
PLATFORM := $(platform-y)
board-$(CONFIG_PILOT) := pilot
......@@ -74,7 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire
cpuclass-$(CONFIG_M5307) := coldfire
cpuclass-$(CONFIG_M532x) := coldfire
cpuclass-$(CONFIG_M5407) := coldfire
cpuclass-$(CONFIG_M548x) := coldfire
cpuclass-$(CONFIG_M54xx) := coldfire
cpuclass-$(CONFIG_M68328) := 68328
cpuclass-$(CONFIG_M68EZ328) := 68328
cpuclass-$(CONFIG_M68VZ328) := 68328
......@@ -91,18 +91,18 @@ export PLATFORM BOARD MODEL CPUCLASS
# Some CFLAG additions based on specific CPU type.
#
cflags-$(CONFIG_M5206) := $(call cc-option,-mcpu=5206,-m5200)
cflags-$(CONFIG_M5206e) := $(call cc-option,-m5206e,-m5200)
cflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200)
cflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200)
cflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307)
cflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200)
cflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307)
cflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307)
cflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307)
cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200)
cflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307)
cflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200)
cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200)
cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200)
cflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
cflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
cflags-$(CONFIG_M68328) := -m68000
cflags-$(CONFIG_M68EZ328) := -m68000
cflags-$(CONFIG_M68VZ328) := -m68000
......
arch/m68knommu/kernel/setup.c
View file @ 6a7f6ec9
......@@ -55,55 +55,29 @@ void (*mach_halt)(void);
void (*mach_power_off)(void);
#ifdef CONFIG_M68328
#define CPU "MC68328"
#define CPU_NAME "MC68328"
#endif
#ifdef CONFIG_M68EZ328
#define CPU "MC68EZ328"
#define CPU_NAME "MC68EZ328"
#endif
#ifdef CONFIG_M68VZ328
#define CPU "MC68VZ328"
#define CPU_NAME "MC68VZ328"
#endif
#ifdef CONFIG_M68360
#define CPU "MC68360"
#define CPU_NAME "MC68360"
#endif
#if defined(CONFIG_M5206)
#define CPU "COLDFIRE(m5206)"
#ifndef CPU_NAME
#define CPU_NAME "UNKNOWN"
#endif
#if defined(CONFIG_M5206e)
#define CPU "COLDFIRE(m5206e)"
#endif
#if defined(CONFIG_M520x)
#define CPU "COLDFIRE(m520x)"
#endif
#if defined(CONFIG_M523x)
#define CPU "COLDFIRE(m523x)"
#endif
#if defined(CONFIG_M5249)
#define CPU "COLDFIRE(m5249)"
#endif
#if defined(CONFIG_M5271)
#define CPU "COLDFIRE(m5270/5271)"
#endif
#if defined(CONFIG_M5272)
#define CPU "COLDFIRE(m5272)"
#endif
#if defined(CONFIG_M5275)
#define CPU "COLDFIRE(m5274/5275)"
#endif
#if defined(CONFIG_M528x)
#define CPU "COLDFIRE(m5280/5282)"
#endif
#if defined(CONFIG_M5307)
#define CPU "COLDFIRE(m5307)"
#endif
#if defined(CONFIG_M532x)
#define CPU "COLDFIRE(m532x)"
#endif
#if defined(CONFIG_M5407)
#define CPU "COLDFIRE(m5407)"
#endif
#ifndef CPU
#define CPU "UNKNOWN"
/*
* Different cores have different instruction execution timings.
* The old/traditional 68000 cores are basically all the same, at 16.
* The ColdFire cores vary a little, their values are defined in their
* headers. We default to the standard 68000 value here.
*/
#ifndef CPU_INSTR_PER_JIFFY
#define CPU_INSTR_PER_JIFFY 16
#endif
extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end;
......@@ -208,7 +182,7 @@ void __init setup_arch(char **cmdline_p)
command_line[sizeof(command_line) - 1] = 0;
#endif /* CONFIG_UBOOT */
printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU "\n");
printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU_NAME "\n");
#ifdef CONFIG_UCDIMM
printk(KERN_INFO "uCdimm by Lineo, Inc. <www.lineo.com>\n");
......@@ -257,11 +231,6 @@ void __init setup_arch(char **cmdline_p)
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE-1] = 0;
#ifdef DEBUG
if (strlen(*cmdline_p))
printk(KERN_DEBUG "Command line: '%s'\n", *cmdline_p);
#endif
#if defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
......@@ -303,15 +272,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
char *cpu, *mmu, *fpu;
u_long clockfreq;
cpu = CPU;
cpu = CPU_NAME;
mmu = "none";
fpu = "none";
#ifdef CONFIG_COLDFIRE
clockfreq = (loops_per_jiffy * HZ) * 3;
#else
clockfreq = (loops_per_jiffy * HZ) * 16;
#endif
clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY;
seq_printf(m, "CPU:\t\t%s\n"
"MMU:\t\t%s\n"
......
arch/m68knommu/mm/Makefile
View file @ 6a7f6ec9
......@@ -2,4 +2,4 @@
# Makefile for the linux m68knommu specific parts of the memory manager.
#
obj-y += init.o fault.o memory.o kmap.o
obj-y += init.o kmap.o
arch/m68knommu/mm/fault.c deleted 100644 → 0
View file @ c6fa63c6
/*
* linux/arch/m68knommu/mm/fault.c
*
* Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
* Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
*
* Based on:
*
* linux/arch/m68k/mm/fault.c
*
* Copyright (C) 1995 Hamish Macdonald
*/
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <asm/system.h>
#include <asm/pgtable.h>
extern void die_if_kernel(char *, struct pt_regs *, long);
/*
* This routine handles page faults. It determines the problem, and
* then passes it off to one of the appropriate routines.
*
* error_code:
* bit 0 == 0 means no page found, 1 means protection fault
* bit 1 == 0 means read, 1 means write
*
* If this routine detects a bad access, it returns 1, otherwise it
* returns 0.
*/
asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
#ifdef DEBUG
printk(KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n",
regs->sr, regs->pc, address, error_code);
#endif
/*
* Oops. The kernel tried to access some bad page. We'll have to
* terminate things with extreme prejudice.
*/
if ((unsigned long) address < PAGE_SIZE)
printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
else
printk(KERN_ALERT "Unable to handle kernel access");
printk(KERN_ALERT " at virtual address %08lx\n", address);
die_if_kernel("Oops", regs, error_code);
do_exit(SIGKILL);
return 1;
}
arch/m68knommu/mm/kmap.c
View file @ 6a7f6ec9
......@@ -35,15 +35,6 @@ void iounmap(void *addr)
{
}
/*
* __iounmap unmaps nearly everything, so be careful
* it doesn't free currently pointer/page tables anymore but it
* wans't used anyway and might be added later.
*/
void __iounmap(void *addr, unsigned long size)
{
}
/*
* Set new cache mode for some kernel address space.
* The caller must push data for that range itself, if such data may already
......
arch/m68knommu/mm/memory.c deleted 100644 → 0
View file @ c6fa63c6
/*
* linux/arch/m68knommu/mm/memory.c
*
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
*
* Based on:
*
* linux/arch/m68k/mm/memory.c
*
* Copyright (C) 1995 Hamish Macdonald
*/
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <asm/segment.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
/*
* Map some physical address range into the kernel address space.
*/
unsigned long kernel_map(unsigned long paddr, unsigned long size,
int nocacheflag, unsigned long *memavailp )
{
return paddr;
}
arch/m68knommu/platform/548x/config.c → arch/m68knommu/platform/54xx/config.c
View file @ 6a7f6ec9
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/548x/config.c
* linux/arch/m68knommu/platform/54xx/config.c
*
* Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
*/
......@@ -15,13 +15,13 @@
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/m548xsim.h>
#include <asm/m54xxsim.h>
#include <asm/mcfuart.h>
#include <asm/m548xgpt.h>
#include <asm/m54xxgpt.h>
/***************************************************************************/
static struct mcf_platform_uart m548x_uart_platform[] = {
static struct mcf_platform_uart m54xx_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.irq = 64 + 35,
......@@ -40,20 +40,20 @@ static struct mcf_platform_uart m548x_uart_platform[] = {
},
};
static struct platform_device m548x_uart = {
static struct platform_device m54xx_uart = {
.name = "mcfuart",
.id = 0,
.dev.platform_data = m548x_uart_platform,
.dev.platform_data = m54xx_uart_platform,
};
static struct platform_device *m548x_devices[] __initdata = {
&m548x_uart,
static struct platform_device *m54xx_devices[] __initdata = {
&m54xx_uart,
};
/***************************************************************************/
static void __init m548x_uart_init_line(int line, int irq)
static void __init m54xx_uart_init_line(int line, int irq)
{
int rts_cts;
......@@ -72,18 +72,18 @@ static void __init m548x_uart_init_line(int line, int irq)
MCF_MBAR + MCF_PAR_PSC(line));
}
static void __init m548x_uarts_init(void)
static void __init m54xx_uarts_init(void)
{
const int nrlines = ARRAY_SIZE(m548x_uart_platform);
const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
int line;
for (line = 0; (line < nrlines); line++)
m548x_uart_init_line(line, m548x_uart_platform[line].irq);
m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
}
/***************************************************************************/
static void mcf548x_reset(void)
static void mcf54xx_reset(void)
{
/* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n");
......@@ -97,8 +97,8 @@ static void mcf548x_reset(void)
void __init config_BSP(char *commandp, int size)
{
mach_reset = mcf548x_reset;
m548x_uarts_init();
mach_reset = mcf54xx_reset;
m54xx_uarts_init();
}
/***************************************************************************/
......@@ -106,7 +106,7 @@ void __init config_BSP(char *commandp, int size)
static int __init init_BSP(void)
{
platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
return 0;
}
......
arch/m68knommu/platform/68328/ints.c
View file @ 6a7f6ec9
......@@ -179,8 +179,8 @@ void __init init_IRQ(void)
IMR = ~0;
for (i = 0; (i < NR_IRQS); i++) {
set_irq_chip(irq, &intc_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_chip(i, &intc_irq_chip);
set_irq_handler(i, handle_level_irq);
}
}
arch/m68knommu/platform/coldfire/Makefile
View file @ 6a7f6ec9
......@@ -14,7 +14,7 @@
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o
obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o
obj-$(CONFIG_M5206) += timers.o intc.o
obj-$(CONFIG_M5206e) += timers.o intc.o
obj-$(CONFIG_M520x) += pit.o intc-simr.o
......@@ -26,7 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o
obj-$(CONFIG_M5307) += timers.o intc.o
obj-$(CONFIG_M532x) += timers.o intc-simr.o
obj-$(CONFIG_M5407) += timers.o intc.o
obj-$(CONFIG_M548x) += sltimers.o intc-2.o
obj-$(CONFIG_M54xx) += sltimers.o intc-2.o
obj-y += pinmux.o gpio.o
extra-y := head.o
arch/m68knommu/platform/coldfire/cache.c 0 → 100644
View file @ 6a7f6ec9
/***************************************************************************/
/*
* cache.c -- general ColdFire Cache maintainence code
*
* Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/***************************************************************************/
#ifdef CACHE_PUSH
/***************************************************************************/
/*
* Use cpushl to push all dirty cache lines back to memory.
* Older versions of GAS don't seem to know how to generate the
* ColdFire cpushl instruction... Oh well, bit stuff it for now.
*/
void mcf_cache_push(void)
{
__asm__ __volatile__ (
"clrl %%d0\n\t"
"1:\n\t"
"movel %%d0,%%a0\n\t"
"2:\n\t"
".word 0xf468\n\t"
"addl %0,%%a0\n\t"
"cmpl %1,%%a0\n\t"
"blt 2b\n\t"
"addql #1,%%d0\n\t"
"cmpil %2,%%d0\n\t"
"bne 1b\n\t"
: /* No output */
: "i" (CACHE_LINE_SIZE),
"i" (DCACHE_SIZE / CACHE_WAYS),
"i" (CACHE_WAYS)
: "d0", "a0" );
}
/***************************************************************************/
#endif /* CACHE_PUSH */
/***************************************************************************/
arch/m68knommu/platform/coldfire/entry.S
View file @ 6a7f6ec9
......@@ -36,13 +36,16 @@
#include <asm/asm-offsets.h>
#include <asm/entry.h>
#ifdef CONFIG_COLDFIRE_SW_A7
/*
* Define software copies of the supervisor and user stack pointers.
*/
.bss
sw_ksp:
.long 0
sw_usp:
.long 0
#endif /* CONFIG_COLDFIRE_SW_A7 */
.text
......@@ -51,7 +54,6 @@ sw_usp:
.globl ret_from_exception
.globl ret_from_signal
.globl sys_call_table
.globl ret_from_interrupt
.globl inthandler
.globl fasthandler
......@@ -140,20 +142,7 @@ Luser_return:
jne Lwork_to_do /* still work to do */
Lreturn:
move #0x2700,%sr /* disable intrs */
movel sw_usp,%a0 /* get usp */
movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
movel %sp@(PT_OFF_FORMATVEC),%a0@- /* copy exception format/vector/sr */
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stk adj */
addql #8,%sp /* remove exception */
movel %sp,sw_ksp /* save ksp */
subql #8,sw_usp /* set exception */
movel sw_usp,%sp /* restore usp */
rte
RESTORE_USER
Lwork_to_do:
movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */
......@@ -191,31 +180,7 @@ ENTRY(inthandler)
jbsr do_IRQ /* call high level irq handler */
lea %sp@(8),%sp /* pop args off stack */
bra ret_from_interrupt /* this was fallthrough */
/*
* This is the fast interrupt handler (for certain hardware interrupt
* sources). Unlike the normal interrupt handler it just uses the
* current stack (doesn't care if it is user or kernel). It also
* doesn't bother doing the bottom half handlers.
*/
ENTRY(fasthandler)
SAVE_LOCAL
movew %sp@(PT_OFF_FORMATVEC),%d0
andl #0x03fc,%d0 /* mask out vector only */
movel %sp,%sp@- /* push regs arg */
lsrl #2,%d0 /* calculate real vector # */
movel %d0,%sp@- /* push vector number */
jbsr do_IRQ /* call high level irq handler */
lea %sp@(8),%sp /* pop args off stack */
RESTORE_LOCAL
ENTRY(ret_from_interrupt)
/* the fasthandler is confusing me, haven't seen any user */
jmp ret_from_exception
bra ret_from_exception
/*
* Beware - when entering resume, prev (the current task) is
......@@ -226,9 +191,8 @@ ENTRY(ret_from_interrupt)
*/
ENTRY(resume)
movel %a0, %d1 /* get prev thread in d1 */
movel sw_usp,%d0 /* save usp */
movel %d0,%a0@(TASK_THREAD+THREAD_USP)
RDUSP
movel %a2,%a0@(TASK_THREAD+THREAD_USP)
SAVE_SWITCH_STACK
movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */
......@@ -236,5 +200,5 @@ ENTRY(resume)
RESTORE_SWITCH_STACK
movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */
movel %a0, sw_usp
WRUSP
rts
arch/m68knommu/platform/coldfire/head.S
View file @ 6a7f6ec9
......@@ -3,7 +3,7 @@
/*
* head.S -- common startup code for ColdFire CPUs.
*
* (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>.
* (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>.
*/
/*****************************************************************************/
......@@ -13,7 +13,6 @@
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/coldfire.h>
#include <asm/mcfcache.h>
#include <asm/mcfsim.h>
#include <asm/thread_info.h>
......@@ -173,10 +172,27 @@ _start:
/*
* Now that we know what the memory is, lets enable cache
* and get things moving. This is Coldfire CPU specific.
* and get things moving. This is Coldfire CPU specific. Not
* all version cores have identical cache register setup. But
* it is very similar. Define the exact settings in the headers
* then the code here is the same for all.
*/
CACHE_ENABLE /* enable CPU cache */
movel #CACHE_INIT,%d0 /* invalidate whole cache */
movec %d0,%CACR
nop
movel #ACR0_MODE,%d0 /* set RAM region for caching */
movec %d0,%ACR0
movel #ACR1_MODE,%d0 /* anything else to cache? */
movec %d0,%ACR1
#ifdef ACR2_MODE
movel #ACR2_MODE,%d0
movec %d0,%ACR2
movel #ACR3_MODE,%d0
movec %d0,%ACR3
#endif
movel #CACHE_MODE,%d0 /* enable cache */
movec %d0,%CACR
nop
#ifdef CONFIG_ROMFS_FS
/*
......
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