Commit 6d599c8d authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'amlogic-dt64-2' of...

Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Pull "Amlogic 64-bit DT changes for v4.13 (round 2)" from Kevin Hilman:

- support new SPI controller driver
- several more leaf clocks exposed to DT
- New board: S905x LibreTech CC board

* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: meson-gxl: Add Libre Technology CC support
  dt-bindings: arm: amlogic: Add Libre Technology CC board
  dt-bindings: add Libre Technology vendor prefix
  ARM64: dts: meson-gx: Add SPICC nodes
  clk: meson-gxbb: un-export the CPU clock
  clk: meson-gxbb: expose UART clocks
  clk: meson-gxbb: expose SPICC gate
  clk: meson-gxbb: expose spdif master clock
  clk: meson-gxbb: expose i2s master clock
  clk: meson-gxbb: expose spdif clock gates
parents 2b29ca22 cd84aff1
...@@ -52,6 +52,7 @@ Board compatible values (alphabetically, grouped by SoC): ...@@ -52,6 +52,7 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p212" (Meson gxl s905x) - "amlogic,p212" (Meson gxl s905x)
- "hwacom,amazetv" (Meson gxl s905x) - "hwacom,amazetv" (Meson gxl s905x)
- "khadas,vim" (Meson gxl s905x) - "khadas,vim" (Meson gxl s905x)
- "libretech,cc" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d) - "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d) - "amlogic,p231" (Meson gxl s905d)
......
...@@ -173,6 +173,7 @@ lantiq Lantiq Semiconductor ...@@ -173,6 +173,7 @@ lantiq Lantiq Semiconductor
lego LEGO Systems A/S lego LEGO Systems A/S
lenovo Lenovo Group Ltd. lenovo Lenovo Group Ltd.
lg LG Corporation lg LG Corporation
libretech Shenzhen Libre Technology Co., Ltd
licheepi Lichee Pi licheepi Lichee Pi
linaro Linaro Limited linaro Linaro Limited
linux Linux-specific binding linux Linux-specific binding
......
...@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb ...@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
......
...@@ -304,6 +304,15 @@ i2c_C: i2c@87e0 { ...@@ -304,6 +304,15 @@ i2c_C: i2c@87e0 {
status = "disabled"; status = "disabled";
}; };
spicc: spi@8d80 {
compatible = "amlogic,meson-gx-spicc";
reg = <0x0 0x08d80 0x0 0x80>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spifc: spi@8c80 { spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>; reg = <0x0 0x08c80 0x0 0x80>;
......
...@@ -671,6 +671,13 @@ &sd_emmc_c { ...@@ -671,6 +671,13 @@ &sd_emmc_c {
clock-names = "core", "clkin0", "clkin1"; clock-names = "core", "clkin0", "clkin1";
}; };
&spicc {
clocks = <&clkc CLKID_SPICC>;
clock-names = "core";
resets = <&reset RESET_PERIPHS_SPICC>;
num-cs = <1>;
};
&spifc { &spifc {
clocks = <&clkc CLKID_SPI>; clocks = <&clkc CLKID_SPI>;
}; };
......
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Author: Jerome Brunet <jbrunet@baylibre.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905x-p212.dtsi"
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Technology CC";
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
leds {
compatible = "gpio-leds";
system {
label = "librecomputer:system-status";
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
default-state = "on";
panic-indicator;
};
blue {
label = "librecomputer:blue";
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
/*
* The following devices exists but are exposed on the general
* purpose GPIO header. End user may well decide to use those pins
* for another purpose
*/
&sd_emmc_a {
status = "disabled";
};
&uart_A {
status = "disabled";
};
&wifi32k {
status = "disabled";
};
...@@ -612,6 +612,13 @@ &sd_emmc_c { ...@@ -612,6 +612,13 @@ &sd_emmc_c {
clock-names = "core", "clkin0", "clkin1"; clock-names = "core", "clkin0", "clkin1";
}; };
&spicc {
clocks = <&clkc CLKID_SPICC>;
clock-names = "core";
resets = <&reset RESET_PERIPHS_SPICC>;
num-cs = <1>;
};
&spifc { &spifc {
clocks = <&clkc CLKID_SPI>; clocks = <&clkc CLKID_SPI>;
}; };
......
...@@ -171,7 +171,7 @@ ...@@ -171,7 +171,7 @@
* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
*/ */
#define CLKID_SYS_PLL 0 #define CLKID_SYS_PLL 0
/* CLKID_CPUCLK */ #define CLKID_CPUCLK 1
/* CLKID_HDMI_PLL */ /* CLKID_HDMI_PLL */
#define CLKID_FIXED_PLL 3 #define CLKID_FIXED_PLL 3
/* CLKID_FCLK_DIV2 */ /* CLKID_FCLK_DIV2 */
...@@ -191,12 +191,12 @@ ...@@ -191,12 +191,12 @@
#define CLKID_ISA 18 #define CLKID_ISA 18
#define CLKID_PL301 19 #define CLKID_PL301 19
#define CLKID_PERIPHS 20 #define CLKID_PERIPHS 20
#define CLKID_SPICC 21 /* CLKID_SPICC */
/* CLKID_I2C */ /* CLKID_I2C */
/* #define CLKID_SAR_ADC */ /* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24 #define CLKID_SMART_CARD 24
/* CLKID_RNG0 */ /* CLKID_RNG0 */
#define CLKID_UART0 26 /* CLKID_UART0 */
#define CLKID_SDHC 27 #define CLKID_SDHC 27
#define CLKID_STREAM 28 #define CLKID_STREAM 28
#define CLKID_ASYNC_FIFO 29 #define CLKID_ASYNC_FIFO 29
...@@ -209,7 +209,7 @@ ...@@ -209,7 +209,7 @@
/* CLKID_ETH */ /* CLKID_ETH */
#define CLKID_DEMUX 37 #define CLKID_DEMUX 37
/* CLKID_AIU_GLUE */ /* CLKID_AIU_GLUE */
#define CLKID_IEC958 39 /* CLKID_IEC958 */
/* CLKID_I2S_OUT */ /* CLKID_I2S_OUT */
#define CLKID_AMCLK 41 #define CLKID_AMCLK 41
#define CLKID_AIFIFO2 42 #define CLKID_AIFIFO2 42
...@@ -218,7 +218,7 @@ ...@@ -218,7 +218,7 @@
#define CLKID_ADC 45 #define CLKID_ADC 45
#define CLKID_BLKMV 46 #define CLKID_BLKMV 46
/* CLKID_AIU */ /* CLKID_AIU */
#define CLKID_UART1 48 /* CLKID_UART1 */
#define CLKID_G2D 49 #define CLKID_G2D 49
/* CLKID_USB0 */ /* CLKID_USB0 */
/* CLKID_USB1 */ /* CLKID_USB1 */
...@@ -238,7 +238,7 @@ ...@@ -238,7 +238,7 @@
/* CLKID_USB0_DDR_BRIDGE */ /* CLKID_USB0_DDR_BRIDGE */
#define CLKID_MMC_PCLK 66 #define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67 #define CLKID_DVIN 67
#define CLKID_UART2 68 /* CLKID_UART2 */
/* #define CLKID_SANA */ /* #define CLKID_SANA */
#define CLKID_VPU_INTR 70 #define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71 #define CLKID_SEC_AHB_AHB3_BRIDGE 71
...@@ -251,7 +251,7 @@ ...@@ -251,7 +251,7 @@
#define CLKID_GCLK_VENCI_INT 78 #define CLKID_GCLK_VENCI_INT 78
#define CLKID_DAC_CLK 79 #define CLKID_DAC_CLK 79
/* CLKID_AOCLK_GATE */ /* CLKID_AOCLK_GATE */
#define CLKID_IEC958_GATE 81 /* CLKID_IEC958_GATE */
#define CLKID_ENC480P 82 #define CLKID_ENC480P 82
#define CLKID_RNG1 83 #define CLKID_RNG1 83
#define CLKID_GCLK_VENCI_INT1 84 #define CLKID_GCLK_VENCI_INT1 84
...@@ -277,13 +277,13 @@ ...@@ -277,13 +277,13 @@
#define CLKID_MALI_1_DIV 104 #define CLKID_MALI_1_DIV 104
/* CLKID_MALI_1 */ /* CLKID_MALI_1 */
/* CLKID_MALI */ /* CLKID_MALI */
#define CLKID_CTS_AMCLK 107 /* CLKID_CTS_AMCLK */
#define CLKID_CTS_AMCLK_SEL 108 #define CLKID_CTS_AMCLK_SEL 108
#define CLKID_CTS_AMCLK_DIV 109 #define CLKID_CTS_AMCLK_DIV 109
#define CLKID_CTS_MCLK_I958 110 /* CLKID_CTS_MCLK_I958 */
#define CLKID_CTS_MCLK_I958_SEL 111 #define CLKID_CTS_MCLK_I958_SEL 111
#define CLKID_CTS_MCLK_I958_DIV 112 #define CLKID_CTS_MCLK_I958_DIV 112
#define CLKID_CTS_I958 113 /* CLKID_CTS_I958 */
#define NR_CLKS 114 #define NR_CLKS 114
......
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
#ifndef __GXBB_CLKC_H #ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H #define __GXBB_CLKC_H
#define CLKID_CPUCLK 1
#define CLKID_HDMI_PLL 2 #define CLKID_HDMI_PLL 2
#define CLKID_FCLK_DIV2 4 #define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5 #define CLKID_FCLK_DIV3 5
...@@ -13,24 +12,30 @@ ...@@ -13,24 +12,30 @@
#define CLKID_GP0_PLL 9 #define CLKID_GP0_PLL 9
#define CLKID_CLK81 12 #define CLKID_CLK81 12
#define CLKID_MPLL2 15 #define CLKID_MPLL2 15
#define CLKID_SPICC 21
#define CLKID_I2C 22 #define CLKID_I2C 22
#define CLKID_SAR_ADC 23 #define CLKID_SAR_ADC 23
#define CLKID_RNG0 25 #define CLKID_RNG0 25
#define CLKID_UART0 26
#define CLKID_SPI 34 #define CLKID_SPI 34
#define CLKID_ETH 36 #define CLKID_ETH 36
#define CLKID_AIU_GLUE 38 #define CLKID_AIU_GLUE 38
#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40 #define CLKID_I2S_OUT 40
#define CLKID_MIXER_IFACE 44 #define CLKID_MIXER_IFACE 44
#define CLKID_AIU 47 #define CLKID_AIU 47
#define CLKID_UART1 48
#define CLKID_USB0 50 #define CLKID_USB0 50
#define CLKID_USB1 51 #define CLKID_USB1 51
#define CLKID_USB 55 #define CLKID_USB 55
#define CLKID_HDMI_PCLK 63 #define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_USB0_DDR_BRIDGE 65
#define CLKID_UART2 68
#define CLKID_SANA 69 #define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77 #define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AOCLK_GATE 80 #define CLKID_AOCLK_GATE 80
#define CLKID_IEC958_GATE 81
#define CLKID_AO_I2C 93 #define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95 #define CLKID_SD_EMMC_B 95
...@@ -42,5 +47,8 @@ ...@@ -42,5 +47,8 @@
#define CLKID_MALI_1_SEL 103 #define CLKID_MALI_1_SEL 103
#define CLKID_MALI_1 105 #define CLKID_MALI_1 105
#define CLKID_MALI 106 #define CLKID_MALI 106
#define CLKID_CTS_AMCLK 107
#define CLKID_CTS_MCLK_I958 110
#define CLKID_CTS_I958 113
#endif /* __GXBB_CLKC_H */ #endif /* __GXBB_CLKC_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment