drm/omap: DMM/TILER support for OMAP4+ platform
Dynamic Memory Manager (DMM) is a hardware block in the OMAP4+ processor that contains at least one TILER instance. TILER, or Tiling and Isometric Lightweight Engine for Rotation, provides IOMMU capabilities through the use of a physical address translation table. The TILER also provides zero cost rotation and mirroring. The TILER provides both 1D and 2D access by providing different views or address ranges that can be used to access the physical memory that has been mapped in through the PAT. Access to the 1D view results in linear access to the underlying memory. Access to the 2D views result in tiled access to the underlying memory resulted in increased efficiency. The TILER address space is managed by a tiler container manager (TCM) and allocates the address space through the use of the Simple Tiler Allocation algorithm (SiTA). The purpose of the algorithm is to keep fragmentation of the address space as low as possible. Signed-off-by: Andy Gross <andy.gross@ti.com> Signed-off-by: Rob Clark <rob@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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