Commit 736da811 authored by Matt Roper's avatar Matt Roper

drm/i915: Use literal representation of cdclk tables

The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms.  We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabling new platforms.  Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.

v2: Fix comparison when finding best cdclk.

v3: Another logic fix for calc_cdclk.

v4:
 - Use named initializers for cdclk tables. (Ville)
 - Include refclk as a field in the table instead of adding all three
   ratios for each entry. (Ville)
 - Terminate tables with an empty entry to avoid needing to store the
   table size. (Ville)
 - Don't try so hard to return reasonable values from our lookup
   functions if we get impossible inputs; just WARN and return 0.
   (Ville)
 - Keep a bxt_ prefix on the lookup functions since they're still only
   used on bxt+ for now.  We can rename them later if we extend this
   table-based approach back to older platforms.  (Ville)

v5:
 - Fix cnl table's ratios for 24mhz refclk. (Ville)
 - Don't miss the named initializers on the cnl table. (Ville)
 - Represent refclk in table as u16 rather than u32. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190910161506.7158-1-matthew.d.roper@intel.com
parent 71dc367e
This diff is collapsed.
...@@ -15,6 +15,13 @@ struct intel_atomic_state; ...@@ -15,6 +15,13 @@ struct intel_atomic_state;
struct intel_cdclk_state; struct intel_cdclk_state;
struct intel_crtc_state; struct intel_crtc_state;
struct intel_cdclk_vals {
u16 refclk;
u32 cdclk;
u8 divider; /* CD2X divider * 2 */
u8 ratio;
};
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
void intel_cdclk_init(struct drm_i915_private *i915); void intel_cdclk_init(struct drm_i915_private *i915);
void intel_cdclk_uninit(struct drm_i915_private *i915); void intel_cdclk_uninit(struct drm_i915_private *i915);
......
...@@ -1420,6 +1420,9 @@ struct drm_i915_private { ...@@ -1420,6 +1420,9 @@ struct drm_i915_private {
/* The current hardware cdclk state */ /* The current hardware cdclk state */
struct intel_cdclk_state hw; struct intel_cdclk_state hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;
int force_min_cdclk; int force_min_cdclk;
} cdclk; } cdclk;
......
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