Commit 74e4ce6a authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula

drm/i915/glk: Split GLK DSI device ready functionality

This patch divides glk_dsi_device_ready() function into
two part. First part will program LP wake and MIPI DSI mode
to MIPI_CTRL reg using newly defined function glk_dsi_enable_io().
glk_dsi_enable_io() will be called from intel_dsi_pre_enable.
Second part will do remaining device ready activities using
the existing function glk_dsi_device_ready().
Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497340095-5877-1-git-send-email-madhav.chauhan@intel.com
parent f6262bda
...@@ -346,12 +346,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, ...@@ -346,12 +346,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
return true; return true;
} }
static void glk_dsi_device_ready(struct intel_encoder *encoder) static void glk_dsi_enable_io(struct intel_encoder *encoder)
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port; enum port port;
u32 tmp, val; u32 tmp;
/* Set the MIPI mode /* Set the MIPI mode
* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
...@@ -381,6 +381,14 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) ...@@ -381,6 +381,14 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
GLK_MIPIIO_PORT_POWERED, 20)) GLK_MIPIIO_PORT_POWERED, 20))
DRM_ERROR("MIPIO port is powergated\n"); DRM_ERROR("MIPIO port is powergated\n");
} }
}
static void glk_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
u32 val;
/* Wait for MIPI PHY status bit to set */ /* Wait for MIPI PHY status bit to set */
for_each_dsi_port(port, intel_dsi->ports) { for_each_dsi_port(port, intel_dsi->ports) {
...@@ -391,8 +399,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) ...@@ -391,8 +399,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
} }
/* Get IO out of reset */ /* Get IO out of reset */
tmp = I915_READ(MIPI_CTRL(PORT_A)); val = I915_READ(MIPI_CTRL(PORT_A));
I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED); I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
/* Get IO out of Low power state*/ /* Get IO out of Low power state*/
for_each_dsi_port(port, intel_dsi->ports) { for_each_dsi_port(port, intel_dsi->ports) {
...@@ -427,9 +435,9 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) ...@@ -427,9 +435,9 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
I915_WRITE(MIPI_DEVICE_READY(port), val); I915_WRITE(MIPI_DEVICE_READY(port), val);
tmp = I915_READ(MIPI_CTRL(port)); val = I915_READ(MIPI_CTRL(port));
tmp &= ~GLK_LP_WAKE; val &= ~GLK_LP_WAKE;
I915_WRITE(MIPI_CTRL(port), tmp); I915_WRITE(MIPI_CTRL(port), val);
} }
/* Wait for Stop state */ /* Wait for Stop state */
...@@ -811,6 +819,9 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, ...@@ -811,6 +819,9 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
/* Deassert reset */ /* Deassert reset */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
if (IS_GEMINILAKE(dev_priv))
glk_dsi_enable_io(encoder);
/* Put device in ready state (LP-11) */ /* Put device in ready state (LP-11) */
intel_dsi_device_ready(encoder); intel_dsi_device_ready(encoder);
......
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