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Commit 76138f94 authored by Russell King's avatar Russell King Committed by Gregory CLEMENT
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ARM: dts: armada388-clearfog: split clearfog DTS file 

There are two versions of the clearfog - a base and a pro model.  The
base model has an additional PHY on eth1, replacing the DSA switch on
the pro model.  MPP assignments are slightly different.  The base model
also omits the second PCIe, and footprint for a PIC microcontroller.

In order to cater for these differences, move all the existing clearfog
support to a dtsi file before starting to modify it, to make the
following changes more clear.
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 77fb9c04
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Showing with 427 additions and 376 deletions
arch/arm/boot/dts/armada-388-clearfog.dts
View file @ 76138f94
/*
* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
* Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*
......@@ -47,384 +47,10 @@
*/
/dts-v1/;
#include "armada-388.dtsi"
#include "armada-38x-solidrun-microsom.dtsi"
#include "armada-388-clearfog.dtsi"
/ {
model = "SolidRun Clearfog A1";
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
ethernet2 = &eth1;
ethernet3 = &eth2;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
soc {
internal-regs {
ethernet@30000 {
phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <1>;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@34000 {
phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <3>;
bm,pool-short = <1>;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
i2c@11000 {
/* Is there anything on this? */
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
* 1-CON3 PERST#
* 2-CON2 PERST#
* 3-CON3 W_DISABLE
* 4-CON2 CLKREQ#
* 5-USB3 overcurrent
* 6-USB3 power
* 7-CON2 W_DISABLE
* 8-JP4 P1
* 9-JP4 P4
* 10-JP4 P5
* 11-m.2 DEVSLP
* 12-SFP_LOS
* 13-SFP_TX_FAULT
* 14-SFP_TX_DISABLE
* 15-SFP_MOD_DEF0
*/
expander0: gpio-expander@20 {
/*
* This is how it should be:
* compatible = "onnn,pca9655",
* "nxp,pca9555";
* but you can't do this because of
* the way I2C works.
*/
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
pcie1_0_clkreq {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie1.0-clkreq";
};
pcie1_0_w_disable {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-w-disable";
};
pcie2_0_clkreq {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie2.0-clkreq";
};
pcie2_0_w_disable {
gpio-hog;
gpios = <7 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie2.0-w-disable";
};
usb3_ilimit {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
usb3_power {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb3-power";
};
m2_devslp {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "m.2 devslp";
};
sfp_los {
/* SFP loss of signal */
gpio-hog;
gpios = <12 GPIO_ACTIVE_HIGH>;
input;
line-name = "sfp-los";
};
sfp_tx_fault {
/* SFP laser fault */
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
input;
line-name = "sfp-tx-fault";
};
sfp_tx_disable {
/* SFP transmit disable */
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "sfp-tx-disable";
};
sfp_mod_def0 {
/* SFP module present */
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
input;
line-name = "sfp-mod-def0";
};
};
/* The MCP3021 is 100kHz clock only */
mikrobus_adc: mcp3021@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
/* Also something at 0x64 */
};
i2c@11100 {
/*
* Routed to SFP, mikrobus, and PCIe.
* SFP limits this to 100kHz, and requires
* an AT24C01A/02/04 with address pins tied
* low, which takes addresses 0x50 and 0x51.
* Mikrobus doesn't specify beyond an I2C
* bus being present.
* PCIe uses ARP to assign addresses, or
* 0x63-0x64.
*/
clock-frequency = <100000>;
pinctrl-0 = <&clearfog_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
pinctrl@18000 {
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
marvell,pins = "mpp46";
marvell,function = "ref";
};
clearfog_dsa0_pins: clearfog-dsa0-pins {
marvell,pins = "mpp23", "mpp41";
marvell,function = "gpio";
};
clearfog_i2c1_pins: i2c1-pins {
/* SFP, PCIe, mSATA, mikrobus */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
marvell,pins = "mpp20";
marvell,function = "gpio";
};
clearfog_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp55";
marvell,function = "spi1";
};
mikro_pins: mikro-pins {
/* int: mpp22 rst: mpp29 */
marvell,pins = "mpp22", "mpp29";
marvell,function = "gpio";
};
mikro_spi_pins: mikro-spi-pins {
marvell,pins = "mpp43";
marvell,function = "spi1";
};
mikro_uart_pins: mikro-uart-pins {
marvell,pins = "mpp24", "mpp25";
marvell,function = "ua1";
};
rear_button_pins: rear-button-pins {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
};
sata@a8000 {
/* pinctrl? */
status = "okay";
};
sata@e0000 {
/* pinctrl? */
status = "okay";
};
sdhci@d8000 {
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
pinctrl-0 = <&microsom_sdhci_pins
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
wp-inverted;
};
serial@12100 {
/* mikrobus uart */
pinctrl-0 = <&mikro_uart_pins>;
pinctrl-names = "default";
status = "okay";
};
usb@58000 {
/* CON3, nearest power. */
status = "okay";
};
usb3@f0000 {
/* CON2, nearest CPU, USB2 only. */
status = "okay";
};
usb3@f8000 {
/* CON7 */
status = "okay";
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
pcie@2,0 {
/* Port 1, Lane 0. CON3, nearest power. */
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@3,0 {
/* Port 2, Lane 0. CON2, nearest CPU. */
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
dsa@0 {
compatible = "marvell,dsa";
dsa,ethernet = <&eth1>;
dsa,mii-bus = <&mdio>;
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
pinctrl-names = "default";
#address-cells = <2>;
#size-cells = <0>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4 0>;
port@0 {
reg = <0>;
label = "lan5";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
};
port@6 {
/* 88E1512 external phy */
reg = <6>;
label = "lan6";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
pinctrl-names = "default";
button_0 {
/* The rear SW3 button */
label = "Rear Button";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
};
};
&spi1 {
/*
* Add SPI CS pins for clearfog:
* CS0: W25Q32 (not populated on uSOM)
* CS1:
* CS2: mikrobus
*/
pinctrl-0 = <&spi1_pins
&clearfog_spi1_cs_pins
&mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/armada-388-clearfog.dtsi 0 → 100644
View file @ 76138f94
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