drm/amd/amdgpu: Correct whitespace in SI DPM code

Replace 8 spaces with tabs, correct {} braces, etc.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/si_dpm.c

@@ -2147,7 +2147,7 @@ static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
 	si_pi->enable_dte = false;
 
 	if (si_pi->powertune_data->enable_powertune_by_default) {
-		ni_pi->enable_power_containment= true;
+		ni_pi->enable_power_containment = true;
 		ni_pi->enable_cac = true;
 		if (si_pi->dte_data.enable_dte_by_default) {
 			si_pi->enable_dte = true;
@@ -2426,13 +2426,12 @@ static int si_populate_power_containment_values(struct amdgpu_device *adev,
 
 		if ((max_ps_percent == 0) ||
 		    (prev_sclk == max_sclk) ||
-		    disable_uvd_power_tune) {
+		    disable_uvd_power_tune)
 			min_sclk = max_sclk;
-		} else if (i == 1) {
+		else if (i == 1)
 			min_sclk = prev_sclk;
-		} else {
+		else
 			min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
-		}
 
 		if (min_sclk < state->performance_levels[0].sclk)
 			min_sclk = state->performance_levels[0].sclk;
@@ -2632,7 +2631,6 @@ static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
 	u32 i;
 	u32 v0_loadline;
 
-
 	if (table == NULL)
 		return -EINVAL;
 
@@ -3219,10 +3217,9 @@ static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
 {
 	unsigned int i;
 
-        for (i = 0; i < table->count; i++) {
+	for (i = 0; i < table->count; i++)
 		if (voltage <= table->entries[i].value)
 			return table->entries[i].value;
-        }
 
 	return table->entries[table->count - 1].value;
 }
@@ -4367,14 +4364,11 @@ static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
 static int si_upload_firmware(struct amdgpu_device *adev)
 {
 	struct si_power_info *si_pi = si_get_pi(adev);
-	int ret;
 
 	si_reset_smc(adev);
 	si_stop_smc_clock(adev);
 
-	ret = si_load_smc_ucode(adev, si_pi->sram_end);
-
-	return ret;
+	return si_load_smc_ucode(adev, si_pi->sram_end);
 }
 
 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
@@ -4938,9 +4932,7 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev,
 
 	reg = CG_R(0xffff) | CG_L(0);
 	table->initialState.levels[0].aT = cpu_to_be32(reg);
-
 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
-
 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
 
 	if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
@@ -5771,10 +5763,8 @@ static int si_upload_sw_state(struct amdgpu_device *adev,
 	if (ret)
 		return ret;
 
-	ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
+	return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
 				    state_size, si_pi->sram_end);
-
-	return ret;
 }
 
 static int si_upload_ulv_state(struct amdgpu_device *adev)
@@ -6184,12 +6174,10 @@ static int si_upload_mc_reg_table(struct amdgpu_device *adev,
 
 	si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
 
-
 	return si_copy_bytes_to_smc(adev, address,
 				    (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
 				    sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
 				    si_pi->sram_end);
-
 }
 
 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
@@ -6525,25 +6513,17 @@ static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
 	fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
 	fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
 	fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
-
 	fan_table.slope1 = cpu_to_be16(slope1);
 	fan_table.slope2 = cpu_to_be16(slope2);
-
 	fan_table.fdo_min = cpu_to_be16(fdo_min);
-
 	fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
-
 	fan_table.hys_up = cpu_to_be16(1);
-
 	fan_table.hys_slope = cpu_to_be16(1);
-
 	fan_table.temp_resp_lim = cpu_to_be16(5);
-
 	reference_clock = amdgpu_asic_get_xclk(adev);
 
 	fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
 						reference_clock) / 1600);
-
 	fan_table.fdo_max = cpu_to_be16((u16)duty100);
 
 	tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
@@ -6916,9 +6896,7 @@ static int si_dpm_enable(struct amdgpu_device *adev)
 	si_start_dpm(adev);
 
 	si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
-
 	si_thermal_start_thermal_controller(adev);
-
 	ni_update_current_ps(adev, boot_ps);
 
 	return 0;
@@ -6972,7 +6950,6 @@ static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
 	struct amdgpu_ps *new_ps = &requested_ps;
 
 	ni_update_requested_ps(adev, new_ps);
-
 	si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
 
 	return 0;